WO2018216338A1

WO2018216338A1 - Driver circuit

Info

Publication number: WO2018216338A1
Application number: PCT/JP2018/011739
Authority: WO
Inventors: 稔充 ▲高▼上; 邦彦松田
Original assignee: 株式会社デンソー
Priority date: 2017-05-25
Filing date: 2018-03-23
Publication date: 2018-11-29
Also published as: JP2018201063A; JP6787252B2

Abstract

A driver circuit (1, 51, 61, 71, 81, 91) is provided with: two switching elements (Q1, Q2) connected in series between a pair of power supply lines (L1, L2), to which a power supply voltage is supplied; and a drive unit (2) that complementarily drives the two switching elements corresponding to an input signal. The driver circuit supplies an output voltage to a subject to be driven, said output voltage having been outputted from an output node (No) connected to an interconnection point between the two switching elements. The high-potential-side switching element (Q1) is an N channel type MOS transistor. The driver circuit is provided with: a voltage limiting unit (3) that limits the gate voltage of the high-potential-side switching element to a predetermined clamp voltage; a potential fixing resistor (4) connected between the gate and the source of the high-potential-side switching element; and a leak suppressing unit (5, 52, 62, 72, 82, 92) that suppresses occurrence of leak current flowing from the gate of the high-potential-side switching element to the output node.

Description

Driver circuit

Cross-reference of related applications

This application is based on Japanese Application No. 2017-103604 filed on May 25, 2017, the contents of which are incorporated herein by reference.

The present disclosure relates to a driver circuit that supplies an output voltage to a drive target.

The switching element that constitutes the motor drive circuit, the switching element that functions as a power relay that cuts off the power supply to the control circuit, the driver circuit that drives the switching element that constitutes the charge pump circuit, etc. A voltage is output (see, for example, Patent Document 1).

Here, when the power supply voltage is a voltage having a relatively large fluctuation range such as a voltage of a battery mounted on the vehicle, the following problem may occur. That is, in the above configuration, the output voltage of the driver circuit increases as the power supply voltage increases, and therefore, when the power supply voltage increases greatly, there is a possibility that it exceeds the withstand voltage of the switching element serving as a load.

As a countermeasure against such a problem, an N-channel MOS transistor is used as a high-side switching element that constitutes the output stage of the driver circuit, and the gate voltage is limited to an arbitrary voltage or less. It is considered. According to such a configuration, even when the power supply voltage greatly increases, the output voltage is limited to a voltage equal to or lower than a desired voltage value regardless of the increase.

JP 2010-169102 A

In the above configuration, a resistor is provided between the gate and source of the MOS transistor for fixing the potential when the MOS transistor is turned off. For this reason, in the above configuration, a leakage current flows to the output node of the driver circuit through the resistor during the period when the MOS transistor is turned on, and the output voltage rises from the target value due to the leakage current. .

An object of the present disclosure is to provide a driver circuit that can suppress an increase in output voltage caused by a leakage current while limiting the output voltage to a desired voltage.

In one embodiment of the present disclosure, a driver circuit includes two switching elements connected in series between a pair of power supply lines to which a power supply voltage is supplied, and a driving unit that complementarily drives the two switching elements according to an input signal The output voltage output from the output node connected to the interconnection point of the two switching elements is supplied to the drive target. Of the two switching elements, the switching element on the high potential side is an N-channel MOS transistor. The driver circuit includes a voltage limiting unit that limits the gate voltage of the switching element on the high potential side to a predetermined clamp voltage. According to such a configuration, even when the power supply voltage greatly increases, the output voltage can be limited to a voltage equal to or lower than a desired voltage value regardless of the increase.

The driver circuit also includes a potential fixing resistor connected between the gate and source of the switching element on the high potential side. As a result, when the switching element on the high potential side is driven off, the switching element can be reliably turned off. Further, the driver circuit includes a leak suppression unit that suppresses the generation of a leak current that flows from the gate of the switching element on the high potential side to the output node. According to such a configuration, the leakage current flowing to the output node via the potential fixing resistor or the like can be kept low during the period in which the switching element on the high potential side is turned on. Therefore, according to the above configuration, it is possible to suppress an increase in the output voltage due to the leakage current while limiting the output voltage to a desired voltage.

Further, in one aspect of the present disclosure, in the driver circuit, the leak suppression unit suppresses generation of the leak current by executing a current extracting operation of extracting a predetermined current from the output node. According to such a configuration, although the current flows to the output node through the potential fixing resistor during the period when the switching element on the high potential side is turned on, the current is caused by the current extraction operation by the leak suppression unit. Since it is pulled out, the leakage current flowing out from the output node can be kept low. Therefore, according to the above configuration, it is possible to reliably suppress an increase in output voltage due to a leakage current flowing through the potential fixing resistor.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a diagram schematically showing the configuration of the driver circuit according to the first embodiment. FIG. 2 is a diagram schematically showing a configuration of a conventional driver circuit. FIG. 3 is a timing chart schematically showing the output voltage when the on-drive period is short. FIG. 4 is a timing chart schematically showing the output voltage when the on-drive period is long. FIG. 5 is a first diagram illustrating a specific application example of the driver circuit according to the first embodiment. FIG. 6 is a second diagram illustrating a specific application example of the driver circuit according to the first embodiment. FIG. 7 is a third diagram illustrating a specific application example of the driver circuit according to the first embodiment. FIG. 8 is a diagram schematically illustrating the configuration of the driver circuit according to the second embodiment. FIG. 9 is a diagram schematically illustrating the configuration of the driver circuit according to the third embodiment. FIG. 10 is a diagram schematically illustrating the configuration of the driver circuit according to the fourth embodiment. FIG. 11 is a diagram schematically illustrating the configuration of the driver circuit according to the fifth embodiment. FIG. 12 is a diagram schematically illustrating the configuration of the driver circuit according to the sixth embodiment.

Hereinafter, a plurality of embodiments will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS.

A driver circuit 1 shown in FIG. 1 is provided, for example, in an electronic control device mounted on a vehicle and drives a load connected to an output node No. Although not shown in FIG. 1, examples of the load to be driven by the driver circuit 1 include a MOS transistor used in a motor drive circuit or the like.

The driver circuit 1 includes transistors Q1 and Q2, a drive unit 2 that drives the transistors Q1 and Q2, a Zener diode 3, a potential fixing resistor 4, a leak suppression unit 5, and the like. In the present embodiment, the driver circuit 1 is configured as, for example, an ASIC (Application Specific Integrated Circuit).

A power supply voltage VS is supplied to the driver circuit 1 via a pair of power supply lines L1 and L2. In this case, the power supply voltage VS is a battery voltage supplied from a battery mounted on the vehicle, and its fluctuation range is relatively large. The transistors Q1 and Q2 are N-channel MOS transistors and correspond to switching elements.

The drain of the transistor Q1 is connected to the high potential side power supply line L1 to which the power supply voltage VS is applied, and the source thereof is connected to the drain of the transistor Q2. The source of the transistor Q2 is connected to the low potential side power supply line L2 to which the reference potential (= 0V) of the circuit is applied. Thus, the transistors Q1 and Q2 are connected in series between the pair of power supply lines L1 and L2. The transistor Q1 corresponds to a switching element on the high potential side. The interconnection point of the transistors Q1 and Q2 is connected to the output node No, and the output voltage Vo output from the output node No is supplied to the load to be driven.

The driving unit 2 includes transistors Q3 and Q4, inverting buffers 6 and

current sources

7 and 8 which are N channel type MOS transistors. The drain of the transistor Q3 is connected to the power supply line L1 through the current source 7, and the source thereof is connected to the power supply line L2. The drain of the transistor Q4 is connected to the power supply line L1 through the current source 8, and the source thereof is connected to the power supply line L2.

The inverting buffer 6 receives an input signal Si given from the outside through the input node Ni, and outputs the inverted signal. The gate of the transistor Q3 is connected to the output terminal of the inverting buffer 6. The gate of the transistor Q4 is connected to the input node Ni. The drain of the transistor Q3 is connected to the gate of the transistor Q1. The drain of the transistor Q4 is connected to the gate of the transistor Q2.

With this configuration, the drive unit 2 drives the transistors Q1 and Q2 in a complementary manner in accordance with the input signal Si. Specifically, the drive unit 2 drives the transistor Q1 on and drives the transistor Q2 off while the input signal Si is at a high level (for example, 5 V). Further, the drive unit 2 drives the transistor Q1 off and the transistor Q2 on while the input signal Si is at a low level (eg, 0 V).

The cathode of the Zener diode 3 is connected to the gate of the transistor Q1, and the anode thereof is connected to the power line L2. The Zener diode 3 limits the gate voltage of the transistor Q1 to a predetermined clamp voltage, and corresponds to a voltage limiting unit. In this case, the clamp voltage is the Zener voltage Vz of the Zener diode 3. In the present embodiment, the Zener voltage Vz is a voltage value lower than the steady value of the power supply voltage VS.

According to such a configuration, the gate voltage of the transistor Q1 during the period in which the transistor Q1 is turned on has a voltage value equal to or lower than the Zener voltage Vz without being affected by fluctuations in the power supply voltage VS. Therefore, according to the above configuration, even when the power supply voltage VS is greatly increased, the output voltage Vo can be limited to the limit voltage VL expressed by the following equation (1) regardless of the increase. However, the threshold voltage of the transistor Q1 is Vt.
VL = Vz−Vt (1)

As described above, the Zener voltage Vz of the Zener diode 3 is a voltage value smaller than the steady value of the power supply voltage VS. Therefore, the target value of the output voltage Vo of the driver circuit 1, that is, the target output voltage, is a voltage that is lower than the Zener voltage Vz by the threshold voltage Vt, that is, the same voltage as the limit voltage VL described above.

Note that the limit voltage VL may vary depending on the temperature characteristics of the Zener diode 3. Therefore, the specifications (temperature characteristics and Zener voltage Vz) of the Zener diode 3 are selected so that the output voltage Vo does not exceed the withstand voltage of the elements constituting the load of the supply destination in the operating temperature range of the driver circuit 1. There is a need.

The potential fixing resistor 4 is connected between the gate and source of the transistor Q1. The potential fixing resistor 4 is provided to fix the gate-source voltage to a voltage lower than the threshold voltage Vt and reliably maintain the off state when the transistor Q1 is driven off. In such a configuration, there is a possibility that a minute leak current flows from the gate of the transistor Q1 to the source of the transistor Q1, that is, the output node No, via the potential fixing resistor 4 during the period when the transistor Q1 is turned on. The current value IL of such a leakage current is determined from the threshold voltage Vt of the transistor Q1 and the resistance value Ra of the potential fixing resistor 4, as shown in the following equation (2).
IL = Vt / Ra (2)

The leak suppression unit 5 is provided to suppress the occurrence of such a leak current, and includes a transistor Q5 that is an N-channel MOS transistor and a current source 9. The drain of the transistor Q5 is connected to the output node No via the current source 9, and the source thereof is connected to the power supply line L2. The gate of the transistor Q5 is connected to the input node Ni.

In the above configuration, the current source 9 corresponds to a load connected between the output node No and the power supply line L2. The transistor Q5 corresponds to a switch connected in series with the current source 9 between the output node No and the power supply line L2.

According to such a configuration, during a period when the input signal Si is at a high level, that is, during a period in which the transistor Q1 is turned on, the transistor Q5 is turned on, thereby providing a load between the output node No and the power supply line L2. A current source 9 is connected. Therefore, a predetermined current corresponding to the current value of the current source 9 is drawn from the output node No to the power supply line L2 while the transistor Q1 is turned on.

By performing such a current extraction operation by the leak suppression unit 5, the occurrence of a leak current flowing from the gate of the transistor Q1 to the output node No can be suppressed. In the present embodiment, the current value of the current source 9 is a value equal to or greater than the current value IL of the leakage current expressed by the above equation (2), specifically, a current value obtained by adding a predetermined margin to the current value IL. Is set.

Next, the operation of the above configuration will be described with reference to FIG.
[1] Operation during a period when the input signal Si is at low level When the input signal Si is at low level, the transistor Q3 is turned on and the transistor Q4 is turned off. As a result, the transistor Q1 is driven off and the transistor Q2 is driven on. Therefore, during the period when the input signal Si is at the low level, the output voltage Vo is 0 V, which is the potential of the power supply line L2. Further, during this period, the transistor Q5 is turned off, so that the current drawing operation by the leak suppression unit 5 is not executed.

[2] Operation during a period when the input signal Si is at high level When the input signal Si is at high level, the transistor Q3 is turned off and the transistor Q4 is turned on. As a result, the transistor Q1 is driven on and the transistor Q2 is driven off. Therefore, during the period when the input signal Si is at the high level, the output voltage Vo is a voltage lower than the gate voltage of the transistor Q1 by the threshold voltage Vt. At this time, when the power supply voltage VS is a steady value or a voltage value higher than the steady value, the output voltage Vo becomes a target value, that is, the limit voltage VL shown in the above equation (1).

In this period, since the transistor Q5 is turned on, the current extraction operation by the leak suppression unit 5 is executed. Therefore, the generation of a minute leak current that flows from the gate of transistor Q1 to output node No is suppressed.

According to this embodiment described above, the following effects can be obtained.
In the configuration in which the leak suppression unit 5 is omitted from the driver circuit 1 as in the driver circuit 21 shown in FIG. 2 (hereinafter referred to as a conventional configuration), the following problem occurs. That is, in the conventional configuration, during the period in which the transistor Q1 is turned on (hereinafter referred to as the on drive period), the leakage current IL flows from the gate of the transistor Q1 to the output node No via the potential fixing resistor 4, Due to the current IL, there arises a problem that the output voltage Vo rises from the target value.

However, since the leakage current IL is a very small current, when the on-drive period is a relatively short period, as shown by a dotted line in FIG. 3, the increase in the output voltage Vo in the on-drive period is relatively small. In particular, when a MOS transistor serving as a load is switched at a high speed, the ON drive period is also shortened, so that the increase in the output voltage Vo is very small. Therefore, in such a case, the increase of the output voltage Vo caused by the leakage current IL does not become a big problem. Note that the time Ta in FIG. 3 and FIG. 4 to be described later is described for comparing the lengths of the respective ON drive periods, and indicates the same time.

However, when the ON drive period becomes a relatively long period, for example, at the time of initial check of the circuit or at the time of failure, the output voltage Vo gradually increases due to the leakage current IL as shown by the dotted line in FIG. The voltage value is about the same as the gate voltage Vg of the transistor Q1. As described above, when the output voltage Vo rises higher than the target value, for example, a voltage exceeding the withstand voltage is applied to the element constituting the load, and there is a possibility that the element may be damaged. In particular, when the Zener voltage Vz fluctuates in a higher direction with temperature fluctuation, such a problem may become more apparent.

On the other hand, the driver circuit 1 of the present embodiment includes a leak suppression unit 5 that suppresses the occurrence of a leak current flowing from the gate of the transistor Q1 to the output node No. According to such a configuration, the leakage current flowing to the output node No via the potential fixing resistor 4 can be kept low during the period in which the transistor Q1 is turned on.

In the driver circuit 1, the leak suppression unit 5 suppresses the generation of leak current by executing a current extraction operation for extracting a predetermined current from the output node No. According to such a configuration, although the current flows toward the output node No through the potential fixing resistor 4 during the period when the transistor Q1 is turned on, the current is extracted by the current extraction operation by the leak suppression unit 5. Therefore, the leakage current flowing out from the output node No can be suppressed low.

As described above, in the driver circuit 1 according to the present embodiment, the generation of the leakage current flowing through the potential fixing resistor 4 can be suppressed, so that the increase in the output voltage Vo resulting therefrom can be reliably suppressed. . As a result, in the driver circuit 1 according to the present embodiment, the output voltage Vo is maintained at the target value (= Vg−Vt) regardless of the length of the ON drive period, as shown by the one-dot chain line in FIGS. Is done. Therefore, according to the present embodiment, it is possible to obtain an excellent effect that it is possible to suppress an increase in the output voltage Vo due to the leakage current while limiting the output voltage Vo to a desired voltage.

Further, the leak suppression unit 5 of the present embodiment includes a current source 9 connected between the output node No and the power supply line L2. The current value of the current source 9 is set to a current value equal to or greater than the current value of the leakage current. In this way, when the current suppressing operation is performed, the leakage suppressing unit 5 can always extract a current equal to or higher than the leakage current, and as a result, the output voltage Vo caused by the leakage current can be reliably increased (floated). It becomes possible to suppress.

Furthermore, the leakage suppression unit 5 of this embodiment includes a transistor Q5 connected in series between the output node No and the power supply line L2 together with the current source 9. In this way, by turning off the transistor Q5, the current source 9 can be disconnected from between the output node No and the power supply line L2, and the following effects are obtained.

That is, there is a possibility that the gate voltage of the transistor Q1 is slightly higher than 0V because the on-resistance of the transistor Q3 is high, for example, during a period when the input signal Si is at a low level. For this reason, in the configuration in which the current source 9 is always connected between the output node No and the power supply line L2, the output voltage Vo is not completely 0V during the period when the input signal Si is at the low level, and the transistor Q1 A voltage obtained by dividing the gate voltage by the potential fixing resistor 4 and the current source 9 is output.

On the other hand, in this embodiment, since the transistor Q5 is turned off while the input signal Si is at a low level, the current source 9 is disconnected from the output node No and the power supply line L2. Even if the voltage is higher than 0V, the output voltage Vo becomes 0V and there is no possibility that a minute voltage is output.

In addition, the leakage inspection of the transistor Q2 may be performed in the screening of the driver circuit 1. In this leak test, a predetermined voltage is applied between the drain and source of the transistor Q2. In the case where the current source 9 is always connected between the output node No and the power supply line L2, the current source 9 is connected in parallel between the drain and source of the transistor Q2. The test may not be performed correctly. On the other hand, in this embodiment, since the current source 9 can be disconnected from the output node No and the power supply line L2 by turning off the transistor Q5, the leakage inspection of the transistor Q2 can be normally performed.

Since the driver circuit 1 according to the present embodiment can achieve the above-described effects, the power supply voltage VS has a large fluctuation range such as a battery voltage, and the power supply voltage VS is either low or high. However, it is suitable for applications where loss of function is not permitted. For example, the driver circuit 1 can be used for a motor drive driver, an output buffer driver, a relay driver, a charge pump driver, and the like. As specific application examples of the driver circuit 1, for example, configurations shown in FIGS.

That is, as shown in FIGS. 5 and 6, the driver circuit 1 can be used as a motor drive driver that drives a switching element that constitutes a motor drive circuit 31 that drives a motor M used in an electric power steering system, for example. . The motor drive circuit 31 is configured as an H bridge circuit including four N channel type MOS transistors Q31 to Q34.

More specifically, the driver circuit 1 can be used as a high-side driver that drives the high-side transistor Q31 that constitutes the motor drive circuit 31, as shown in FIG. Further, as shown in FIG. 6, the driver circuit 1 can be used as a low-side driver that drives the low-side transistor Q <b> 32 that constitutes the motor drive circuit 31.

As shown in FIG. 7, the driver circuit 1 can be used as a relay driver that drives an N-channel MOS transistor Q41 that functions as a power supply relay that cuts off power supply to a circuit 41 such as a control circuit.

(Second Embodiment)
The second embodiment will be described below with reference to FIG.
As shown in FIG. 8, the driver circuit 51 of the present embodiment is different from the driver circuit 1 of the first embodiment in that a leak suppression unit 52 is provided instead of the leak suppression unit 5. The leak suppression unit 52 is different from the leak suppression unit 5 in that a resistor 53 is provided instead of the current source 9. In this case, the resistor 53 corresponds to a load connected between the output node No and the power supply line L2.

Also with such a configuration, the transistor Q5 is turned on during the period when the transistor Q1 is turned on, whereby the resistor 53 as a load is connected between the output node No and the power supply line L2. Therefore, a predetermined current corresponding to the resistance value of the resistor 53 is drawn from the output node No to the power supply line L2 while the transistor Q1 is turned on. By performing such a current extracting operation by the leak suppression unit 52, the occurrence of a leak current flowing from the gate of the transistor Q1 to the output node No can be suppressed.

In this case, the value of the current drawn by the current drawing operation is determined by the resistance value of the resistor 53. Therefore, in the present embodiment, the resistance value of the resistor 53 is set so that the current value is equal to or greater than the current value IL of the leak current. The resistance value of the resistor 53 is set to be higher than the resistance value of the potential fixing resistor 4.

Since the driver circuit 51 of the present embodiment described above also suppresses the leakage current flowing to the output node No via the potential fixing resistor 4 during the period when the transistor Q1 is turned on, the same as in the first embodiment. The effect is obtained. Also, according to the present embodiment, the accuracy of setting the current value to be extracted by the current extraction operation is lower than that of the first embodiment, but the configuration of the leak suppression unit 52 can be simplified, and consequently the driver circuit 51. The manufacturing cost can be reduced.

(Third embodiment)
The third embodiment will be described below with reference to FIG.
As shown in FIG. 9, the driver circuit 61 of the present embodiment is different from the driver circuit 1 of the first embodiment in that a leak suppression unit 62 is provided instead of the leak suppression unit 5. The leak suppression unit 62 is different from the leak suppression unit 5 in that the transistor Q5 is omitted. In this case, the current source 9 is always connected between the output node No and the power supply line L2.

Also with such a configuration, a predetermined current corresponding to the current value of the current source 9 is drawn from the output node No to the power supply line L2 during the period when the transistor Q1 is turned on. By performing such a current extraction operation by the leak suppression unit 62, the occurrence of a leak current flowing from the gate of the transistor Q1 to the output node No can be suppressed.

Since the driver circuit 61 of the present embodiment described above also suppresses the leakage current flowing to the output node No via the potential fixing resistor 4 during the period when the transistor Q1 is turned on, the same as in the first embodiment. The effect is obtained. Further, according to the present embodiment, compared with the first embodiment, the circuit scale can be reduced by the amount that the transistor Q5 is omitted, and thus the manufacturing cost of the driver circuit 61 can be reduced.

(Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to FIG.
As shown in FIG. 10, the driver circuit 71 of this embodiment is different from the driver circuit 51 of the second embodiment in that a leak suppression unit 72 is provided instead of the leak suppression unit 52. The leak suppression unit 72 is different from the leak suppression unit 52 in that the transistor Q5 is omitted. In this case, the resistor 53 is always connected between the output node No and the power supply line L2.

Also with such a configuration, a predetermined current corresponding to the resistance value of the resistor 53 is drawn from the output node No to the power supply line L2 during the period when the transistor Q1 is turned on. By performing such a current extracting operation by the leak suppression unit 72, the occurrence of a leak current flowing from the gate of the transistor Q1 to the output node No can be suppressed.

The driver circuit 71 of the present embodiment described above also suppresses the leakage current flowing to the output node No via the potential fixing resistor 4 during the period in which the transistor Q1 is turned on, so that it is the same as in the second embodiment. The effect is obtained. Further, according to the present embodiment, compared with the second embodiment, the circuit scale can be reduced by the amount that the transistor Q5 is omitted, and thus the manufacturing cost of the driver circuit 71 can be reduced.

(Fifth embodiment)
Hereinafter, a fifth embodiment will be described with reference to FIG.
As shown in FIG. 11, the driver circuit 81 of the present embodiment is different from the driver circuit 1 of the first embodiment in that a leak suppression unit 82 is provided instead of the leak suppression unit 5. The leak suppression unit 82 includes transistors Q81 and Q82.

Transistors Q81 and Q82 are both NPN bipolar transistors. The transistor Q81 is in the form of a diode connection in which the collector and the base are connected. The collector of the transistor Q81 is connected to the anode of the Zener diode 3, and the emitter thereof is connected to the power supply line L2. The base of the transistor Q81 is connected to the base of the transistor Q82. Transistor Q82 has a collector connected to output node No, and an emitter connected to power supply line L2. In this case, transistor Q82 corresponds to a load connected between output node No and power supply line L2.

Thus, the transistors Q81 and Q82 constitute a current mirror circuit 83. In the above configuration, a current corresponding to the input current of the current mirror circuit 83, that is, the current flowing through the Zener diode 3, flows through the transistor Q82 which is a load. In the above configuration, the Zener diode 3 allows a current to flow and limit the gate voltage of the transistor Q1 when the power supply voltage VS becomes equal to or higher than the Zener voltage Vz.

Therefore, the leak suppression unit 82 configured as described above performs the current extraction operation during the period in which the transistor Q1 is turned on and the gate voltage is limited by the Zener diode 3. In this case, the value of the current drawn by the current drawing operation is determined by the value of the current flowing through the Zener diode 3 during the period when the gate voltage is limited and the mirror ratio of the current mirror circuit 83. Therefore, in the present embodiment, the specification of the Zener diode 3 and the setting of the mirror ratio of the current mirror circuit 83 are performed so that the current value is equal to or greater than the leakage current value IL. ing.

The driver circuit 81 of the present embodiment described above also suppresses the leakage current flowing to the output node No via the potential fixing resistor 4 during the period in which the transistor Q1 is turned on, so that it is the same as in the first embodiment. The effect is obtained. In addition, the current extraction operation by the leak suppression unit 82 of the present embodiment is executed in a period during which the transistor Q1 is turned on and a period in which the gate voltage is limited by the Zener diode 3. That is, in the present embodiment, even when the transistor Q1 is turned on, the current extraction operation is not performed during the period when the gate voltage is not limited by the Zener diode 3. The reason for this is as follows.

That is, during the period when the gate voltage is not limited by the Zener diode 3, the power supply voltage VS is lower than the Zener voltage Vz. Therefore, even if the output voltage Vo increases due to the leakage current during such a period, the output voltage Vo does not exceed the target value, and a voltage exceeding the withstand voltage is applied to the circuit elements constituting the load. There is no fear of being applied. Therefore, the current extraction operation by the leak suppression unit 82 does not have to be performed during a period in which the gate voltage is not limited by the Zener diode 3.

For this reason, in the present embodiment, the current extraction operation is executed only during the period when the gate voltage is limited by the Zener diode 3. According to such a configuration, the current extraction operation is not performed during the period in which the power supply voltage VS is lower than the Zener voltage Vz, and thus the current consumption can be reduced by that amount.

(Sixth embodiment)
Hereinafter, a sixth embodiment will be described with reference to FIG.
As shown in FIG. 12, the driver circuit 91 of the present embodiment is different from the driver circuit 1 of the first embodiment in that a leak suppression unit 92 is provided instead of the leak suppression unit 5. Leakage suppression unit 92 includes transistors Q91 to Q93 and resistors R91 to R93.

The transistor Q91 is an N-channel MOS transistor, and an input signal Si is given to the gate thereof. The source of the transistor Q91 is connected to the power supply line L2, and the drain thereof is connected to the power supply line L91 via resistors R91 and R92. A power supply voltage such as 5 V is applied to the power supply line L91.

Transistors Q92 and Q93 are PNP type bipolar transistors. The emitter of the transistor Q92 is connected to the power supply line L91, and the base thereof is connected to the interconnection point of the resistors R91 and R92. The collector of the transistor Q92 is connected to the collector of the transistor Q93 via the resistor R93 and is also connected to the base of the transistor Q93.

The collector of the transistor Q93 is connected to the source of the transistor Q1, and the emitter thereof is connected to the gate of the transistor Q1 through the potential fixing resistor 4. That is, in this case, the potential fixing resistor 4 is connected between the gate and source of the transistor Q1 via the transistor Q93.

In the above configuration, the potential fixing resistor 4 is connected between the gate and source of the transistor Q1 by turning on the transistor Q93 during a period when the input signal Si is at a low level, that is, during a period when the transistor Q1 is driven to turn off. Thus, when the transistor Q1 is driven off, the gate-source voltage is fixed to a voltage lower than the threshold voltage Vt, and the transistor Q1 can be reliably turned off.

In the above configuration, the potential fixing resistor 4 is disconnected from the gate and the source of the transistor Q1 by turning off the transistor Q93 during the period when the input signal Si is at a high level, that is, the period when the transistor Q1 is turned on. . As a result, when the transistor Q1 is turned on, there is no path through which the leakage current flows from the gate of the transistor Q1 to the output node No. As a result, the generation of the leakage current is suppressed. Therefore, the present embodiment also has the same effect as that of the first embodiment, that is, the excellent effect that the output voltage Vo caused by the leakage current can be suppressed while limiting the output voltage Vo to a desired voltage. Is obtained.

(Other embodiments)
The present disclosure is not limited to the embodiments described above and illustrated in the drawings, and can be arbitrarily modified, combined, or expanded without departing from the scope of the present disclosure.

Leakage suppression units

5, 52, 62, and 72 may be configured to perform a current extraction operation for extracting a predetermined current from output node No at least during a period in which transistor Q1 is turned on. The configuration can be changed as appropriate.

The leak suppression unit 82 is configured to perform a current extraction operation for extracting a predetermined current from the output node No at least during a period in which the transistor Q1 is turned on and a period in which the gate voltage is limited by the Zener diode 3. What is necessary is just to change the specific structure suitably.

The current drawn by the current drawing operation is preferably set to a current value equal to or greater than the leak current value, but may be set to a current value less than the leak current value. Even in such a setting, it is possible to obtain the effect of reducing the increase in the output voltage Vo due to the leakage current.

The leak suppression unit 92 may be configured to be able to isolate the potential fixing resistor 4 from between the gate and source of the transistor Q1 during the period when the transistor Q1 is turned on, and the specific configuration can be changed as appropriate. .
The drive unit 2 only needs to have a configuration capable of driving the transistors Q1 and Q2 in a complementary manner, and the specific configuration thereof can be changed as appropriate.

In each of the above embodiments, the Zener diode 3 connected between the gate of the transistor Q1 and the power supply line L2 is used as a voltage limiting unit that limits the gate voltage of the transistor Q1 to a predetermined clamp voltage. Other circuit elements or circuits may be used.
The transistor Q2 is not limited to an N-channel MOS transistor, and various switching elements can be used.

Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims

Two switching elements (Q1, Q2) connected in series between a pair of power supply lines (L1, L2) to which a power supply voltage is supplied, and a drive unit that complementarily drives the two switching elements according to an input signal (2), and a driver circuit (1, 51, 61, 71, 81) that supplies an output voltage output from an output node (No) connected to an interconnection point of the two switching elements to a driving target. 91)
Of the two switching elements, the switching element (Q1) on the high potential side is an N-channel MOS transistor,
A voltage limiting unit (3) for limiting the gate voltage of the switching element on the high potential side to a predetermined clamp voltage;
A potential fixing resistor (4) connected between the gate and source of the switching element on the high potential side;
A leakage suppression unit (5, 52, 62, 72, 82, 92) that suppresses generation of a leakage current flowing from the gate of the switching element on the high potential side to the output node;
A driver circuit comprising:
The driver circuit according to claim 1, wherein the leakage suppression unit (5, 52, 62, 72, 82) suppresses the generation of the leakage current by executing a current extraction operation for extracting a predetermined current from the output node.
3. The driver circuit according to claim 2, wherein the leakage suppression unit (5, 52, 62, 72) performs the current extraction operation at least during a period in which the high-potential side switching element is driven to turn on.
3. The leak suppression unit (82) performs the current extraction operation at least during a period in which the high-potential side switching element is turned on and a period in which the gate voltage is limited by the voltage limiting unit. Driver circuit.
The driver circuit according to any one of claims 2 to 4, wherein the predetermined current is set to a current value equal to or greater than a current value of the leakage current.
The said leak suppression part is provided with the load (9, 53, Q82) connected between the said output node and the said power supply line by the side of a low electric potential among a pair of said power supply lines. The driver circuit according to the item.
The driver circuit according to claim 6, wherein the leak suppression unit (5, 52) further includes a switch (Q5) connected in series between the output node and the low-potential side power line together with the load.
The driver circuit according to claim 6 or 7, wherein the load (9) is a current source.
The driver circuit according to claim 6 or 7, wherein the load (53) is a resistor.