JP3925686B2 - Output limiting circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an output limiting circuit that prevents an abnormal voltage from being output when a circuit is turned on, and more particularly to an output limiting circuit that can be applied to a high-speed circuit and can release the output limitation during normal operation.
[0002]
[Prior art]
A so-called diode clamp circuit exists as a conventional output limiting circuit. The diode clamp circuit turns on the diode when a predetermined output voltage is exceeded, and limits the output voltage signal to a constant value.
[0003]
FIG. 4 is a configuration block diagram showing an example of such a conventional output limiting circuit. In FIG. 4, reference numeral 1 denotes an output restriction target circuit that is an output restriction target, 2 and 3 are diodes, and 100 is an output voltage signal whose output is restricted.
[0004]
The output of the output restriction target circuit 1 is connected to the anode of the diode 2 and the cathode of the diode 3 and is output as an output voltage signal 100. The cathode of the diode 2 is connected to a positive voltage source, and the anode of the diode 3 is connected to a negative voltage source.
[0005]
Here, the operation of the conventional example shown in FIG. 4 will be described. When the voltage value of the positive voltage source is “V1”, the voltage value of the negative voltage source is “V2”, the voltage value of the output terminal is “VA”, and the diode 2 and 3 forward voltages are “VF”,
V1 + VF>VA> V2 + VF (1)
The diodes 2 and 3 are “OFF” in a range satisfying the above condition, and the output of the output restriction target circuit 1 is output as it is as the output voltage signal 100.
[0006]
On the other hand, when the circuit power is turned on, the voltage at the output terminal rises.
VA> V1 + VF (2)
In this case, the diode 2 is turned “ON” (the diode 3 remains “OFF”), and all the output current of the output restriction target circuit 1 flows into the positive voltage source.
[0007]
Therefore, the output voltage signal 100 is limited to “V1 + VF” regardless of the output of the output restriction target circuit 1.
[0008]
Similarly, when the circuit power is turned on, the voltage at the output terminal drops,
VA <V2 + VF (3)
In this case, the diode 3 is “ON” (the diode 2 remains “OFF”), and all of the output current of the output restriction target circuit 1 flows into the negative voltage source.
[0009]
Therefore, the output voltage signal 100 is limited to “V2 + VF” regardless of the output of the output restriction target circuit 1.
[0010]
As a result, by using the diode clamp circuit as shown in FIG.
V1 + VF>VA> V2 + VF (4)
It will be limited to the range shown in.
[0011]
[Problems to be solved by the invention]
However, since the conventional example shown in FIG. 4 is configured to directly limit the output voltage of the output restriction target circuit 1, a transistor used in the output stage of the output restriction target circuit 1 is used as a diode constituting the output restriction circuit. Therefore, a diode having a driving capability equal to or higher than the driving capability is required.
[0012]
That is, a diode having a relatively large size is used, and when the output restriction target circuit 1 operates at high speed, there is a problem that this diode becomes a capacitive load and hinders high-speed operation.
[0013]
In addition, the conventional example shown in FIG. 4 has a problem that the output restriction cannot be easily released when it is desired to release the output restriction when the output restriction target circuit 1 is operating normally after the power is turned on.
Therefore, the problem to be solved by the present invention is to realize an output limiting circuit that can be applied to a high-speed circuit and can release the output limitation during normal operation.
[0014]
[Means for Solving the Problems]
In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In the output limiting circuit that prevents the abnormal voltage from being output when the circuit is turned on,
An output restriction target circuit whose output voltage is restricted, a control circuit configured by a plurality of transistor circuits and changing the state of the control voltage based on the threshold voltage and the power supply voltage of the transistor circuit, and based on the state of the control voltage A function stopping means for stopping the function of the output restriction target circuit; and an output fixing means for fixing the output voltage to a constant value regardless of the output of the output restriction target circuit based on the state of the control voltage. The output restriction can be released during normal operation.
[0015]
The invention according to claim 2
In the output limiting circuit according to the invention of claim 1,
The control circuit comprises:
A first NMOS transistor circuit having a gate and a drain connected to one of the power supply voltages; a gate connected to the other of the power supply voltage; a source of the first NMOS transistor circuit connected to a source; A PMOS transistor circuit for outputting a control voltage; and a second NMOS transistor circuit having a gate connected to one of the power supply voltages, a source connected to the other of the power supply voltages, and a drain connected to the drain of the PMOS transistor circuit. By being configured, it becomes possible to release the output restriction during normal operation.
[0016]
The invention described in claim 3
In the output limiting circuit according to the invention of claim 1,
The function stop means is
A first switch circuit that cuts off an input signal based on the state of the control voltage, and a second switch circuit group that stops the operation of each circuit constituting the output restriction target circuit based on the state of the control voltage As a result, it can be applied to a high-speed circuit, and the output restriction can be released during normal operation.
[0017]
The invention according to claim 4
In the output limiting circuit according to the invention of claim 1,
The output fixing means;
Consisting of a constant voltage source and a switch circuit that connects the output of the constant voltage source to an output terminal based on the state of the control voltage, it can be applied to a high-speed circuit and can release the output restriction during normal operation. It becomes possible.
[0018]
The invention according to claim 5
In the output limiting circuit which is the invention according to claim 3 or claim 4 ,
The switch circuit is
Since it is an NMOS transistor circuit or a PMOS transistor circuit, it can be applied to a high-speed circuit and the output restriction can be released during normal operation.
[0019]
The invention described in claim 6
In the output limiting circuit which is the invention according to claim 2,
By inserting a plurality of NMOS transistor circuits having gates and drains connected in series between the first NMOS transistor circuit and the PMOS transistor circuit, the output control release voltage can be changed.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of an output limiting circuit according to the present invention. In FIG. 1, 4 is an output restriction target circuit, 5 is a control circuit, 6 is a function stop means, 7 is an output fixing means, 100a is an output voltage signal, 101 and 102 are power supply voltages, and 103 is a control voltage.
[0021]
The output of the output restriction target circuit 4 is output as an output voltage signal 100a through the output fixing means 7. The power supply voltages 101 and 102 are applied to the control circuit 5, and the control voltage 103 from the control circuit 5 is connected to the control input terminals of the function stop unit 6 and the output fixing unit 7, respectively. Further, the function stopping means 6 stops the function of the output restriction target circuit 4 by its operation.
[0022]
Here, the operation of the embodiment shown in FIG. 1 will be described. The control circuit 5 changes the state of the control voltage 103 according to the value of the power supply voltage signal. The function stop means 6 stops the function of the output restriction target circuit 4 based on the state of the control voltage 103, and the output fixing means 7 determines the output voltage signal 100a based on the state of the control voltage 103 regardless of the output of the output restriction target circuit 4. The voltage value is fixed to a constant value.
[0023]
For example, when the power supply voltages 101 and 102 have not transiently reached a predetermined voltage value when the power is turned on, the control voltage 103 is set to “low level”, while the power supply voltages 101 and 102 have reached a predetermined voltage value. In this state, in other words, in the steady state, the control voltage 103 is set to “high level”.
[0024]
The function stop means 6 stops the function of the output restriction target circuit 4 when the control voltage 103 is “low level”, and stops the function of the output restriction target circuit 4 when the control voltage 103 is “high level”. Is released.
[0025]
On the other hand, when the control voltage 103 is "low level", the output fixing means 7 fixes the voltage value of the output voltage signal 100a to a constant value regardless of the output of the output restriction target circuit 4, and the control voltage 103 is "high level". In the case of “,” the output of the output restriction target circuit 4 is output as it is.
[0026]
That is, without using a relatively large diode, the control circuit 5 fixes the output voltage signal 100a to a constant voltage value when the transient power supply voltages 101 and 102 rise when the power is turned on. The output of the voltage signal 100a is limited, and the output control is canceled when the power supply voltage reaches a steady state.
[0027]
As a result, when the control circuit 5 detects the state of the power supply voltage, the function of the output restriction target circuit is stopped in a transient state, the output voltage signal is fixed to a constant value, and the power supply voltage becomes a steady state. By releasing the output control, it becomes possible to release the output restriction during normal operation.
[0028]
FIG. 2 is a block diagram showing a specific example of each of the control circuit 5, the function stop means 6, and the output fixing means 7. 2, 4, 5, 6, 7, 100a, 101, 102, and 103 are assigned the same reference numerals as in FIG. 1, and 8, 10, 14, and 15 are NMOS transistor circuits (hereinafter simply referred to as NMOS). , 9 are PMOS transistor circuits (hereinafter simply referred to as PMOS), 11, 12, 13 and 16 are switch circuits, 17 is a constant voltage source, 104 is an input signal to the output restriction target circuit 4, and 105 is a bias voltage signal. is there.
[0029]
Further, 14 and 15 constitute the output restriction target circuit 4, 8 to 10 constitute the control circuit 5, 11 to 13 constitute the function stop means 6, and 16 and 17 constitute the output fixing means 7, respectively.
[0030]
The power supply voltage 101 is applied to the gate and drain of the NMOS 8, the gate of the MOS 10, and the drain of the NMOS 14, respectively. The power supply voltage 102 is applied to the gate of the PMOS 9, the sources of the NMOS 10 and 15, and the switch circuits 12 and 13, respectively.
[0031]
The source of the NMOS 8 is connected to the source of the PMOS 9, and the drain of the PMOS 9 outputs the control voltage 103 and is connected to the drain of the NMOS 10.
[0032]
The input signal 104 is applied to one end of the switch circuit 11, and the other end of the switch circuit 11 is connected to the gate of the NMOS 14 to the other end of the switch circuit 12. The source of the NMOS 14 outputs the output voltage signal 100 a and is connected to the drain of the NMOS 15 and one end of the switch circuit 16.
[0033]
The bias voltage signal 105 is connected to the other end of the switch circuit 13 and the gate of the NMOS 15, the other end of the switch circuit 16 is connected to one end of the constant voltage source 17, and the other end of the constant voltage source 17 is grounded.
[0034]
Finally, the control voltage 103 is connected to the control input terminals of the switch circuits 11, 12, 13 and 16, respectively.
[0035]
Here, the operation of the specific example shown in FIG. 2 will be described. When the power is turned on, the voltage “Vab” between the power supply voltages 101 and 102 sequentially increases from “0 V”. When the voltage exceeds the NMOS threshold voltage “Vtn”, the NMOS 10 is turned “ON” and tries to flow a drain current.
[0036]
On the other hand, when the threshold voltage of the PMOS is “Vtp”, the PMOS 9 is not “ON” unless the “Vab” exceeds “Vtn + Vtp”, and the drain current cannot flow. In other words, the drain current cannot flow unless the NMOS 8 and the PMOS 9 are simultaneously “ON”.
[0037]
In this case, since the NMOS 10 cannot flow the drain current, the control voltage 103 becomes equal to the power supply voltage 102.
[0038]
Further, the voltage “Vab” between the power supply voltages 101 and 102 sequentially increases from “Vtn”, and when it exceeds “Vtn + Vtp”, the NMOS 8 and the PMOS 9 are simultaneously turned “ON”.
[0039]
Here, when the mutual conductance of the voltage-current conversion circuit composed of the NMOS 8 and the PMOS 9 is sufficiently larger than the mutual conductance of the NMOS 10, the power supply voltages 101 and 102 are “Va” and “Vb”, the control voltage 103 is “Vc”, If the gate-source voltage of the NMOS 8 is “Vgs8” and the gate-source voltage of the PMOS 9 is “Vgs9”,
Vc = Va-Vgs8-Vgs9 + Vtp
≒ Va-Vtn (5)
It becomes.
[0040]
That is, when the voltage “Vab” is between “Vtn” and “Vtn + Vtp”, the control voltage 103 is “Vb”, and when the voltage “Vab” is equal to or higher than “Vtn + Vtp”, the control voltage 103 is “Va−”. Vtn ".
[0041]
On the other hand, the switch circuit 11, 13 and 16 is “ON” when “Vc = Vb” and “OFF” when “Vc = Va−Vtn”, and “OFF” when “Vc = Vb”. “Vc = Va−Vtn” is set to be “ON”.
[0042]
For this reason, when the power is turned on, the voltage “Vab” between the power supply voltages 101 and 102 sequentially increases from “0 V” and exceeds the NMOS threshold voltage “Vtn”, the control voltage 103 which is the output of the control circuit 5 is “ Vc = Vb ”, the switch circuits 12, 13 and 16 are turned“ ON ”, and the switch circuit 11 is turned“ OFF ”.
[0043]
At this time, the input signal 104 is disconnected and the power supply voltage 102 is applied to the gates of the NMOSs 14 and 15 to stop the NMOS function, and the output voltage of the constant voltage source 17 is output as the output voltage signal 100a. Therefore, the output voltage of the constant voltage source 17 is fixed. In other words, the output is limited.
[0044]
When the voltage “Vab” between the power supply voltages 101 and 102 sequentially increases from “Vtn” and exceeds “Vtn + Vtp”, the control voltage 103 which is the output of the control circuit 5 becomes “Vc = Va−Vtn”. The switch circuits 12, 13 and 16 are turned “OFF”, and the switch circuit 11 is turned “ON”.
[0045]
At this time, the output voltage of the constant voltage source 17 is disconnected from the output terminal, the input signal 104 is applied to the gate of the NMOS 14, and the bias voltage 105 is applied to the gate of the NMOS 15. For this reason, the NMOS 15 operates as a constant current source, and the NMOS 14 and the NMOS 15 operate as a source follower circuit. In other words, the output restriction is released.
[0046]
As a result, in the case of FIG. 2, the control circuit 5 detects the state of the power supply voltage, and in a transient state, the function of the source follower circuit that is the output restriction target circuit is stopped, and the output voltage signal is output from the constant voltage source 17. By fixing the voltage and releasing the output control when the power supply voltage reaches a steady state, the output restriction can be released during normal operation.
[0047]
FIG. 3 is an explanatory diagram showing a specific example of the switch circuit. As a specific example of realizing the functions of the switch circuits 13, 14 and 16, the functions of the PMOS transistor and the switch circuit 11 shown in FIG. As a specific example to be realized, an NMOS transistor shown in FIG.
[0048]
In the specific example shown in FIG. 2, the source follower circuit is exemplified as the output restriction target circuit 4. However, the present invention is not limited to this and can be applied to circuits having various configurations.
[0049]
Further, in the specific example of the control circuit 5 shown in FIG. 2, one NMOS 8 is connected to the source of the PMOS 9, but by inserting a plurality of NMOS transistor circuits having gates and drains connected in series, The output control release voltage can be changed to “Vtp + 2Vtn”, “Vtp + 3Vtn”, “Vtp + 4Vtn”. A PMOS transistor circuit can also be used as the NMOS 8.
[0050]
【The invention's effect】
As is apparent from the above description, the present invention has the following effects.
According to the first to fifth aspects of the present invention, the state of the power supply voltage is detected by the control circuit, the function of the output restriction target circuit is stopped in the transient state, the output voltage signal is fixed to a constant value, and the power supply voltage When the state becomes a steady state, it is possible to release the output restriction during normal operation by releasing the output control.
[0051]
Further, since the output fixing means and the function stopping means can be constituted by small MOS transistors, they can be applied to high-speed circuits.
[0052]
According to a sixth aspect of the present invention, a plurality of NMOS transistor circuits having gates and drains connected between the NMOS transistor circuit and the PMOS transistor circuit are inserted in series, so that the output control release voltage is reduced. Can be changed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an output limiting circuit according to the present invention.
FIG. 2 is a block diagram illustrating a specific example of each of a control circuit, a function stop unit, and an output fixing unit.
FIG. 3 is an explanatory diagram illustrating a specific example of a switch circuit.
FIG. 4 is a configuration block diagram showing an example of a conventional output limiting circuit.
[Explanation of symbols]
1, 4 Output restriction target circuits 2, 3 Diode 5 Control circuit 6 Function stopping means 7 Output fixing means 8, 10, 14, 15 NMOS transistor circuit 9 PMOS transistor circuits 11, 12, 13, 16 Switch circuit 17 Constant voltage source 100 , 100a Output voltage signal 101, 102 Power supply voltage 103 Control voltage 104 Input signal 105 Bias voltage signal

Claims (6)

In the output limiting circuit that prevents the abnormal voltage from being output when the circuit is turned on,
An output restriction target circuit whose output voltage is restricted; and
A control circuit configured by a plurality of transistor circuits and changing the state of the control voltage based on the threshold voltage and the power supply voltage of the transistor circuit ;
Function stop means for stopping the function of the output restriction target circuit based on the state of the control voltage;
An output control circuit comprising: output fixing means for fixing the output voltage to a constant value regardless of the output of the output restriction target circuit based on the state of the control voltage. The control circuit comprises:
A first NMOS transistor circuit having a gate and a drain connected to one of the power supply voltages;
A PMOS transistor circuit having a gate connected to the other of the power supply voltages, a source of the first NMOS transistor circuit connected to a source, and a drain outputting the control voltage;
2. A second NMOS transistor circuit having a gate connected to one of the power supply voltages, a source connected to the other of the power supply voltages, and a drain connected to a drain of the PMOS transistor circuit. The output limiting circuit according to 1. The function stop means is
A first switch circuit that disconnects an input signal based on the state of the control voltage;
2. The output limiting circuit according to claim 1, further comprising: a second switch circuit group that stops the operation of each circuit constituting the output limiting target circuit based on the state of the control voltage. The output fixing means;
A constant voltage source;
2. The output limiting circuit according to claim 1, further comprising a switch circuit that connects an output of the constant voltage source to an output terminal based on a state of the control voltage. The switch circuit is
5. The output limiting circuit according to claim 3, wherein the output limiting circuit is an NMOS transistor circuit or a PMOS transistor circuit. 3. The output limiting circuit according to claim 2, wherein a plurality of NMOS transistor circuits whose gates and drains are connected are inserted in series between the first NMOS transistor circuit and the PMOS transistor circuit.

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