KR101149902B1 - Level-shift circuit - Google Patents

Abstract

It is possible to reduce the current consumption, reduce the power supply voltage required for signal transmission, and obtain a level shift circuit that can accurately transmit a signal even when the power supply voltage fluctuates. The level shift circuit of the present invention includes an inverter circuit INV2, a level shift element MOS1, a first resistor R1, and a current mirror circuit CM1. The inverter circuit INV2 inverts the input signal and outputs it. The level shift element MOS1 operates by using the output signal of the inverter circuit INV2 as a gate signal. One end of the first resistor R1 is connected to the output of the inverter circuit. The current mirror circuit CM1 flows a current corresponding to the current input from the output of the inverter circuit INV2 through the first resistor R1 from the source of the level shift element MOS1 to the ground point.

Description

Level shift circuit {LEVEL-SHIFT CIRCUIT}

The present invention relates to a level shift circuit for shifting the level of an input signal.

In the inverter device, a half bridge circuit, a full bridge circuit, a three phase bridge circuit, or the like is used. These circuits are provided with the level shift circuit which shifts the level of an input signal (for example, refer patent document 1).

[Patent Document 1] Japanese Patent Laid-Open No. 2003-179482

In the level shift circuit of FIG. 1 of patent document 1, the constant current sources CC1 and CC2 provided in the source side of MOS transistors Q1 and Q2 are always in an operating state. For this reason, the drain current of one of the MOS transistors Q1 and Q2 flows even when the input signal is kept high or low. Here, in order to reduce the RC time constant in high speed operation, since the resistance values of the resistors R1 and R2 are made smaller than 10 k ?, the current values of the constant current sources CC1 and CC2 are larger than 1 mA. Therefore, in the circuit of patent document 1, the circuit current of 1 mA or more is always consumed.

In addition, in the level shift circuit, it is required to reduce the power supply voltage required for signal transmission. Moreover, in the conventional level shift circuit, when a power supply voltage fluctuates and falls, it may not be able to transmit a signal correctly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to reduce the current consumption, to reduce the power supply voltage required for signal transmission, and to accurately transmit a signal even when the power supply voltage fluctuates. To obtain a shift circuit.

The present invention provides an inverter circuit for inverting and outputting an input signal, a level shift element that operates by using an output signal of the inverter circuit as a gate signal, a first resistor having one end connected to an output of the inverter circuit, And a current mirror circuit for flowing a current corresponding to a current input from an output of the inverter circuit through a single resistor to a ground point from a source of the level shift element.

According to the present invention, the current consumption can be reduced, the power supply voltage required for signal transmission can be reduced, and the signal can be accurately transmitted even if the power supply voltage fluctuates.

1 is a diagram showing a half bridge circuit according to an embodiment of the present invention.
2 is a timing chart illustrating the operation of the circuit of FIG. 1.
3 is a diagram showing a level shift circuit according to Embodiment 1 of the present invention.
4 is a diagram showing a level shift circuit according to a reference example.
5 is a timing chart showing the operation of the circuit of the first embodiment.
6 is a timing chart showing the operation of the circuit of the reference example.
7 is a diagram showing power supply voltage dependence of the circuits of the first embodiment and the reference example.
8 is a diagram showing the level shift circuit according to the second embodiment of the present invention.
9 is a timing chart illustrating the operation of the circuit of FIG. 8.
10 is a diagram showing a level shift circuit according to Embodiment 3 of the present invention.
Fig. 11 is a diagram showing the level shift circuit according to the fourth embodiment of the present invention.
Fig. 12 is a diagram showing the level shift circuit according to the fifth embodiment of the present invention.
Fig. 13 is a diagram showing the level shift circuit according to the sixth embodiment of the present invention.
Fig. 14 is a diagram showing the level shift circuit according to the seventh embodiment of the present invention.
Fig. 15 is a diagram showing the level shift circuit according to the eighth embodiment of the present invention.
Fig. 16 is a diagram showing the level shift circuit according to the ninth embodiment of the present invention.
17 is a diagram showing the level shift circuit according to the tenth embodiment of the present invention.

Example 1.

[Half Bridge Circuit]

1 is a diagram showing a half bridge circuit according to an embodiment of the present invention. In response to an instruction from the control circuit 10 such as a microcomputer or a CPU, the high side driver 12 and the low side driver 14 turn on / off the IGBTs 16 and 18, respectively. The collector of the IGBT 16 is connected to a power supply 20, and the emitter is connected to a load 22 such as a motor or a lamp. The collector of the IGBT 18 is connected to the load 22, and the emitter is grounded.

The high side driver 12 will be described in more detail. The input signal input from the control circuit 10 via the input terminal INH is input to the one shot pulse circuit 28 through the resistor 24 and the Schmitt circuit 26. The anode of the diode 30 is grounded, and the cathode is connected to the input terminal INH. The resistor 32 is connected between the input terminal INH and the ground point. The anode of the diode 34 is connected to the input of the Schmitt circuit 26 and the cathode is connected to the power supply.

The one shot pulse circuit 28 outputs a one shot ON pulse when the input signal rises, and outputs a one shot OFF pulse when the input signal falls. The level shift circuits 36 and 38 shift the levels of the one shot ON pulse and the one shot OFF pulse, respectively. The configuration of the level shift circuits 36 and 38 will be described later in detail. The anodes of the diodes 44, 46, to which the resistors 40, 42 are connected, respectively, between the outputs of the level shift circuits 36, 38 and the power supply VB, are connected to the power supply VS. The cathode is connected to the output of the level shift circuits 36 and 38 respectively.

The output signals of the level shift circuits 36 and 38 are input to the set terminal S and the reset terminal R of the RS flip-flop circuit 52 via the inverters 48 and 50, respectively. The output signal of the RS flip-flop circuit 52 is input to the gate of the PMOS transistor 58 and the gate of the NMOS transistor 60 through the inverters 54 and 56, respectively. The source of the PMOS transistor 58 is connected to the power supply VB, the source of the NMOS transistor 60 is connected to the power supply VS, and the drain of the PMOS transistor 58 and the drain of the NMOS transistor 60 connect the output terminal OUTH. It is connected to the gate of the IGBT 16 through.

2 is a timing chart illustrating the operation of the circuit of FIG. 1. The one shot pulse circuit 28 outputs a one shot ON pulse when the input signal input from the input terminal INH rises, and outputs a one shot OFF pulse when the input signal falls. As a result, the output signal output from the output terminal OUTH is switched ON / OFF in accordance with the high / low change of the input signal IN.

[Level shift circuit]

3 is a diagram showing a level shift circuit according to the first embodiment of the present invention. This level shift circuit corresponds to the level shift circuits 36 and 38 in the half bridge circuit of FIG.

The inverter circuit INV1 inverts the input signal input from the input terminal IN, and the inverter circuit INV2 inverts and outputs it. The level shift element MOS1, which is an NMOS transistor, operates by using the output signal of the inverter circuit INV2 as a gate signal. One end of the first resistor R1 is connected to the output of the inverter circuit INV2. The current mirror circuit CM1 flows the current ID corresponding to the current IC input from the output of the inverter circuit INV2 through the first resistor R1 from the source of the level shift element MOS1 to the ground point.

The drain of the level shift element MOS1 is connected to the power supply VB through the resistor R2, and is connected to the output terminal OUT through the inverter circuits INV3, INV4, and INV5. The anode of the diode D1 is connected to the power supply VS, and the cathode is connected to the drain of the level shift element MOS1. The threshold voltage of the level shift element MOS1 is VTH1, and the threshold voltage of the inverter INV3 is VTH2.

The inverter circuit INV2 has a PMOS transistor MOS2 and an NMOS transistor MOS3. The PMOS transistor MOS2 inputs an input signal from a gate, a source is connected to the power supply VCC, and a drain is connected to the gate of the level shift element MOS1. The NMOS transistor MOS3 receives an input signal from a gate, has a source grounded, and a drain connected to the gate of the level shift element MOS1.

The current mirror circuit CM1 has a first bipolar transistor Tr1 and a second bipolar transistor Tr2. In the first bipolar transistor Tr1, the base and the collector are connected to the other end of the first resistor R1, and the emitter is grounded. The base of the second bipolar transistor Tr2 is connected to the base of the first bipolar transistor Tr1, the collector is connected to the source of the level shift element MOS1, and the emitter is grounded. In other words, the current mirror circuit CM1 of the first embodiment is a Widlar type current mirror.

[Effect 1]

The effect of the level shift circuit which concerns on Example 1 is demonstrated, comparing with a reference example. 4 is a diagram illustrating a level shift circuit according to a reference example. Unlike the circuit of FIG. 3, instead of the first resistor R1, a resistor R1 ′ is connected between the drain of the PMOS transistor MOS2 and the gate of the level shift element MOS1. The collector of the first bipolar transistor Tr1 is connected to the other end of the resistor R1 'and the emitter is grounded. The base and collector of the second bipolar transistor Tr2 are connected to the base of the first bipolar transistor Tr1 and the source of the level shift element MOS1, and the emitter is grounded. In other words, the current mirror circuit CM2 of the reference example is a Wilson current mirror circuit.

5 is a timing chart showing the operation of the circuit of the first embodiment, and FIG. 6 is a timing chart showing the operation of the circuit of the reference example. 7 is a diagram showing the power supply voltage dependence of the circuits of the first embodiment and the reference example. For example, VTH1> 1V, VBE = 0.7V, and VDS <1V. At this time, the threshold voltage VTH1 increases as the current ID increases.

In order to operate the current mirror circuits CM1 and CM2, it is necessary to satisfy the condition VCC> VBE + VDS in the first embodiment, and to satisfy the condition VCC> VTH1 + VBE + VDS in the reference example. Therefore, the first embodiment can reduce the power supply voltage VCC (permissible voltage) necessary for transmitting a signal as compared with the reference example.

[Effect 2]

In the reference example, ID = (VCC- (VTH1 + VBE + VDS)) / R1 '. On the other hand, in Example 1, ID = (VCC- (VBE + VDS)) / R1. In other words, in Embodiment 1, the current ID does not depend on the threshold voltage VTH1. Therefore, when the current ID of the same magnitude is obtained, the resistance value of the resistor R1 of the first embodiment can be made larger than the resistance value of the resistor R1 'of the reference example. For this reason, in Example 1, the fluctuation | variation of electric current ID can be made small with respect to the fluctuation | variation (power supply voltage fall) of the power supply voltage VCC.

In the reference example, since the variation of the current ID due to the fluctuation of the power supply voltage VCC is large, the condition ID * R2> VBS-VTH2 may not be satisfied, and the level shift circuit may not operate normally and the signal may not be transmitted. . On the contrary, in Example 1, since the variation of the current ID with respect to the fluctuation of the power supply voltage VCC is small, a signal can be transmitted correctly even if a power supply voltage changes.

Table 1 shows the results of calculating the deviation? IC and? ID of the IC and ID when the power supply voltage VCC fluctuates. Here, the current multiplication coefficients of the bipolar transistors Tr1 and Tr2 of the current mirror circuits CM1 and CM2 are sufficiently large. In addition, ID = IC × 2 was set so small that the influence of the base currents of the bipolar transistors Tr1 and Tr2 could be ignored. In addition, both current ICs and IDs in standard time (VCC = 15V) were assumed to be the same. From the calculation result, it was confirmed that Example 1 of deviation (DELTA) IC and (DELTA) ID become smaller than a reference example.

[Table 1]

[Effect 3]

In the level shift circuit of the first embodiment, the level shift element MOS1 and the current mirror circuit CM1 are turned on / off simultaneously in accordance with the input signal. Therefore, when the input signal is low, the level shift element MOS1 and the current mirror circuit CM1 are turned off, and the circuit current between VCC-GND and VB-GND is hardly consumed. Therefore, in Example 1, the current consumption can be reduced. Although the effect varies slightly depending on the current mirror ratio, in the case of ID = IC × 2, in Example 1, the circuit current between VCC-GND is reduced by about 3 mA and the circuit current between VB-GND is reduced by about 6 mA in comparison with the reference example. can do.

At this time, in order to reduce the circuit current between VCC-GND, it is conceivable to increase the ratio (current mirror ratio) of the collector current of transistor Tr2 to the collector current of transistor Tr1 (for example, 10). In this case, however, there are problems such as an increase in the circuit area and a disturbance in the setting of the current mirror current value due to the influence of the base current. In Example 1, this problem does not occur.

Example 2.

8 is a diagram showing the level shift circuit according to the second embodiment of the present invention. The second resistor R3 is connected between the drain of the PMOS transistor MOS2 and the gate of the level shift element MOS1. One end of the first resistor R1 is connected to the connection point of the drain of the PMOS transistor MOS2 and the second resistor R3. Other configurations are the same as those in the first embodiment.

9 is a timing chart illustrating the operation of the circuit of FIG. 8. The level shift element MOS1 is soft-on by the combination of the parasitic capacitance (RC filter effect) of the second resistor R3 and the level shift element MOS1. In other words, during the ON operation, the current mirror circuit CM1 is raised before the level shift element MOS1. As a result, since the current ID rises slowly, generation of surge current and voltage between the collector and the emitter of the transistor Tr2 due to the high-speed switching can be prevented. On the other hand, during the OFF operation, the level shift element MOS1 is lowered before the current mirror circuit CM1.

Example 3.

10 is a diagram showing the level shift circuit according to the third embodiment of the present invention. A zener diode D2 is provided in which the anode is grounded and the cathode is connected to the source of the level shift element MOS1. Other configurations are the same as those in the first embodiment.

In the high breakdown voltage level shift circuit (VB> VCC), the collector of the transistor Tr2 is used for the high speed switching of the level shift element MOS1, the potential variation of the power supply VB or the power supply VS, or the power supply VB starting before the power supply VCC. • There may be a surge that exceeds the device breakdown voltage between emitters. On the other hand, by connecting the Zener diode D2 in parallel with the transistor Tr2, the surge voltage between the collector and the emitter can be absorbed, and the collector potential of the transistor Tr2 (= source potential of the level shift element MOS1) can be clamped below a certain voltage. .

Example 4.

11 is a diagram showing a level shift circuit according to the fourth embodiment of the present invention. A diode D3 is provided in which the anode is connected to the source of the level shift element MOS1 and the cathode is connected to the output of the inverter circuit INV2. Other configurations are the same as those in the first embodiment.

Surge generated between the collector and the emitter of the transistor Tr2 is discharged in four paths I1 to I4 through the diode D3. Here, the paths I1 and I2 are paths to be discharged by the current mirror operation. Path I3 is a path that discharges through the parasitic diode (PN forward operation) of MOS2 when the surge voltage is greater than VCC. The path I4 is a path for turning on MOS3 to discharge when the input signal is L. FIG. Thereby, the same effect as Example 3 can be obtained.

Example 5.

12 is a diagram showing the level shift circuit according to the fifth embodiment of the present invention. A diode D4 is provided in which the anode is connected to the source of the level shift element MOS1 and the cathode is connected to the power supply VCC. Other configurations are the same as those in the first embodiment. By thus clamping the collector potential of the second bipolar transistor Tr2 directly to the power supply VCC through the diode D4, the same effect as in Example 3 can be obtained.

Example 6.

Fig. 13 is a diagram showing the level shift circuit according to the sixth embodiment of the present invention. A third bipolar transistor Tr3 whose base is connected to the collector of the first bipolar transistor Tr1, whose emitter is connected to the base of the first and second bipolar transistors Tr1 and Tr2, and whose collector is connected to the power supply Vcc is provided. The resistor R4 is connected between the collector of the third bipolar transistor Tr3 and the ground point. In other words, the current mirror circuit CM1 of the sixth embodiment is a base current compensation type current mirror. Other configurations are the same as those in the first embodiment.

In the reference example, it is necessary to use bipolar transistors Tr1 and Tr2 with high hfe in order to bring the current ID closer to the current IR1. On the other hand, in the sixth embodiment, since the base currents of the bipolar transistors Tr1 and Tr2 are mainly supplied by the bipolar transistors Tr3, IR1 = ID can be set with a small deviation. However, the bipolar transistors Tr1 and Tr2 are devices having the same specification, and the bipolar transistors Tr1 and Tr2 need to be small enough to ignore the influence of the base current of the bipolar transistor Tr3 on the current IR1.

Example 7.

Fig. 14 is a diagram showing the level shift circuit according to the seventh embodiment of the present invention. The current Mira Canow circuit CM1 has a first MOS transistor MOS4 and a second MOS transistor MOS5. In the first MOS transistor MOS4, the gate and the drain are connected to the other end of the first resistor R1, and the source is grounded. In the second MOS transistor MOS5, a gate is connected to the gate of the first MOS transistor MOS4, a drain is connected to the source of the level shift element MOS1, and the source is grounded. In other words, the current mirror circuit CM1 of the seventh embodiment is a MOS type current mirror circuit. Other configurations are the same as those in the first embodiment. In the MOS type current mirror circuit, since there is no problem of the current mirror circuit using the bipolar transistor described in the sixth embodiment, it is possible to set IR1 = ID with a small deviation.

Example 8.

Fig. 15 is a diagram showing the level shift circuit according to the eighth embodiment of the present invention. As in Example 2, the second resistor R3 is provided, and in the same manner as in Example 3, a Zener diode D2 is provided. Other configurations are the same as those in the seventh embodiment. Thereby, the same effect as Example 2, 3, 7 can be acquired.

Example 9.

Fig. 16 is a diagram showing the level shift circuit according to the ninth embodiment of the present invention. Similarly to the second embodiment, the second resistor R3 is provided, and similarly to the fourth embodiment, the diode D3 is provided. Other configurations are the same as those in the seventh embodiment. Thereby, the same effect as Example 2, 4, 7 can be acquired.

Example 10.

17 is a diagram showing the level shift circuit according to the tenth embodiment of the present invention. As in the second embodiment, the second resistor R3 is provided, and in the same manner as in the fifth embodiment, the diode D4 is provided. Other configurations are the same as those in the seventh embodiment. Thereby, the same effect as Example 2, 5, 7 can be acquired.

CM1: Current Mirror Circuit
D2: Zener Diode
D3, D4: Diode
INV2: Inverter Circuit
MOS1: level shift element
MOS2: PMOS transistor
MOS3: NMOS transistor
MOS4: first MOS transistor
MOS5: second MOS transistor
R1: first resistor
R3: second resistor
Tr1: first bipolar transistor
Tr2: second bipolar transistor
Tr3: third bipolar transistor

Claims (9)

An inverter circuit for inverting and outputting an input signal;
A level shift element which operates by using the inverted signal as a gate signal;
A first resistor whose one end is connected to the output of said inverter circuit,
And a current mirror circuit for flowing a current corresponding to a current input from the output of the inverter circuit through the first resistor from a source of the level shift element to a ground point.
A level shift element that operates by using a signal inverted from an input signal as a gate signal,
A current mirror circuit for inputting a current determined from a signal inverting the input signal, for flowing a current corresponding to the input current from a source of the level shift element to a ground point;
An inverter circuit for outputting a signal inverting the input signal;
And a first resistor connected between the output of the inverter circuit and the current mirror circuit to determine a current input to the current mirror circuit. The method of claim 2,
The current mirror circuit,
A first bipolar transistor having a base and a collector connected to the other end of the first resistor, and having an emitter grounded;
And a base connected to a base of the first bipolar transistor, a collector connected to a source of the level shift element, and an emitter connected to a grounded second bipolar transistor.
The method of claim 2,
The current mirror circuit,
A first MOS transistor having a gate and a drain connected to the other end of the first resistor, and having a source grounded;
And a gate is connected to the gate of the first MOS transistor, a drain is connected to the source of the level shift element, and the source has a second MOS transistor whose ground is grounded.
The method according to any one of claims 1 to 4,
The inverter circuit,
A PMOS transistor whose input signal is input from a gate, a source is connected to a power supply, and a drain is connected to a gate of the level shift element;
And a NMOS transistor whose input is input from a gate, whose source is grounded, and whose drain is connected to the gate of said level shift element.
6. The method of claim 5,
And a second resistor connected between the drain of the PMOS transistor and the gate of the level shift element,
One end of the first resistor is connected to a connection point of a drain of the PMOS transistor and the second resistor.
The method according to any one of claims 2 to 4,
And a Zener diode having an anode grounded and a cathode connected to a source of the level shift element.
The method according to any one of claims 1 to 4,
And an anode connected to the source of the level shift element and a cathode connected to the output of the inverter circuit.
The method according to any one of claims 1 to 4,
And an anode connected to a source of said level shift element, and a cathode connected to a power supply.

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