CN104320118B

CN104320118B - A kind of driving circuit structure

Info

Publication number: CN104320118B
Application number: CN201410616465.XA
Authority: CN
Inventors: 李兆桂; 陈涛
Original assignee: WUXI PUYA SEMICONDUCTOR CO Ltd
Current assignee: Praran semiconductor (Shanghai) Co., Ltd
Priority date: 2014-11-06
Filing date: 2014-11-06
Publication date: 2017-12-12
Anticipated expiration: 2034-11-06
Also published as: CN104320118A

Abstract

The present invention relates to analog power technical field,Specially a kind of driving circuit structure,It can preferably keep the linearity of output voltage during soft handover,It includes pull-up current Ibiasp,Voltage source VPP,PMOS P1,Level translator,Second NMOS tube N2,Phase inverter I1,First pull-down current Ibiasn1,Electric capacity C1 one end,First NMOS tube N1,Phase inverter I1 input is driving input IN,First NMOS tube N1 drain terminal connection power vd D,Source is drive output OUT,It is characterized in that,It also includes control circuit,Control circuit includes the 5th NMOS tube N5 that grid end is connected with source,5th NMOS tube N5 source connection PMOS P1 source,5th NMOS tube N5 drain terminal connects the 3rd NMOS tube N3 drain terminal,4th NMOS tube N4 drain terminal,4th NMOS tube N4 grid end is connected with source,The grid end of 3rd NMOS tube connects the grid end of the second NMOS tube,Source connects second pull-down current Ibiasn2 one end,The second pull-down current Ibiasn2 other ends are grounded.

Description

A kind of driving circuit structure

Technical field

The present invention relates to analog power technical field, specially a kind of driving circuit structure.

Background technology

Common drive circuit is as shown in figure 1, by pulling up bigoted electric current Ibiasp, pull-down bias electric current Ibiasn to electricity The grid end capacitor charge and discharge for holding C1 and driving tube N1, N2 produces a linear voltage, but adds metal-oxide-semiconductor threshold voltage in power vd D More than Gate voltage changes when the basic output maintained close to supply voltage VDD of output, voltage change below can just allow defeated Go out OUT and follow linear change, otherwise cause output linearity degree poor.

The content of the invention

In order to solve the above problems, the invention provides a kind of driving circuit structure, and it can be during soft handover The linearity of output voltage can preferably be kept.

Its technical scheme is such：A kind of driving circuit structure, it includes pull-up current Ibiasp, the pull-up current Ibiasp one end connection voltage source VPP, the other end connection PMOS P1 drain terminal, the grid end connection level of the PMOS P1 turn The parallel operation other end connects the second NMOS tube N2 grid end, phase inverter I1 output end, and the input of the phase inverter I1 is driving Input IN, the second NMOS tube N2 source connect first pull-down current Ibiasn1 one end, first pull-down current The Ibiasn1 other ends are grounded, and the drain terminal of the second NMOS tube N2 connects the source of the PMOS P1, electric capacity C1 one end, the One NMOS tube N1 grid end, the electric capacity C1 other ends ground connection, the drain terminal connection power vd D of the first NMOS tube N1, source For drive output OUT, it is characterised in that it also includes control circuit, and the control circuit includes what grid end was connected with source 5th NMOS tube N5, the 5th NMOS tube N5 source connect the source of the PMOS P1, the 5th NMOS tube N5's Drain terminal connects the 3rd NMOS tube N3 drain terminal, the 4th NMOS tube N4 drain terminal, the grid end and source phase of the 4th NMOS tube N4 Even, the grid end of the 3rd NMOS tube connects the grid end of second NMOS tube, source connects the second pull-down current Ibiasn2 mono- End, the second pull-down current Ibiasn2 other ends ground connection.

After structure using the present invention, after adding control circuit, the first NMOS tube N1 grid end is only by normal soft handover The first pull-down current Ibiasn1 come slowly drag down, so as to avoid a high vpp voltage move to VDD supply voltages this Stage exports the more slowly phenomenon for causing output linearity degree difference of follow-up drop-down stage.

Brief description of the drawings

Fig. 1 is prior art circuits schematic diagram；

Fig. 2 is circuit diagram of the present invention.

Embodiment

As shown in Figure 2, a kind of driving circuit structure, it includes pull-up current Ibiasp, and pull-up current Ibiasp one end connects Voltage source VPP, other end connection PMOS P1 drain terminal are connect, VPP produces for internal pump or outside provide is higher than supply voltage The voltage source of a VDD logic circuit normal working voltage, PMOS P1 grid end connection level translator other end connection Second NMOS tube N2 grid end, phase inverter I1 output end, phase inverter I1 input are to drive input IN, the second NMOS tube N2 source connects first pull-down current Ibiasn1 one end, first pull-down current Ibiasn1 other ends ground connection, the second NMOS tube N2 drain terminal connection PMOS P1 source, electric capacity C1 one end, the first NMOS tube N1 grid end, electric capacity C1 other ends ground connection, the One NMOS tube N1 drain terminal connection power vd D, source are drive output OUT, and it also includes control circuit, and control circuit includes The 5th NMOS tube N5 that grid end is connected with source, the 5th NMOS tube N5 source connection PMOS P1 source, the 5th NMOS tube N5 drain terminal connects the 3rd NMOS tube N3 drain terminal, the 4th NMOS tube N4 drain terminal, the 4th NMOS tube N4 grid end and source phase Even, the grid end of the 3rd NMOS tube connects the grid end of the second NMOS tube, source connects second pull-down current Ibiasn2 one end, and second The pull-down current Ibiasn2 other ends are grounded.

Operation principle is as described below：When input signal IN is normally started by the moment of high step-down, soft handover pull-down circuit, this When quick pull-down current branch also begin to open, draw grid current when driving tube grid voltage is higher than power vd D, make grid Voltage rapid decrease, when grid voltage drops to below VDD, pull-down current provides VDD branch roads, the grid of driving tube only by The pull-down current branch road of normal soft handover slowly drags down, so as to avoid a high vpp voltage move to VDD supply voltages this The individual stage exports the more slowly phenomenon for causing output linearity degree difference of follow-up drop-down stage.

When driving input IN input signal by high step-down moment, due to reverser I1 effect, the electricity at node A From low to high, the second NMOS tube N2, the 3rd NMOS tube N3 conducting, the first pull-down current Ibiasn1 soft handovers pull-down circuit is just for pressure The first NMOS tube N1 is often drawn, now the second pull-down current Ibiasn2 also begins to open, and is higher than in the first NMOS tube N1 grid end voltages During power vd D, the 5th NMOS tube N5 conductings, the 4th NMOS tube N4 cut-offs, start and draw grid end electric current, under making grid end voltage quick Drop, when grid end voltage drops to below supply voltage VDD, the 5th NMOS tube N5 cut-offs, the 4th NMOS tube N4 is turned on, under second Sourcing current Ibiasn2 will be provided as the VDD branch roads where the 4th NMOS tube N4, and the first NMOS tube N1 grid end is only cut by normally soft The first pull-down current Ibiasn1 for changing slowly is dragged down, so as to avoid a high vpp voltage move to VDD supply voltages this The individual stage exports the more slowly phenomenon for causing output linearity degree difference of follow-up drop-down stage.

Claims

1. a kind of driving circuit structure, it includes pull-up current Ibiasp, and described pull-up current Ibiasp one end connects voltage source VPP, the other end connection PMOS P1 drain terminal, the grid end connection level translator of the PMOS P1, the level translator The other end connects the second NMOS tube N2 grid end, phase inverter I1 output end, and the input of the phase inverter I1 inputs for driving IN is held, the source of the second NMOS tube N2 connects first pull-down current Ibiasn1 one end, first pull-down current The Ibiasn1 other ends are grounded, and the drain terminal of the second NMOS tube N2 connects the source of the PMOS P1, electric capacity C1 one end, the One NMOS tube N1 grid end, the electric capacity C1 other ends ground connection, the drain terminal connection power vd D of the first NMOS tube N1, source For drive output OUT, it is characterised in that it also includes control circuit, and the control circuit includes what grid end was connected with source 5th NMOS tube N5, the 5th NMOS tube N5 source connect the source of the PMOS P1, the 5th NMOS tube N5's Drain terminal connects the 3rd NMOS tube N3 drain terminal, the 4th NMOS tube N4 drain terminal, the grid end and source phase of the 4th NMOS tube N4 Even, the grid end of the 3rd NMOS tube N3 connects the grid end of the second NMOS tube N2, the 3rd NMOS tube N3 sources connection Second pull-down current Ibiasn2 one end, the second pull-down current Ibiasn2 other ends ground connection.