CN203800914U - Grid electrode drive circuit and power switch circuit - Google Patents
Grid electrode drive circuit and power switch circuit Download PDFInfo
- Publication number
- CN203800914U CN203800914U CN201420224979.6U CN201420224979U CN203800914U CN 203800914 U CN203800914 U CN 203800914U CN 201420224979 U CN201420224979 U CN 201420224979U CN 203800914 U CN203800914 U CN 203800914U
- Authority
- CN
- China
- Prior art keywords
- transistor
- output
- semiconductor switch
- switch device
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electronic Switches (AREA)
- Power Conversion In General (AREA)
Abstract
A grid electrode drive circuit and a power switch circuit are disclosed. The grid electrode drive circuit comprises a power source end, a grounding end, an input end and an output end, wherein grid electrode drive input signals are received at an input end by the grid electrode drive circuit, grid electrode drive output signals for driving a semiconductor switch device are provided at an output end, and the grid electrode drive circuit also comprises a clamping end; when the grid electrode drive input signals are first electric levels, voltage difference between the output end and the clamping end is kept to be a first constant value by the grid electrode drive circuit; when the grid electrode drive input signals are second electric levels, voltage difference between the output end and the clamping end is kept to be a second constant value by the grid electrode drive circuit. Grid source voltage of a semiconductor switch can be kept to be constant voltage difference by the grid electrode drive circuit and does not change due to influence of loads. The semiconductor switch device can be protected from breakdown due to high grid source voltage by the grid electrode drive circuit.
Description
Technical field
The utility model relates to power switch circuit, relates to particularly the gate driver circuit for semiconductor switch device, the power switch circuit that comprises gate driver circuit and grid drive method.
Background technology
Power switch circuit for drive motor comprises semiconductor switch device, such as mos field effect transistor (MOSFET) and igbt (IGBT) etc.In power switch circuit, the high side semiconductor switch device being connected with feeder ear sometimes needs to bear the high voltage over 600V.Transverse diffusion metal oxide semiconductor field effect transistor (ldmos transistor) is included in source region and the drain region that identical region is injected twice and high temperature progradation forms.In ldmos transistor, the horizontal proliferation below grid of source region and drain region, forms a raceway groove with concentration gradient.In addition, the source region of ldmos transistor is formed in the well region with the conductivity type opposite doping type of ldmos transistor, and drain region is formed in the drift region with the high resistant of the conductivity type opposite doping type of device.Due to the existence of drift region, the drain electrode of LDMOS can be born high voltage.Ldmos transistor has advantages of large-drive-current, low on-resistance and high-breakdown-voltage, is widely used as the semiconductor switch device of power switch circuit, in particular as bearing high-tension high side semiconductor switch device.
Although the drain electrode of LDMOS can be born high voltage, the source configuration of ldmos transistor is still the same with conventional MOSFET.Ldmos transistor is easy to due to high gate source voltage V
gSand puncture.Therefore the high side semiconductor switch device that, need to design suitable gate driver circuit be ldmos transistor and so on provides suitable gate drive voltage.
Utility model content
The purpose of this utility model is to provide a kind of gate driver circuit of semiconductor switch device, the power switch circuit that comprises this gate driver circuit and grid drive method can protected at work.
According to first aspect of the present utility model, a kind of gate driver circuit is provided, comprise power end, earth terminal, input and output, described gate driver circuit receives gate drive input signal at input, at output, provide grid drive output signal, be used for driving semiconductor switch device, wherein, described gate driver circuit also comprises clamp end, and, when gate drive input signal is the first level, described gate driver circuit remains the first steady state value by the voltage difference between output and clamp end, when gate drive input signal is second electrical level, described gate driver circuit remains the second steady state value by the voltage difference between output and clamp end.
Preferably, in described gate driver circuit, described the first steady state value is greater than the second steady state value, and described the second steady state value is substantially equal to 0.
Preferably, in described gate driver circuit the first level higher than second electrical level.
Preferably, described gate driver circuit also comprises: be connected in series in successively the first resistance, the first transistor and the first current source between power end and ground; Be connected in series in successively the second current source, transistor seconds and the second resistance between power end and clamp end; Be connected in series in successively the 3rd current source, the 3rd transistor and the 4th transistor between power end and clamp end; And be connected to the 3rd resistance between output and clamp end, wherein, the 4th transistorized grid is connected to the intermediate node of transistor seconds and the second resistance, when gate drive input signal is the first level, the first transistor and the 3rd crystal will be managed conducting, and transistor seconds and the 4th transistor disconnect, and when gate drive input signal is second electrical level, the first transistor and the 3rd crystal will be managed disconnection, transistor seconds and the 4th transistor turns.
Preferably, described gate driver circuit also comprises: the first inverter, and its input is connected to the intermediate node of the first resistance and the first transistor, and its output is connected to the grid of transistor seconds; And second inverter, its input is connected to the output of the first inverter, and its input is connected to the 3rd transistorized grid.
Preferably, in described gate driver circuit, when gate drive input signal is the first level, the first transistor conducting, the output of the first inverter produces the first level, transistor seconds is disconnected, the output of the second inverter produces second electrical level, make the 3rd transistor turns, because transistor seconds disconnects, the 4th transistorized gate source voltage is poor is 0, the 4th transistor is disconnected, the 3rd current source produces constant current, and the 3rd resistance of flowing through produces constant voltage difference between output and clamp end; And when gate drive input signal is second electrical level, the first transistor disconnects, the output of the first inverter produces second electrical level, make transistor seconds conducting, the output of the second inverter produces the first level, and the 3rd transistor is disconnected, due to transistor seconds conducting, the 4th transistorized grid is the first level, makes the 4th transistor turns, output and clamp end short circuit.
Preferably, described gate driver circuit also comprises: be connected in series in successively the 4th resistance, the 5th transistor and the 4th current source between power end and ground; And first inverter, its input is connected to the input of gate driver circuit, its output is connected to the 5th transistorized grid, wherein, the 3rd transistorized grid is connected to the intermediate node of the first transistor and the first resistance, and the grid of transistor seconds is connected to the 4th resistance and the 5th transistorized intermediate node.
Preferably, in described gate driver circuit, when gate drive input signal is the first level, the first transistor conducting, at the 3rd transistorized grid, produce second electrical level, make the 3rd transistor turns, the output of the first inverter produces second electrical level, the 5th transistor is disconnected, correspondingly, transistor seconds and the 4th transistor disconnect, and the 3rd current source produces constant current, the 3rd resistance of flowing through produces constant voltage difference between output and clamp end; And when gate drive input signal is second electrical level, the first transistor disconnects, and at the 3rd transistorized grid, produces the first level, and the 3rd transistor is disconnected, the output of the first inverter produces the first level, make the 5th transistor turns, correspondingly, transistor seconds conducting, due to transistor seconds conducting, the 4th transistorized grid is the first level, makes the 4th transistor turns, output and clamp end short circuit.
Preferably, in described gate driver circuit, each in the first to the 3rd current source consists of auxiliary transistor.
Preferably, in described gate driver circuit, the first and the 4th transistor is the MOSFET of the first conduction type, and the second and the 3rd transistor is the MOSFET of the second conduction type.
Preferably, in described gate driver circuit, the first conduction type is a kind of in N-type and P type, and the second conduction type is the another kind in N-type and P type.
According to second aspect of the present utility model, a kind of power switch circuit is provided, comprising: be connected in series in successively the first high side semiconductor switch device and the first downside semiconductor switch device between the first supply voltage and ground; And first grid drive circuit as above, wherein, the first high side semiconductor switch device and the first downside semiconductor switch device comprise respectively source electrode, drain and gate, the power end of described first grid drive circuit is connected to second source voltage, and the output of described first grid drive circuit is connected with the grid of the first high side semiconductor switch device, the clamp end of described first grid drive circuit is connected with the source electrode of the first high side semiconductor switch device.
Preferably, in described power switch circuit, between the first high side semiconductor switch device and the intermediate node and ground of the first downside semiconductor switch device, provide load driving voltage.
Preferably, described power switch circuit also comprises: be connected in series in successively the second high side semiconductor switch device and the second downside semiconductor switch device between the first supply voltage and ground; And second grid drive circuit as above, wherein, the second high side semiconductor switch device and the second downside semiconductor switch device comprise respectively source electrode, drain and gate, the power end of described second grid drive circuit is connected to second source voltage, and the output of described second grid drive circuit is connected with the grid of the second high side semiconductor switch device, the clamp end of described second grid drive circuit is connected with the source electrode of the second high side semiconductor switch device.
Preferably, in described power switch circuit, between the intermediate node and the second high side semiconductor switch device and the intermediate node of the second downside semiconductor switch device of the first high side semiconductor switch device and the first downside semiconductor switch device, provide load driving voltage.
Preferably, in described power switch circuit, the first high side semiconductor switch device and the first downside semiconductor switch device are respectively the MOSFET of identical conduction type.
Preferably, in described power switch circuit, the first high side semiconductor switch device and the first downside semiconductor switch device are respectively ldmos transistor.
Preferably, in described power switch circuit, second source voltage is 2 multiple value of the first supply voltage.
According to the third aspect of the present utility model, provide a kind of for driving the grid drive method of semiconductor switch device, comprise: at input, receive gate drive input signal, and provide grid drive output signal at output, wherein, when gate drive input signal is the first level, the voltage difference between output and clamp end is remained to the first steady state value, when gate drive input signal is second electrical level, the voltage difference between output and clamp end is remained to the second steady state value.
Preferably, in described method, described the first steady state value is greater than the second steady state value, and described the second steady state value is substantially equal to 0.
Preferably, in described method, the first level is higher than second electrical level.
According to the gate driver circuit of embodiment of the present utility model, in the whole control cycle of semiconductor switch device, can keep the output of gate driver circuit and the voltage difference between clamp end to be always constant voltage difference or 0, thereby by the gate source voltage V of ldmos transistor
gSremain this constant voltage difference or 0, and can not change due to the impact of load.At work, this gate driver circuit can guarantee that the normal switch of semiconductor switch device switches, and protects the semiconductor switch device can be because high voltage punctures simultaneously.
Accompanying drawing explanation
By the description to the utility model embodiment referring to accompanying drawing, above-mentioned and other objects of the present utility model, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 is according to the schematic circuit of the power switch circuit of prior art;
Fig. 2 be shown in Fig. 1 according to the oscillogram of the power switch circuit of prior art;
Fig. 3 is according to the schematic circuit of the power switch circuit of embodiment of the present utility model; And
Fig. 4 is for according to the first example of the gate driver circuit adopting in the power switch circuit of embodiment of the present utility model; And
Fig. 5 is for according to the second example of the gate driver circuit adopting in the power switch circuit of embodiment of the present utility model.
Embodiment
Hereinafter with reference to accompanying drawing, various embodiment of the present utility model is described in more detail.In each accompanying drawing, identical element adopts same or similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.
Fig. 1 is according to the schematic circuit of the power switch circuit of prior art.In the configuration of prior art, power switch circuit can comprise two ldmos transistors that are arranged to half H bridge, or four layouts help the ldmos transistor of H bridge, for driving load.
In the power switch circuit shown in Fig. 1, show according to four ldmos transistor M1-M4 of full H bridge configuration.First group of two ldmos transistor M1 and M3 are connected between power supply VCC and ground GND, and second group of two ldmos transistor M2 and M4 are connected between power supply VCC and ground GND, form symmetrical brachium pontis.Between the intermediate node of first group of two ldmos transistor M1 and M3 and second group of two ldmos transistor M2 and the intermediate node of M4, connect load.Be connected to two ldmos transistor M1 between power supply VCC and intermediate node and M2 respectively as high-side switch, be connected to two ldmos transistor M3 between intermediate node and ground GND and M4 respectively as low side switch.Power switch circuit also comprises charge pump U0, for generation of the voltage of 2 times of power supply VCC, i.e. 2*VCC.Gate driver circuit U1-U4 comprises respectively input, output, power end and earth terminal.The output of gate driver circuit U1-U4 is connected with the grid of ldmos transistor M1-M4 respectively, to control its conducting or disconnection.The power end of gate driver circuit U1 and U2 is connected with charge pump U0, and to obtain the supply voltage of 2*VCC, the power end of gate driver circuit U3 and U4 is connected directly to power supply VCC.
Fig. 2 is the oscillogram of the power switch circuit shown in Fig. 1.The input A1 of gate driver circuit U1 receives identical first grid drive input signal with the input B2 of gate driver circuit U4.When first grid drive input signal is the first level, the output H1 of gate driver circuit U1 provides for example first grid drive output signal of 2*VCC, and the output L2 of gate driver circuit U4 provides the 4th grid drive output signal of VCC.When first grid drive input signal is second electrical level, the grid drive output signal of the output H1 of gate driver circuit U1 and the output L2 of gate driver circuit U4 is second electrical level, for example GND.In one example, the first level is higher than second electrical level.The input A2 of gate driver circuit U2 receives identical second grid drive input signal with the input B1 of gate driver circuit U3.When second grid drive input signal is the first level, the output H2 of gate driver circuit U2 provides for example second grid drive output signal of 2*VCC, and the output L1 of gate driver circuit U3 provides the 3rd grid drive output signal of VCC.When second grid drive input signal is second electrical level, the grid drive output signal of the output H2 of gate driver circuit U2 and the output L1 of gate driver circuit U3 is second electrical level, for example GND.
The grid of ldmos transistor M1 in first group of ldmos transistor (i.e. the first high-side switch) receives identical grid drive output signal with the grid of ldmos transistor M4 (i.e. the second low side switch) in second group of ldmos transistor, thereby conducting simultaneously or disconnection.Similarly, the grid of ldmos transistor M2 in second group of ldmos transistor (i.e. the second high-side switch) receives identical grid drive output signal with the grid of ldmos transistor M3 (i.e. the first low side switch) in first group of ldmos transistor, thereby conducting simultaneously or disconnection.This power switch circuit exists two kinds of operating states, in the first operating state, ldmos transistor M1 and M4 conducting, and ldmos transistor M2 and M3 disconnect, in the second operating state, ldmos transistor M1 and M4 disconnect, and ldmos transistor M2 and M3 conducting, thereby alternately to load, provide electric current.As the ldmos transistor M1 of high-side switch,
M2 has respectively the drain electrode being connected with VCC and the source electrode being connected with load, and in its conducting state, electric current flows to load from power supply VCC, on its source voltage, draws as VCC.Ldmos transistor M3, M4 as low side switch have respectively the drain electrode being connected with load and the source electrode being connected with ground GND, and its source voltage remains GND.
Take the first operating state as example, and in ldmos transistor M1 conducting, its grid voltage is 2*VCC.If motor normally starts, on its source voltage, draw as VCC gate source voltage V
gS=2*VCC-VCC.Yet if motor fails to start in time, the source voltage of ldmos transistor M1 is likely very low.The V of ldmos transistor M1
gSlikely, much larger than VCC, even reach 2*VCC.As a result, ldmos transistor M1 is easy to due to high gate source voltage V
gSand puncture.Similarly, in the second operating state, ldmos transistor M2 is easy to equally due to high gate source voltage V
gSand puncture.
In addition, similar with the full bridge configuration shown in Fig. 1, in half H bridge configuration, two ldmos transistors are connected between power supply VCC and ground GND.Between the intermediate node and ground GND of two ldmos transistors, connect load.At work, two ldmos transistor alternate conduction, thus to load, provide electric current.Ldmos transistor for high-side switch also may be due to high gate source voltage V
gSand puncture.
Fig. 3 is according to the schematic circuit of the power switch circuit of embodiment of the present utility model.Figure 3 illustrates according to four ldmos transistor M1-M4 of full H bridge configuration.Power switch circuit also comprises charge pump U0, for generation of the voltage of 2 times of power supply VCC, i.e. 2*VCC.Four gate driver circuit U1-U4 comprise respectively input, output, power end and earth terminal.The output of four gate driver circuit U1-U4 is connected with the grid of four ldmos transistor M1-M4 respectively, to control its conducting or disconnection.The power end of high side gate driver circuit U1 and U2 is connected with charge pump U0, and to obtain the supply voltage of 2*VCC, the power end of lowside gate drive circuit U3 and U4 is connected directly to power supply VCC.
Different from the power switch circuit according to prior art shown in Fig. 1, for two gate driver circuit U1 and the U2 of high-side switch, comprise respectively additional clamp end S1 and S2.The clamp end S1 of gate driver circuit U1 is connected with the source electrode of ldmos transistor M1.In ldmos transistor M1 conduction period, the voltage between the output H1 of gate driver circuit U1 and clamp end S1 is always steady state value, thereby by the gate source voltage V of ldmos transistor M1
gSremain this steady state value, and can be because high voltage punctures.Similarly, the clamp end S2 of gate driver circuit U2 is connected with the source electrode of ldmos transistor M2.In ldmos transistor M2 conduction period, the voltage difference between the output H2 of gate driver circuit U2 and clamp end S2 is always steady state value, thereby by the gate source voltage V of ldmos transistor M2
gSremain this steady state value, and can be because high voltage punctures.
In addition, similar with the full bridge configuration shown in Fig. 3, in half H bridge configuration, two ldmos transistors are connected between power supply VCC and ground GND.Between the intermediate node and ground GND of two ldmos transistors, connect load.At work, two ldmos transistor alternate conduction, thus to load, provide electric current.High side gate driver circuit comprises input, output, power end and earth terminal, and additional clamp end.The clamp end of this gate driver circuit is connected with the source electrode of the ldmos transistor for high-side switch.
Fig. 4 for according to the gate driver circuit U1 adopting in the power switch circuit of embodiment of the present utility model the first example.Gate driver circuit U1 comprises input A1, output H1, power end 2*VCC and earth terminal GND, and additional clamp end S1.
The first resistance R 1, the first transistor M11 and the first current source Id1 are connected in series between power end 2*VCC and ground GND successively.The grid of the first transistor M11 is connected with input A1.The second current source Id2, transistor seconds M12 and the second resistance R 2 are connected in series between power end 2*VCC and clamp end S1 successively.The input of the first inverter N1 is connected to the intermediate node of the first resistance R 1 and the first transistor M11, and its output is connected to the grid of transistor seconds M12.The 3rd current source Id3, the 3rd transistor M13 and the 4th transistor M14 are connected in series between power end 2*VCC and clamp end S1 successively.The grid of the 4th transistor M14 is connected to the intermediate node of transistor seconds M12 and the second resistance R 2.The input of the second inverter N2 is connected to the output of the first inverter N1, and its output is connected to the grid of the 3rd transistor M13.The intermediate node of the 3rd transistor M13 and the 4th transistor M14 is connected to output H1.The 3rd resistance is connected between output H1 and clamp end S1.
The first level of the first inverter N1 and the second inverter N2 is output as 2*VCC, and second electrical level is output as VCC.Under the control of the first inverter N1 and the second inverter N2, transistor seconds M12 and the 3rd transistor M13 alternate conduction and disconnection.
In the embodiment shown in fig. 4, the first transistor M11 and the 4th transistor M14 are N-type MOSFET, and transistor seconds M12 and the 3rd transistor M13 are P type MOSFET.In alternative embodiment, each in first to fourth transistor M11-M14 can be all N-type MOSFET or P type MOSFET.In addition, the first to the 3rd above-mentioned current source Id1-Id3 can consist of auxiliary transistor respectively.
At work, the input A1 of gate driver circuit U1 receives gate drive input signal as shown in Figure 2, for example pwm signal.
When gate drive input signal is the first level, the first transistor M11 conducting.The first current source Id1 produces constant current, from power end 2*VCC, via the first resistance R 1, flow to ground GND.Input at the first inverter N1 produces second electrical level.The output of the first inverter N1 produces the first level, and transistor seconds M12 is disconnected.The output of the second inverter N2 produces second electrical level, makes the 3rd transistor M13 conducting.Meanwhile, because transistor seconds M12 disconnects, the gate source voltage of the 4th transistor M14 is poor is 0, and the 4th transistor M14 is disconnected.As a result, the 3rd current source Id3 produces constant current, from power end 2*VCC, via the 3rd resistance R 3, flow to ground GND.At the 3rd resistance R 3 two ends, constant voltage difference will be produced.Like this, the gate source voltage V of high side LDMOSM1
gSremain constant voltage difference, and can not change due to the impact of load.
When gate drive input signal is second electrical level, the first transistor M11 cut-off.Input at the first inverter N1 produces the first level.The output of the first inverter N1 produces second electrical level, makes transistor seconds M12 conducting.The output of the second inverter N2 produces the first level, and the 3rd transistor M13 is disconnected.Meanwhile, due to transistor seconds M12 conducting, the constant current that the second constant-current source Id2 produces flow to ground GND via the second resistance R 2.Grid at the 4th transistor M14 produces the first level, makes the 4th transistor M14 conducting.As a result, short circuit between output H1 and clamp end S1.Like this, the gate source voltage V of high side LDMOS M1
gSremain 0, and can not change due to the impact of load.
As can be seen here, in the whole cycle of pwm signal, the gate source voltage V of high side LDMOS M1
gSall can remain constant voltage difference, or be 0, and can not be subject to the impact of the change in voltage of load.By changing the numerical value of the 3rd current source and the 3rd resistance, the gate source voltage V in the time of can also controlling high side LDMOS M1 conducting
gSnumerical value.
Fig. 5 for according to the gate driver circuit U1 adopting in the power switch circuit of embodiment of the present utility model the second example.Gate driver circuit U1 comprises input A1, output H1, power end 2*VCC and earth terminal GND, and additional clamp end S1.
The first resistance R 1, the first transistor M11 and the first current source Id1 are connected in series between power end 2*VCC and ground GND successively.The grid of the first transistor M11 is connected with input A1.The second current source Id2, transistor seconds M12 and the second resistance R 2 are connected in series between power end 2*VCC and clamp end S1 successively.The 3rd current source Id3, the 3rd transistor M13 and the 4th transistor M14 are connected in series between power end 2*VCC and clamp end S1 successively.The grid of the 3rd transistor M13 is connected to the intermediate node of the first transistor M11 and the first resistance R 1.The grid of the 4th transistor M14 is connected to the intermediate node of transistor seconds M12 and the second resistance R 2.The intermediate node of the 3rd transistor M13 and the 4th transistor M14 is connected to output H1.The 3rd resistance is connected between output H1 and clamp end S1.The 4th resistance R 4, the 5th transistor M15 and the 4th current source Id4 are connected in series between power end 2*VCC and ground GND successively.The input of the first inverter N1 is connected with input A1, and its output is connected to the grid of the 5th transistor M15.The grid of transistor seconds M12 is connected to the intermediate node of the 5th transistor M15 and the 4th resistance R 4.
Under the control of the first inverter N1 and the 5th transistor M15, transistor seconds M12 and the 3rd transistor M13 alternate conduction and disconnection.
In the embodiment shown in fig. 5, the first transistor M11, the 4th transistor M14 and the 5th transistor M15 are N-type MOSFET, and transistor seconds M12 and the 3rd transistor M13 are P type MOSFET.In alternative embodiment, each in first to fourth transistor M11-M14 can be all N-type MOSFET or P type MOSFET.In addition, first to fourth above-mentioned current source Id1-Id4 can consist of auxiliary transistor respectively.
At work, the input A1 of gate driver circuit U1 receives gate drive input signal as shown in Figure 2, for example pwm signal.When gate drive input signal is the first level, the first transistor M11 conducting.The first current source Id1 produces constant current, from power end 2*VCC, via the first resistance R 1, flow to ground GND.Grid at the 3rd transistor M13 produces second electrical level, makes the 3rd transistor M13 conducting.The output of the first inverter N1 produces second electrical level, and the 5th transistor M15 is disconnected.Correspondingly, transistor seconds M12 and the 4th transistor M14 all disconnect.As a result, the 3rd current source Id3 produces constant current, from power end 2*VCC, via the 3rd resistance R 3, flow to ground GND.At the 3rd resistance R 3 two ends, constant voltage difference will be produced.Like this, the gate source voltage V of high side LDMOS M1
gSremain constant voltage difference, and can not change due to the impact of load.
When gate drive input signal is second electrical level, the first transistor M11 disconnects.Grid at the 3rd transistor M13 produces the first level, and the 3rd transistor M13 is disconnected.The output of the first inverter N1 produces the first level, makes the 5th transistor M15 conducting.Correspondingly, transistor seconds M12 conducting.Due to transistor seconds M12 conducting, the constant current that the second constant-current source Id2 produces flow to ground GND via the second resistance R 2.Grid at the 4th transistor M14 produces the first level, makes the 4th transistor M14 conducting.As a result, short circuit between output H1 and clamp end S1.Like this, the gate source voltage V of high side LDMOS M1
gSremain 0, and can not change due to the impact of load.
As can be seen here, in the whole cycle of pwm signal, the gate source voltage V of high side LDMOS M1
gSall can remain constant voltage difference, or be 0, and can not be subject to the impact of the change in voltage of load.By changing the numerical value of the 3rd current source and the 3rd resistance, the gate source voltage V in the time of can also controlling high side LDMOS M1 conducting
gSnumerical value.
According to the gate driver circuit U1 of embodiment of the present utility model, in the whole control cycle of ldmos transistor M1, can keep the output H1 of gate driver circuit U1 and the voltage difference between clamp end S1 to be always constant voltage difference or 0, thereby by the gate source voltage V of ldmos transistor M1
gSremain this constant voltage difference or 0, and can be because high voltage punctures.
According to embodiment of the present utility model as described above, these embodiment do not have all details of detailed descriptionthe, and also not limiting this utility model is only described specific embodiment.Obviously, according to above description, can make many modifications and variations.These embodiment are chosen and specifically described to this specification, is in order to explain better principle of the present utility model and practical application, thereby under making, technical field technical staff can utilize the utility model and the modification on the utility model basis to use well.The scope that protection range of the present utility model should be defined with the utility model claim is as the criterion.
Claims (18)
1. a gate driver circuit, comprises power end, earth terminal, input and output, and described gate driver circuit receives gate drive input signal at input, at output, provides grid drive output signal, for driving semiconductor switch device,
Wherein, described gate driver circuit also comprises clamp end, and, when gate drive input signal is the first level, described gate driver circuit remains the first steady state value by the voltage difference between output and clamp end, when gate drive input signal is second electrical level, described gate driver circuit remains the second steady state value by the voltage difference between output and clamp end.
2. gate driver circuit according to claim 1, wherein said the first steady state value is greater than the second steady state value, and described the second steady state value is substantially equal to 0.
3. gate driver circuit according to claim 1, wherein the first level is higher than second electrical level.
4. gate driver circuit according to claim 1, also comprises:
Be connected in series in successively the first resistance, the first transistor and the first current source between power end and ground;
Be connected in series in successively the second current source, transistor seconds and the second resistance between power end and clamp end;
Be connected in series in successively the 3rd current source, the 3rd transistor and the 4th transistor between power end and clamp end; And
Be connected to the 3rd resistance between output and clamp end,
Wherein, the 4th transistorized grid is connected to the intermediate node of transistor seconds and the second resistance,
When gate drive input signal is the first level, the first transistor and the 3rd crystal will be managed conducting, and transistor seconds and the 4th transistor disconnect, and
When gate drive input signal is second electrical level, the first transistor and the 3rd crystal will be managed disconnection, transistor seconds and the 4th transistor turns.
5. gate driver circuit according to claim 4, also comprises:
The first inverter, its input is connected to the intermediate node of the first resistance and the first transistor, and its output is connected to the grid of transistor seconds; And
The second inverter, its input is connected to the output of the first inverter, and its input is connected to the 3rd transistorized grid.
6. gate driver circuit according to claim 5, wherein
When gate drive input signal is the first level, the first transistor conducting, the output of the first inverter produces the first level, and transistor seconds is disconnected, the output of the second inverter produces second electrical level, make the 3rd transistor turns, because transistor seconds disconnects, the 4th transistorized gate source voltage is poor is 0, the 4th transistor is disconnected, the 3rd current source produces constant current, and the 3rd resistance of flowing through produces constant voltage difference between output and clamp end; And
When gate drive input signal is second electrical level, the first transistor disconnects, the output of the first inverter produces second electrical level, make transistor seconds conducting, the output of the second inverter produces the first level, and the 3rd transistor is disconnected, due to transistor seconds conducting, the 4th transistorized grid is the first level, makes the 4th transistor turns, output and clamp end short circuit.
7. gate driver circuit according to claim 4, also comprises:
Be connected in series in successively the 4th resistance, the 5th transistor and the 4th current source between power end and ground; And
The first inverter, its input is connected to the input of gate driver circuit, and its output is connected to the 5th transistorized grid,
Wherein, the 3rd transistorized grid is connected to the intermediate node of the first transistor and the first resistance, and the grid of transistor seconds is connected to the 4th resistance and the 5th transistorized intermediate node.
8. gate driver circuit according to claim 7, wherein
When gate drive input signal is the first level, the first transistor conducting, at the 3rd transistorized grid, produce second electrical level, make the 3rd transistor turns, the output of the first inverter produces second electrical level, the 5th transistor is disconnected, correspondingly, transistor seconds and the 4th transistor disconnect, and the 3rd current source produces constant current, the 3rd resistance of flowing through produces constant voltage difference between output and clamp end; And
When gate drive input signal is second electrical level, the first transistor disconnects, and at the 3rd transistorized grid, produces the first level, and the 3rd transistor is disconnected, the output of the first inverter produces the first level, make the 5th transistor turns, correspondingly, transistor seconds conducting, due to transistor seconds conducting, the 4th transistorized grid is the first level, makes the 4th transistor turns, output and clamp end short circuit.
9. gate driver circuit according to claim 4, wherein, each in the first to the 3rd current source consists of auxiliary transistor.
10. gate driver circuit according to claim 4, wherein the first and the 4th transistor is the MOSFET of the first conduction type, the second and the 3rd transistor is the MOSFET of the second conduction type.
11. gate driver circuits according to claim 10, wherein the first conduction type is a kind of in N-type and P type, the second conduction type is the another kind in N-type and P type.
12. 1 kinds of power switch circuits, comprising:
Be connected in series in successively the first high side semiconductor switch device and the first downside semiconductor switch device between the first supply voltage and ground; And
According to the first grid drive circuit described in any one in claim 1-11,
Wherein, the first high side semiconductor switch device and the first downside semiconductor switch device comprise respectively source electrode, drain and gate,
The power end of described first grid drive circuit is connected to second source voltage, and
The output of described first grid drive circuit is connected with the grid of the first high side semiconductor switch device, and the clamp end of described first grid drive circuit is connected with the source electrode of the first high side semiconductor switch device.
13. power switch circuits according to claim 12, wherein, between the first high side semiconductor switch device and the intermediate node and ground of the first downside semiconductor switch device, provide load driving voltage.
14. power switch circuits according to claim 12, also comprise:
Be connected in series in successively the second high side semiconductor switch device and the second downside semiconductor switch device between the first supply voltage and ground; And
According to the second grid drive circuit described in any one in claim 1-11,
Wherein, the second high side semiconductor switch device and the second downside semiconductor switch device comprise respectively source electrode, drain and gate,
The power end of described second grid drive circuit is connected to second source voltage, and
The output of described second grid drive circuit is connected with the grid of the second high side semiconductor switch device, and the clamp end of described second grid drive circuit is connected with the source electrode of the second high side semiconductor switch device.
15. power switch circuits according to claim 14, wherein, between the intermediate node and the second high side semiconductor switch device and the intermediate node of the second downside semiconductor switch device of the first high side semiconductor switch device and the first downside semiconductor switch device, provide load driving voltage.
16. according to the power switch circuit described in any one in claim 12-15, and wherein the first high side semiconductor switch device and the first downside semiconductor switch device are respectively the MOSFET of identical conduction type.
17. power switch circuits according to claim 16, wherein the first high side semiconductor switch device and the first downside semiconductor switch device are respectively ldmos transistor.
18. according to the power switch circuit described in any one in claim 12-15, and wherein second source voltage is 2 multiple value of the first supply voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420224979.6U CN203800914U (en) | 2014-04-30 | 2014-04-30 | Grid electrode drive circuit and power switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420224979.6U CN203800914U (en) | 2014-04-30 | 2014-04-30 | Grid electrode drive circuit and power switch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203800914U true CN203800914U (en) | 2014-08-27 |
Family
ID=51383098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420224979.6U Expired - Fee Related CN203800914U (en) | 2014-04-30 | 2014-04-30 | Grid electrode drive circuit and power switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203800914U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104320118A (en) * | 2014-11-06 | 2015-01-28 | 无锡普雅半导体有限公司 | Drive circuit structure |
| CN104317343A (en) * | 2014-09-30 | 2015-01-28 | 山东华芯半导体有限公司 | Circuit and method for keeping constant threshold voltage of MOS (Metal Oxide Semiconductor) transistor |
| CN103929162B (en) * | 2014-04-30 | 2017-09-26 | 杭州士兰微电子股份有限公司 | Gate driving circuit, power switch circuit and grid drive method |
| CN111262457A (en) * | 2018-12-03 | 2020-06-09 | 雅达电子国际有限公司 | Rectifier circuit for electrical power supply |
| CN112104205A (en) * | 2020-08-14 | 2020-12-18 | 西安工程大学 | Full-bridge inverter circuit grid driving circuit with midpoint voltage tracking function |
| CN112350552A (en) * | 2020-10-29 | 2021-02-09 | 西安微电子技术研究所 | MOSFET driver with output peak current not affected by power supply voltage change |
-
2014
- 2014-04-30 CN CN201420224979.6U patent/CN203800914U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103929162B (en) * | 2014-04-30 | 2017-09-26 | 杭州士兰微电子股份有限公司 | Gate driving circuit, power switch circuit and grid drive method |
| CN104317343A (en) * | 2014-09-30 | 2015-01-28 | 山东华芯半导体有限公司 | Circuit and method for keeping constant threshold voltage of MOS (Metal Oxide Semiconductor) transistor |
| CN104317343B (en) * | 2014-09-30 | 2016-04-27 | 山东华芯半导体有限公司 | A kind of keep metal-oxide-semiconductor threshold voltage constant circuit and method |
| CN104320118A (en) * | 2014-11-06 | 2015-01-28 | 无锡普雅半导体有限公司 | Drive circuit structure |
| CN104320118B (en) * | 2014-11-06 | 2017-12-12 | 无锡普雅半导体有限公司 | A kind of driving circuit structure |
| CN111262457A (en) * | 2018-12-03 | 2020-06-09 | 雅达电子国际有限公司 | Rectifier circuit for electrical power supply |
| CN112104205A (en) * | 2020-08-14 | 2020-12-18 | 西安工程大学 | Full-bridge inverter circuit grid driving circuit with midpoint voltage tracking function |
| CN112350552A (en) * | 2020-10-29 | 2021-02-09 | 西安微电子技术研究所 | MOSFET driver with output peak current not affected by power supply voltage change |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203800914U (en) | Grid electrode drive circuit and power switch circuit | |
| CN103929162A (en) | Gate drive circuit, power switching circuit and gate drive method | |
| US20140028375A1 (en) | Semiconductor device, and inverter, converter and power conversion device employing the same | |
| US20160315553A1 (en) | Rectifier, Alternator, and Power Converter | |
| CN101686046B (en) | Method for driving new grid electrode of H-bridge circuit | |
| CN104578026A (en) | Semiconductor device | |
| US10944392B2 (en) | Switch circuit and power supply system | |
| CN102033560B (en) | Voltage regulator | |
| CN103219979B (en) | Radio frequency switch, auxiliary voltage generating unit for a radio frequency switch, and method of obtaining auxiliary voltage for a radio frequency switch | |
| US20130248923A1 (en) | Bi-directional switch using series connected n-type mos devices in parallel with series connected p-type mos devices | |
| US9496708B2 (en) | Electric motor drive isolation circuit | |
| CN104067495A (en) | Driver circuit | |
| CN105122452A (en) | Semiconductor apparatus | |
| CN102207743A (en) | Internal power supply voltage generation circuit | |
| US8836380B2 (en) | Bootstrap circuit | |
| CN103190067B (en) | Drive circuit and inverter circuit | |
| CN103890682A (en) | Driver circuit for a semiconductor power switch | |
| CN105684312A (en) | Semiconductor device | |
| RU2012128929A (en) | DEVICE FOR SUPPLYING THE SUPPLY VOLTAGE IN THE BUS TYPE OF THE BUS NETWORK | |
| CN104508980A (en) | Device for controlling at least one transistor | |
| CN105929886A (en) | Reference Voltage Circuit And Electronic Device | |
| CN103219947A (en) | Voltage regulator | |
| US10312913B2 (en) | Level shifter | |
| CN206946908U (en) | High side gate driver | |
| US20130265684A1 (en) | Switching circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140827 Termination date: 20190430 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |