CN104320118A

CN104320118A - Drive circuit structure

Info

Publication number: CN104320118A
Application number: CN201410616465.XA
Authority: CN
Inventors: 李兆桂; 陈涛
Original assignee: WUXI PUYA SEMICONDUCTOR CO Ltd
Current assignee: Praran semiconductor (Shanghai) Co., Ltd
Priority date: 2014-11-06
Filing date: 2014-11-06
Publication date: 2015-01-28
Anticipated expiration: 2034-11-06
Also published as: CN104320118B

Abstract

The invention relates to the technical field of analog power sources, in particular to a drive circuit structure. The drive circuit structure can well maintain the linearity of output voltages in the soft handover process. The drive circuit structure comprises a pull-up current Ibiasp, a voltage source VPP, a PMOS transistor P1, a level shifter, a second NMOS transistor N2, a phase inverter I1, a first pull-down current Ibiasn1, one end of a capacitor C1 and a first NMOS transistor N1. The input end of the phase inverter I1 serves as a drive input end IN, the drain end of the first NMOS transistor N1 is connected with a power source VDD, and the source end of the first NMOS transistor N1 serves as a drive output end OUT. The drive circuit structure is characterized by further comprising a control circuit, the control circuit comprises a fifth NMOS transistor N5 with the grid end and the source end connected, the source end of the fifth NMOS transistor N5 is connected with the source end of the PMOS transistor P1, the drain end of the fifth NMOS transistor N5 is connected with the drain end of a third NMOS transistor N3 and the drain end of a fourth NMOS transistor N4, the grid end of the forth NMOS transistor N4 is connected with the source end, the grid end of the third NMOS transistor is connected with the grid end of the second NMOS transistor, the source end of the third NMOS transistor is connected with one end of a second pull-down current Ibiasn2, and the other end of the second pull-down current Ibiasn2 is grounded.

Description

A kind of driving circuit structure

Technical field

The present invention relates to analog power technical field, be specially a kind of driving circuit structure.

Background technology

Common drive circuit as shown in Figure 1, a linear voltage is produced by the bigoted current Ib iasp of pull-up, the pull-down bias current Ib iasn grid end capacitor charge and discharge to electric capacity C1 and driving tube N1, N2, but the basic output maintained close to supply voltage VDD is exported when power vd D adds the Gate change in voltage of more than metal-oxide-semiconductor threshold voltage, change in voltage below just can allow output OUT follow linear change, otherwise causes output linearity degree poor.

Summary of the invention

In order to solve the problem, the invention provides a kind of driving circuit structure, it can keep the linearity of output voltage preferably in the process of soft handover.

Its technical scheme is such: a kind of driving circuit structure, it comprises pull-up current Ibiasp, described pull-up current Ibiasp one end connects voltage source V PP, the other end connects the drain terminal of PMOS P1, the grid end connection level translator other end of described PMOS P1 connects the grid end of the second NMOS tube N2, the output of inverter I1, the input of described inverter I1 is for driving input IN, the source of described second NMOS tube N2 connects first pull-down current Ibiasn1 one end, described first pull-down current Ibiasn1 other end ground connection, the drain terminal of described second NMOS tube N2 connects the source of described PMOS P1, electric capacity C1 one end, the grid end of the first NMOS tube N1, described electric capacity C1 other end ground connection, the drain terminal of described first NMOS tube N1 connects power vd D, source is drive output OUT, it is characterized in that, it also comprises control circuit, described control circuit comprises the 5th NMOS tube N5 that grid end is connected with source, the source of described 5th NMOS tube N5 connects the source of described PMOS P1, the drain terminal of described 5th NMOS tube N5 connects the drain terminal of the 3rd NMOS tube N3, the drain terminal of the 4th NMOS tube N4, the grid end of described 4th NMOS tube N4 is connected with source, the grid end of described 3rd NMOS tube connects the grid end of described second NMOS tube, source connects second pull-down current Ibiasn2 one end, described second pull-down current Ibiasn2 other end ground connection.

After adopting structure of the present invention, after adding control circuit, the grid end of the first NMOS tube N1 is only slowly dragged down by the first pull-down current Ibiasn1 of normal soft handover, thus avoids and move this stage of VDD supply voltage at a high vpp voltage to export the follow-up drop-down stage much slow to cause the phenomenon of output linearity degree difference.

Accompanying drawing explanation

Fig. 1 is prior art circuits schematic diagram;

Fig. 2 is circuit diagram of the present invention.

Embodiment

As shown in Figure 2, a kind of driving circuit structure, it comprises pull-up current Ibiasp, pull-up current Ibiasp one end connects voltage source V PP, the other end connects the drain terminal of PMOS P1, VPP produces for inner pump or outside provides the voltage source of a logical circuit normal working voltage higher than supply voltage VDD, the grid end connection level translator other end of PMOS P1 connects the grid end of the second NMOS tube N2, the output of inverter I1, the input of inverter I1 is for driving input IN, the source of the second NMOS tube N2 connects first pull-down current Ibiasn1 one end, first pull-down current Ibiasn1 other end ground connection, the drain terminal of the second NMOS tube N2 connects the source of PMOS P1, electric capacity C1 one end, the grid end of the first NMOS tube N1, electric capacity C1 other end ground connection, the drain terminal of the first NMOS tube N1 connects power vd D, source is drive output OUT, it also comprises control circuit, control circuit comprises the 5th NMOS tube N5 that grid end is connected with source, the source of the 5th NMOS tube N5 connects the source of PMOS P1, the drain terminal of the 5th NMOS tube N5 connects the drain terminal of the 3rd NMOS tube N3, the drain terminal of the 4th NMOS tube N4, the grid end of the 4th NMOS tube N4 is connected with source, the grid end of the 3rd NMOS tube connects the grid end of the second NMOS tube, source connects second pull-down current Ibiasn2 one end, second pull-down current Ibiasn2 other end ground connection.

Operation principle is as described below: when input signal IN is by the moment of high step-down, soft handover pull-down circuit normally starts, now the current branch of quick pull-down also starts to open, grid current is drawn higher than during power vd D at driving tube grid voltage, grid voltage is declined fast, when grid voltage drops to below VDD, VDD branch road provides by pull-down current, the grid of driving tube is only slowly dragged down by the pull-down current branch road of normal soft handover, thus avoid and move this stage of VDD supply voltage at a high vpp voltage to export the follow-up drop-down stage much slow to cause the phenomenon of output linearity degree difference.

When driving the moment of input signal by high step-down of input IN, due to the effect of reverser I1, the voltage at node A place from low to high, second NMOS tube N2, 3rd NMOS tube N3 conducting, first pull-down current Ibiasn1 soft handover pull-down circuit normally draws the first NMOS tube N1, now the second pull-down current Ibiasn2 also starts to open, when the first NMOS tube N1 grid terminal voltage is higher than power vd D, 5th NMOS tube N5 conducting, 4th NMOS tube N4 cut-off, start and draw grid end electric current, grid terminal voltage is declined fast, when grid terminal voltage drops to below supply voltage VDD, 5th NMOS tube N5 cut-off, 4th NMOS tube N4 conducting, VDD branch road by the 4th NMOS tube N4 place provides by the second pull-down current Ibiasn2, the grid end of the first NMOS tube N1 is only slowly dragged down by the first pull-down current Ibiasn1 of normal soft handover, thus avoid and move this stage of VDD supply voltage at a high vpp voltage to export the follow-up drop-down stage much slow to cause the phenomenon of output linearity degree difference.

Claims

1. a driving circuit structure, it comprises pull-up current Ibiasp, described pull-up current Ibiasp one end connects voltage source V PP, the other end connects the drain terminal of PMOS P1, the grid end connection level translator other end of described PMOS P1 connects the grid end of the second NMOS tube N2, the output of inverter I1, the input of described inverter I1 is for driving input IN, the source of described second NMOS tube N2 connects first pull-down current Ibiasn1 one end, described first pull-down current Ibiasn1 other end ground connection, the drain terminal of described second NMOS tube N2 connects the source of described PMOS P1, electric capacity C1 one end, the grid end of the first NMOS tube N1, described electric capacity C1 other end ground connection, the drain terminal of described first NMOS tube N1 connects power vd D, source is drive output OUT, it is characterized in that, it also comprises control circuit, described control circuit comprises the 5th NMOS tube N5 that grid end is connected with source, the source of described 5th NMOS tube N5 connects the source of described PMOS P1, the drain terminal of described 5th NMOS tube N5 connects the drain terminal of the 3rd NMOS tube N3, the drain terminal of the 4th NMOS tube N4, the grid end of described 4th NMOS tube N4 is connected with source, the grid end of described 3rd NMOS tube connects the grid end of described second NMOS tube, source connects second pull-down current Ibiasn2 one end, described second pull-down current Ibiasn2 other end ground connection.