CN103490599A - Power tube subsection grid driving circuit - Google Patents

Abstract

The invention relates to an integrated circuit driver technique, in particular to a low EMI power tube subsection grid driving circuit. The power tube subsection grid driving circuit uses different speeds to charge and discharge a power tube grid. When the voltage of the power tube grid begins to change, the charging-discharging speed is slow to prevent large dv/dt and di/dt. When the voltage reaches a certain value, the power tube grid is charged and discharged quickly. Thus, the on-off speed of a power tube is high, and the purpose of restraining EMI in a switch power supply is achieved. The power tube subsection grid driving circuit has the advantages that the on-off of the power tube is high, and the purpose of restraining EMI in the switch power supply is achieved. The power tube subsection grid driving circuit is especially suitable for the field of power tube subsection grid driving circuits.

Description

A kind of power tube step grate drive circuit

Technical field

The present invention relates to the driver ic technology, relate to specifically a kind of low EMI power tube step grate drive circuit.

Background technology

Along with the day of the energy is becoming tight, how the energy is carried out reasonably utilizing and more and more having been put on schedule.The advantages such as Switching Power Supply is high with its efficiency, and hear rate is little are widely used.Along with market improving constantly requirements such as switch power supply output current and efficiency, the chip area that the integrated power pipe is shared and power tube grid capacitance also increase thereupon, in order to make the PWM change in voltage on the power tube grid more precipitous, before needing, stage drive circuit provides large charging and discharging electric current.

Classical actuator electrical route chain of inverters forms, as shown in Figure 1.Wherein, C _pfor power tube grid parasitic capacitance.For faster to C _pcapacitor charge and discharge, the driving force of reverser will be amplified step by step, thereby when upset occurs in control signal, certainly will produce larger dv/dt and di/dt at the power tube grid, the rate of change that wherein dv/dt is voltage in the unit interval, the rate of change that di/dt is electric current in the unit interval, make Switching Power Supply produce larger electromagnetic interference (Electro-Magnetic Interference, EMI) noise.

Summary of the invention

To be solved by this invention, be exactly for the problems referred to above, a kind of low EMI power tube step grate drive circuit is proposed, adopt different speed to be discharged and recharged the power tube grid voltage.

The present invention solves the problems of the technologies described above adopted technical scheme: a kind of power tube step grate drive circuit, it is characterized in that, comprise a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, a NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, capacitor C 1, resistance R 1, device IV1, the first reverser INV1 and the second reverser INV2 in the same way;

The source electrode of the source electrode of the source electrode of the source electrode of the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4 all meets power vd D;

The grid of the one PMOS pipe MP1 connects output and the input of device IV1 in the same way of grid, the first reverser INV1 of a NMOS pipe MN1, and the drain electrode of a PMOS pipe MP1 connects the drain electrode of a NMOS pipe MN1 and an end of resistance R 1;

The other end of resistance R 1 connects the drain electrode of the 3rd PMOS pipe MP3, the drain electrode of the 3rd NMOS pipe MN3, the grid of the 4th PMOS pipe MP4, the grid of the 5th NMOS pipe MN5 and the input of the first reverser INV1, and the drain electrode of the 4th PMOS pipe MP4 connects the source electrode of the 5th PMOS pipe MP5;

The grid of the 2nd PMOS pipe MP2 is connected the drain electrode of grid and the 2nd NMOS pipe MN2 of the 3rd PMOS pipe MP3 with drain electrode;

The grid of the 2nd NMOS pipe MN2 connects the first control signal CT1, and the grid of the 3rd NMOS pipe MN3 connects the second control signal CT2;

The output of device IV1 connects an end of capacitor C 1 and the input of the second reverser INV2 in the same way, and the output of the second reverser INV2 connects the grid of the 5th PMOS pipe MP5 and the grid of the 4th NMOS pipe MN4;

The drain electrode of the 4th NMOS pipe MN4 connects the drain electrode of the 5th PMOS pipe MP5 and the output DRIV that the 5th NMOS manages the drain electrode power pipe step grate drive circuit of MN5;

The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5 and the equal earthed voltage VSS of the other end of capacitor C 1.

The technical scheme that the present invention is total, by adopting different speed to be discharged and recharged the power tube grid voltage, when the power tube grid voltage starts to change, discharge and recharge speed slow, prevent large dv/dt and di/dt, voltage starts fast charging and discharging after reaching certain value, and so not only the switching speed of power tube is very fast, and can realize the purpose that EMI in Switching Power Supply is suppressed.

Concrete, described the first control signal CT1 and the second control signal CT2 are complementary overlapping narrow high level pulse signal.

Beneficial effect of the present invention is, by adopting different speed to be discharged and recharged the power tube grid, make the power tube grid when starting to change, the power tube grid is discharged and recharged to speed slower, prevent larger dv/dt and di/dt, and after grid voltage reaches certain value, start grid voltage is discharged and recharged fast, so not only the switching speed of power tube is very fast, and has realized the purpose that EMI in Switching Power Supply is suppressed.

The accompanying drawing explanation

Fig. 1 is conventional power tube drive circuit schematic diagram;

The circuit diagram that Fig. 2 is embodiment 1;

The circuit diagram that Fig. 3 is embodiment 2.

Embodiment

Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:

For convenient narration, hereinafter a PMOS manages MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10 is successively with MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, substitute a NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 7th NMOS pipe MN7, the 8th NMOS pipe MN8 is successively with MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 substitutes, the first control signal CT1 and the second control signal CT2 substitute with CT1 and CT2 respectively successively, the one NLDMOS pipe MNLD1 and the 2nd NLDMOS pipe MNLD2 substitute with MNLD1 and MNLD2 respectively successively, and device IV1 substitutes with IV1 in the same way, the first reverser INV1, the second reverser INV1, the 3rd reverser INV3 and the 4th reverser INV4 are successively with INV1, INV2, INV3 and INV4 substitute.

Embodiment 1:

As shown in Figure 2, this example is for being applied to low side power tube grid drive circuit, comprise 5 PMOS pipes: MP1, MP2, MP3, MP4, MP5,5 NMOS pipes: MN1, MN2, MN3, MN4, MN5, and capacitor C 1, resistance R 1, homophase device IV1 and inverter INV1, INV2.Concrete annexation is: the grid of MP1 connects grid and the input of homophase device IV1 and the output of inverter INV1 of MN1 pipe, and source electrode connects supply voltage V _dD, drain electrode connects the drain electrode of MN1 and an end of resistance R 1; The source electrode of MN1 connects earth potential VSS, and the other end of resistance R 1 connects the drain electrode of MP3, drain electrode and the grid of MP4, MN5 and the input of INV1 of MN3; The grid of MP3 connects the grid of MP2 and the drain electrode of drain electrode and MN2, and source electrode connects supply voltage V _dD, the source electrode of MP2 connects supply voltage V _dD; The grid connection control signal CT1 of MN2, source electrode connects earth potential VSS; The grid connection control signal CT2 of MN3, source electrode connects earth potential VSS; The output of homophase device IV1 connects an end of capacitor C 1 and the input of INV2, and the other end of C1 connects earth potential VSS, and the output of INV2 connects the grid of MP5, MN4; The source electrode of MP4 connects supply voltage V _dD, drain electrode connects the source electrode of MP5; The drain electrode of MP5 is connected as the output DRIV of power tube drive circuit with the drain electrode of MN4, MN5, and the source electrode of MN4, MN5 all connects earth potential VSS.

In this example, control signal CT1 and CT2 are complementary overlapping narrow high level pulse signal, for power ratio control pipe grid drive circuit, the power tube grid are charged or discharge.

This routine operation principle is:

Grid end electric discharge operation principle: when the CT1 end has a narrow high level signal, transistor MN2 and MP2 are at V _dDand form a path between ground VSS, and the electric current produced in MP2 makes the MP3 pipe open, and node A voltage can be drawn high to high voltage V _dD, cause transistor MN5 to open, thereby start the gate capacitance of low side power tube is discharged, because MN5 works in dark linear zone, so its conducting resistance R _mN5can be write as following form:

$R_{\mathrm{MN}5}=\frac{1}{{\mathrm{\μC}}_{\mathrm{OX}}{S}_{\mathrm{MN}5}(V_{\mathrm{DD}}-V_{\mathrm{TH}})}$

Wherein, S _mN5=(W/L) _mN5, V _tHfor the threshold voltage of NMOS pipe, the mobility that u is metal-oxide-semiconductor, Cox is grid oxygen unit-area capacitance, and therefore now the time constant of electric discharge is:

${\mathrm{\τ}}_1=R_{\mathrm{MN}5}{C}_P=\frac{C_P}{{\mathrm{\μC}}_{\mathrm{OX}}{S}_{\mathrm{MN}5}(V_{\mathrm{DD}}-V_{\mathrm{TH}})}$

Wherein, C _pequivalent gate capacitance for the low side power tube.And, for node B, due to the existence of capacitor C 1, make the B point voltage slowly rise to high level V _dD, transistor MN4 pipe is opened, thereby further the gate capacitance of high-end power tube is discharged, now output is resistance R to the equivalent resistance on ground _mN5and resistance R _mN4parallel connection:

$R_{\mathrm{MN}5}//R_{\mathrm{MN}5}=\frac{1}{(S_{\mathrm{MN}4}+S_{\mathrm{MN}5}){\mathrm{\μC}}_{\mathrm{OX}}(V_{\mathrm{DD}}-V_{\mathrm{TH}})}$

Wherein, S _mN4=(W/L) _mN4, therefore now time constant is:

${\mathrm{\τ}}_2=(R_{\mathrm{MN}5}//R_{\mathrm{MN}5})C_P=\frac{C_P}{(S_{\mathrm{MN}4}+S_{\mathrm{MN}5}){\mathrm{\μC}}_{\mathrm{OX}}(V_{\mathrm{DD}}-V_{\mathrm{TH}})}$

Can find out after MN4 opens, the time constant of power tube gate capacitance electric discharge reduces, and therefore can to the power tube grid, be discharged faster.Thereby realized the effect that step grate drives, at first allowed the grid slower electric discharge of power tube, prevented large dv/dt; Then when gate voltage is low, by speed faster, discharged.By this method, realized suppressing the purpose of switch power supply power tube grid EMI.Transistor MP1, MN1 and INV1 form latch, and after the upset of A point voltage is for high level, inverter INV1 will export the grid of a low level to MP1 and MN1, make the A point voltage keep high level.Because 1 both end voltage of resistance R in the process of latching is poor larger, so add resistance R 1 can be used for limiting the electric current of MP1 and MN1 pipe.

The charging operation principle: same mode, when CT2 end has a narrow high level pulse signal, transistor MN3 opens, and node A is pulled down to electronegative potential, and MN5 manages shutoff.Due to the existence of capacitor C 1, cause the current potential of node B to taper to high potential V equally _dD, in this process, MP5 opens gradually, and MN4 turn-offs gradually, and after capacitor C 1 has been charged, transistor MN4 turn-offs, and MP5 opens fully.Therefore, low side power tube opening process is a fragmentation procedure equally.In the incipient stage, the power tube grid is charged slowly, then, after grid voltage reaches certain value, start the power tube grid is charged fast, realized that equally the step grate of power tube drives, reach the purpose that suppresses switch power supply power tube grid EMI.

Embodiment 2:

This example is for being applied to the gate driver circuit of high-end power, as shown in Figure 3, comprise MP6, MP7, MP8, MP9, MP10, MN6, MNLD1, MNLD2, MN7, MN8, and capacitor C 2, resistance R 2, homophase device IV2 and inverter INV3, INV4, bipolarity triode Q1, Q2 and Q3.Concrete annexation is: the source electrode of MP6, the source electrode of MP7, the source electrode of MP8 and the source electrode of MP9 meet bootstrap voltage mode Boost, the grid of MP6 connects the grid of MN6, the output of INV3 and the input of IV2, the drain electrode of MP6 connects the end of R2 and the drain electrode of MN6, the other end of R2 connects the emitter of Q1, the drain electrode of MP8, the collector electrode of Q3, the drain electrode of MNLD2, the input of INV3, the grid of MP9 and the grid of MN8, the grid of MP7 is connected the grid of MP8 with drain electrode, the emitter of Q2 and the drain electrode of MNLD1, the output of IV2 connects the end of C2 and the input of INV4, the input of INV4 connects the grid of MP10 and the grid of MN7, the drain electrode of MP10 connects the drain electrode of MN7 and output DRIV_H is in the drain electrode of MN8, the source electrode of MN6, the source electrode of MN7, the source electrode of MN8 and the base stage of Q1 and collector electrode, the base stage of Q2 and collector electrode, the base stage of Q3 and emitter meet switching voltage SW.

Specific works principle and embodiment 1 are similar, and just power rail is different, is no longer constant V _dDwith VSS voltage, but unsteady bootstrap voltage mode Boost and SW voltage.Main difference is adding of BJT transistor Q1, Q2, Q3 and NLDMOS pipe MNLD1, MNLD2, and the main purpose of Q2 is that restriction C point voltage can be lower than SW-V _bEQ2, prevent from puncturing the grid end of MP7, MP8 pipe; The main purpose of Q1, Q3 is that restriction D point voltage is not less than SW-V _bEQ1thereby in protection MP6 and MN6 and INV3, metal-oxide-semiconductor is not damaged; Be floating voltage due to C point and D point voltage in addition, need to use the NLDMOS pipe withstand voltage as control valve, prevent the damage of device.

Claims (2)

1. a power tube step grate drive circuit, it is characterized in that, comprise a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, a NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, capacitor C 1, resistance R 1, device IV1, the first reverser INV1 and the second reverser INV2 in the same way;

The source electrode of the source electrode of the source electrode of the source electrode of the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4 all meets power vd D;

The grid of the one PMOS pipe MP1 connects output and the input of device IV1 in the same way of grid, the first reverser INV1 of a NMOS pipe MN1, and the drain electrode of a PMOS pipe MP1 connects the drain electrode of a NMOS pipe MN1 and an end of resistance R 1;

The other end of resistance R 1 connects the drain electrode of the 3rd PMOS pipe MP3, the drain electrode of the 3rd NMOS pipe MN3, the grid of the 4th PMOS pipe MP4, the grid of the 5th NMOS pipe MN5 and the input of the first reverser INV1, and the drain electrode of the 4th PMOS pipe MP4 connects the source electrode of the 5th PMOS pipe MP5;

The grid of the 2nd PMOS pipe MP2 is connected the drain electrode of grid and the 2nd NMOS pipe MN2 of the 3rd PMOS pipe MP3 with drain electrode;

The grid of the 2nd NMOS pipe MN2 connects the first control signal CT1, and the grid of the 3rd NMOS pipe MN3 connects the second control signal CT2;

The output of device IV1 connects an end of capacitor C 1 and the input of the second reverser INV2 in the same way, and the output of the second reverser INV2 connects the grid of the 5th PMOS pipe MP5 and the grid of the 4th NMOS pipe MN4;

The drain electrode of the 4th NMOS pipe MN4 connects the drain electrode of the 5th PMOS pipe MP5 and the output DRIV that the 5th NMOS manages the drain electrode power pipe step grate drive circuit of MN5;

The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5 and the equal earthed voltage VSS of the other end of capacitor C 1.

2. a kind of power tube step grate drive circuit according to claim 1, is characterized in that, described the first control signal CT1 and the second control signal CT2 are complementary overlapping narrow high level pulse signal.

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