CN105141113A - Driver circuit for IGBT driver chip - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits, and specifically relates to a driver circuit for an IGBT driver chip. According to the driver circuit which is mainly based on the conventional circuit, grid stray capacitance is relatively high having several thousands of PF or even over ten thousands of PF according to characteristics of high threshold voltage of IGBT, so that higher current is required for charging; the driver circuit for the IGBT driver chip can ensure that the IGBT grid voltage can be rapidly charged to the threshold voltage point, and can ensure that higher dVge/dt and dic/dt are not generated by the IGBT within the time of t1 to t3 as well, so that the reliability of the IGBT can be effectively ensured, and the starting speed of the IGBT is accelerated as well; and therefore, overhigh dVge/dt and dic/dt can be effectively prevented according to the characteristics of the IGBT to prevent the power-on peak current and the turned-off peak voltage from being overhigh.

Description

A kind of drive circuit for IGBT driving chip

Technical field

The invention belongs to electronic circuit technology field, relate to a kind of drive circuit for IGBT driving chip specifically.

Background technology

IGBT grid drive integrated circult is one of typical circuit of HVIC (high voltage integrated circuit), and due to its high reliability, area is little, and effect high is widely used in the aspect such as household electrical appliance and industrial equipment, Aeronautics and Astronautics, armament systems.A pith of HVIC is the driving to IGBT, but irrational driving can produce high dv/dt and di/dt, and high dv/dt, di/dt switch drive IGBT is the most dangerous switchtype.Reasonably can reach a better effect in conjunction with the self character of IGBT device simultaneously.So how to design according to IGBT device self character the popular domain that a rational drive circuit becomes current IGBT drive circuit.

A kind of more traditional IGBT drive circuit is as Fig. 1, comprise two IGBT device Q1 and Q2, two sustained diode 1 and D2, two-way drive chain realizes the driving to IGBT, this circuit can realize the function driving IGBT substantially, but this circuit is not in conjunction with the self character of IGBT device, rational design driven circuit, relatively high dv/dt, di/dt may be caused, the reliability of IGBT can be affected.

Summary of the invention

To be solved by this invention, be exactly for existing IGBT drive circuit Problems existing, propose a kind of drive circuit for IGBT driving chip.

For achieving the above object, the present invention adopts following technical scheme:

A kind of drive circuit for IGBT driving chip, as shown in Figure 2, wherein-HV is negative ultra high voltage power supply, PGND is Power Groud, comprise a PLDMOS pipe P1, 2nd PLDMOS pipe P2, 3rd PLDMOS pipe P3, 4th PLDMOS pipe P4, first PMOS MP1, second PMOS MP2, first NMOS tube MN1, second NMOS tube MN2, first resistance R1, second resistance R2, 3rd resistance R3, 4th resistance R4, 5th resistance R5, 6th resistance R6, 7th resistance R7, 8th resistance R8, first grid resistance resistance Rg1, second grid resistance resistance Rg2, 3rd grid resistance resistance Rg3, 4th grid resistance resistance Rg4, one IGBT pipe Q1, 2nd IGBT pipe Q2, electric capacity C, first diode D1, second diode D2, first Zener diode Z1 and the second Zener diode Z2, the source electrode of the 4th PLDMOS pipe P4 is by connecing power supply after the 8th resistance R8, and its grid meets the first control signal A1, and its drain electrode connects the drain electrode of the first NMOS tube MN1, the tie point of the 4th PLDMOS pipe P4 and the 8th resistance R8 connects the drain electrode of the second PMOS MP2, the grid of the second PMOS MP2 meets the 3rd control signal A3, and its source electrode connects power supply, the grid of the 3rd PLDMOS pipe P3 meets the second control signal A2, its source electrode by connecing power supply after the 7th resistance R7, grid by meeting the first NMOS tube MN1 after the first grid resistance resistance Rg1 of its drain electrode, the grid of the 2nd PLDMOS pipe P2 meets the 4th control signal B1, and its source electrode is by connecing power supply after the 6th resistance R6, and its drain electrode is by meeting-HV after the 3rd resistance R3, the source electrode of the 2nd PLDMOS pipe P2 and the tie point of the 6th resistance R6 connect the drain electrode of the first PMOS MP1, the grid of the first PMOS MP1 meets the 6th control signal B3, and its source electrode connects power supply, the source electrode of the one PLDMOS pipe P1 is by connecing power supply after the 5th resistance R5, and its grid meets the 5th control signal B2, and its drain electrode connects the N pole of the second Zener diode Z2, the P of the second Zener diode Z2 is long-pending meets-HV, second Zener diode Z2 is in parallel with the 4th resistance R4, the tie point of the second Zener diode Z2 and the 4th resistance R4 is by connecing the drain electrode of the second NMOS tube MN2 after the 4th grid resistance resistance Rg4, the grid of the second NMOS tube MN2 connects the tie point of the 2nd PLDMOS pipe P2 drain electrode and the 3rd resistance R3, and its source electrode meets-HV, the drain electrode of the second NMOS tube MN2 is by connecing the base stage of the 2nd IGBT pipe Q2 after the 3rd grid resistance resistance Rg3, the collector electrode of the 2nd IGBT pipe Q2 connects the negative pole of the second diode D2, and its emitter meets-HV, positive pole-the HV of the second diode D2, second resistance R2 is in parallel with electric capacity C, and the tie point of its one end connects the drain electrode of the 3rd PLDMOS pipe P3 and the N pole of the first Zener diode Z1, and its other end tie point connects the P pole of the first Zener diode Z1, the drain electrode of the 4th PLDMOS pipe P4 is by connecing the source electrode of the first NMOS tube MN1 after the first resistance R1, the drain electrode of the 4th PLDMOS pipe P4 is by connecing the base stage of an IGBT pipe Q1 after the second grid resistance resistance Rg2, the collector electrode of the one IGBT pipe Q1 meets PGND, and its emitter connects the positive pole of the first diode D1, the negative pole of the first diode D1 meets PGND, the P of the first Zener diode Z1 amasss, the emitter of the negative pole of the positive pole of the first diode D1, the second diode D2, an IGBT pipe Q1, and the tie point of the collector electrode of the 2nd IGBT pipe Q2, the source electrode of the first NMOS tube MN1 and the second resistance R2 and electric capacity C is output.

Beneficial effect of the present invention is, can effectively can effectively prevent di/dt and dV/dt excessive according to the characteristic of of IGBT itself, prevent the peak current opened, the crest voltage of shutoff be excessive, can reduce switching time to a certain extent simultaneously.

Accompanying drawing explanation

Fig. 1 is the schematic diagram that conventional I GBT drives;

Fig. 2 is systematic schematic diagram of the present invention;

Fig. 3 is system equivalent schematic diagram of the present invention;

Fig. 4 is the switching characteristic figure of IGBT;

Fig. 5 is that Q1 of the present invention closes, the equivalent schematic diagram that Q2 opens;

Fig. 6 is that Q1 of the present invention opens, the equivalent schematic diagram that Q2 closes.

Embodiment

The present invention is a kind of drive circuit for IGBT driving chip, as shown in Figure 2, wherein-HV is negative ultra high voltage power supply, PGND is Power Groud, comprise a PLDMOS pipe P1, 2nd PLDMOS pipe P2, 3rd PLDMOS pipe P3, 4th PLDMOS pipe P4, first PMOS MP1, second PMOS MP2, first NMOS tube MN1, second NMOS tube MN2, first resistance R1, second resistance R2, 3rd resistance R3, 4th resistance R4, 5th resistance R5, 6th resistance R6, 7th resistance R7, 8th resistance R8, first grid resistance resistance Rg1, second grid resistance resistance Rg2, 3rd grid resistance resistance Rg3, 4th grid resistance resistance Rg4, one IGBT pipe Q1, 2nd IGBT pipe Q2, electric capacity C, first diode D1, second diode D2, first Zener diode Z1 and the second Zener diode Z2, the source electrode of the 4th PLDMOS pipe P4 is by connecing power supply after the 8th resistance R8, and its grid meets the first control signal A1, and its drain electrode connects the drain electrode of the first NMOS tube MN1, the tie point of the 4th PLDMOS pipe P4 and the 8th resistance R8 connects the drain electrode of the second PMOS MP2, the grid of the second PMOS MP2 meets the 3rd control signal A3, and its source electrode connects power supply, the grid of the 3rd PLDMOS pipe P3 meets the second control signal A2, its source electrode by connecing power supply after the 7th resistance R7, grid by meeting the first NMOS tube MN1 after the first grid resistance resistance Rg1 of its drain electrode, the grid of the 2nd PLDMOS pipe P2 meets the 4th control signal B1, and its source electrode is by connecing power supply after the 6th resistance R6, and its drain electrode is by meeting-HV after the 3rd resistance R3, the source electrode of the 2nd PLDMOS pipe P2 and the tie point of the 6th resistance R6 connect the drain electrode of the first PMOS MP1, the grid of the first PMOS MP1 meets the 6th control signal B3, and its source electrode connects power supply, the source electrode of the one PLDMOS pipe P1 is by connecing power supply after the 5th resistance R5, and its grid meets the 5th control signal B2, and its drain electrode connects the N pole of the second Zener diode Z2, the P of the second Zener diode Z2 is long-pending meets-HV, second Zener diode Z2 is in parallel with the 4th resistance R4, the tie point of the second Zener diode Z2 and the 4th resistance R4 is by connecing the drain electrode of the second NMOS tube MN2 after the 4th grid resistance resistance Rg4, the grid of the second NMOS tube MN2 connects the tie point of the 2nd PLDMOS pipe P2 drain electrode and the 3rd resistance R3, and its source electrode meets-HV, the drain electrode of the second NMOS tube MN2 is by connecing the base stage of the 2nd IGBT pipe Q2 after the 3rd grid resistance resistance Rg3, the collector electrode of the 2nd IGBT pipe Q2 connects the negative pole of the second diode D2, and its emitter meets-HV, positive pole-the HV of the second diode D2, second resistance R2 is in parallel with electric capacity C, and the tie point of its one end connects the drain electrode of the 3rd PLDMOS pipe P3 and the N pole of the first Zener diode Z1, and its other end tie point connects the P pole of the first Zener diode Z1, the drain electrode of the 4th PLDMOS pipe P4 is by connecing the source electrode of the first NMOS tube MN1 after the first resistance R1, the drain electrode of the 4th PLDMOS pipe P4 is by connecing the base stage of an IGBT pipe Q1 after the second grid resistance resistance Rg2, the collector electrode of the one IGBT pipe Q1 meets PGND, and its emitter connects the positive pole of the first diode D1, the negative pole of the first diode D1 meets PGND, the negative pole of the P pole of the first Zener diode Z1, the positive pole of the first diode D1, the second diode D2, the emitter of an IGBT pipe Q1, the tie point of the collector electrode of the 2nd IGBT pipe Q2, the source electrode of the first NMOS tube MN1 and the second resistance R2 and electric capacity C is output.

Operation principle of the present invention is:

From switching characteristic Fig. 3 of IGBT, wherein t0 to t4 is the opening process of IGBT, and T0 to T4 is the turn off process of IGBT, and from then on the operation principle of figure and IGBT is known, within t1 to the t3 time period, before namely Miller platform terminates.In particularly t1 to t2 stage wherein, obtained by KCL, KVL equation:

$V_{\lg }+R_g{C}_g\frac{{\mathrm{dV}}_{ge}}{dt}+V_{ge}+V_{Le}=V_{cc}$

$V_{GE\left(th\right)}+\frac{i_C}{g_m}=V_{ge}$

Wherein Rg is resistance, and Cg is parasitic gate electric capacity, and Lg is parasitic gate inductance, and Le is the stray inductance of the emitter of IGBT, and gm is the mutual conductance of IGBT, V _{gE (th)}for the threshold voltage of IGBT.Can be obtained by two formulas above:

$\frac{{\mathrm{di}}_c}{dt}=g_m\frac{{\mathrm{dV}}_{ge}}{dt}$

$\frac{{\mathrm{di}}_c}{dt}=\frac{V_{cc}-V_{ge}}{R_g{C}_g/g_m}$

From two formulas above, resistance and charging current larger, the grid potential change of IGBT faster, grid by dic/dt larger for generation, the unlatching peak current of generation is larger, will affect the normal work of IGBT so significantly.

In the present invention, the equivalent schematic diagram of whole system is as 4, and when the grid potential A1 of P4 is high level, the grid potential A2 of P3 is low level, and the grid potential B1 of P2 is low level, and when the grid potential B1 of P1 is high level, Q1 now closes, and Q2 opens.Equivalent circuit diagram now as shown in Figure 5.

The IGBT pipe Q2 conducting of downside, MP2 open stage, the charging current of IGBT changes, namely Q2 opens the starting stage, before the grid voltage of IGBT is not charged to threshold voltage, corresponding t0 to the t1 time period, its charging current forms by two strands, one opens produced electric current I mp1 by MP1, and MP1 is now in linear zone.

$I_{mp1}=\frac{1}{2}{u}_{p\_mp1}{c}_{ox\_mp1}\frac{W_{mp1}}{L_{mp1}}(V_{cc}-V_{th\_mp1})V_{ds\_mp1}$

Wherein μ p_mp1 represents the mobility of PMOS, and COX_mp1 is gate oxide unit-area capacitance, represent the breadth length ratio of MP1, Vds_mp1 represents the drain-source voltage of MP1, and Vth_mp1 represents the threshold voltage of MP1; Be generally the Ip2 produced by P2, P2 is now in saturation region.

$I_{p2}=\frac{1}{2}{u}_n{c}_{ox}\frac{W}{L}{(V_{cc}-V_{th\_p2}-V_{R6})}^2$

After the grid potential of IGBT reaches threshold voltage, MP1 closes, and namely after the t1 time, only has P2 constant current to the gate charges of IGBT, and the gate charging current of IGBT reduces.As shown in Figure 4, the width of the burst pulse in sequential chart is exactly the time span of t0 to t1 to its sequential chart.

Because the effect of resistance R3 and R6 effectively can limit the grid voltage of IGBT after final stablizing, because the electric current on R3 and R6 is equal, the electric current simultaneously on R6 is determined by P2 and R6, and the current-voltage correlation now on R6 is as follows:

$I_{mp2}=\frac{V_{R6}}{R6}$

Final stabling current size so on R3 is:

$I_{p2}=\frac{B+\sqrt{B^2-4R_6^2{(VCC-V_{th\_p2})}^2}}{2R_6^2}$

$B=2(VCC-V_{th\_p2})R_6+\frac{2}{u_{p\_p2}{c}_{ox\_p2}W/L}$

Wherein μ p_p2 represents the mobility of P2 pipe, and COX_P2 is gate oxide unit-area capacitance, represent the breadth length ratio of P2, Vth_p2 represents the threshold voltage of P2; Final stabling current size so on R3 is:

V _R3＝I _p2×R3

Can be operated in a suitable stationary value after can ensureing the grid potential t4 time point of IGBT like this, this voltage both can ensure that IGBT can be operated in linear zone after the t4 time, and the grid of IGBT also can not be caused breakdown.Simultaneously also ensure that PLDMOS is operated in saturation region, because a termination of R3 bears ultra high voltage, and pressure reduction on R3 is very little.

Characteristic according to IGBT is known, the threshold voltage of IGBT is larger, general at more than 5V, parasitic gate electric capacity is comparatively large, generally has several thousand PF PF even up to ten thousand, larger current is needed to charge, the present invention can ensure that IGBT grid voltage is charged to threshold voltage point fast, but can ensure that IGBT charging current within t1 to the t3 time period is not too large simultaneously, reduces dVge/dt and dic/dt of IGBT, effectively can ensure the reliability of IGBT like this, accelerate the opening speed of IGBT simultaneously.

Simultaneously grid connects and has been connected in series a resistance, known by above-mentioned analysis, and this resistance also can effective suppressor grid charging rate, and reduce dVge/dt and dic/dt, while can prevent from vibrating caused by the parasitic gate inductance of IGBT.Gate current i (t) can be obtained by the differential equation of the second-order circuit of RLC:

$L_g\×\frac{d^{2}i\left(t\right)}{{\mathrm{dt}}^2}+R_g\×\frac{di\left(t\right)}{dt}+\frac{i\left(t\right)}{Cg}=0$

Lg is parasitic gate inductance, and Rg is resistance, and Cg is parasitic gate electric capacity, in order to not cause vibration, then and second-order circuit underdamping work, release:

$R_g\≥2\sqrt{\frac{L_g}{Cg}}$

Can not lower than this value so resistance is minimum, simultaneously in order to ensure that the opening speed of IGBT can not be excessively slow, resistance Rg can not be excessive, and it's the opening time that senior general affects IGBT greatly pasts Rg.

Known by the analysis of the turn-off characteristic of IGBT, particularly in T1 to the T3 time, the closing velocity of IGBT is faster, and the closedown crest voltage that Q1 produces is larger, and with regard to likely causing, the VCE of IGBT is too high to be punctured like this.Have KCL, KVL equation obtains:

$C_{GC}\×\frac{{\mathrm{dV}}_{CE}}{dt}-C_{GC}\×\frac{{\mathrm{dV}}_{GE}}{dt}-C_{GE}\×\frac{{\mathrm{dV}}_{GE}}{dt}-i_G=0$

$V_{GE}-i_G{R}_G-L_G\frac{{\mathrm{di}}_G}{dt}-i_G{R}_{DS\left(on\right)}=0$

Wherein C _gCfor the grid of IGBT and the parasitic capacitance of inter-collector, C _gEfor parasitic capacitance between the grid of IGBT and emitter, L _gfor gate series stray inductance, R _{dS (on)}for MN1 conducting resistance, i _gfor the size of gate charging current.From above-mentioned two computing formula, the charging current that can obtain grid is larger, and the dVge/dt of generation is larger, and it is faster that grid voltage changes, and the dVce/dt of generation is larger.

In the process that the IGBT pipe Q1 of the present invention in high side closes, P3 opens, the opening speed of the effect restriction MN1 of R2 and C, the resistance of MN1 also effectively can slow down the opening speed of MN1 simultaneously, the size of the gate pull down current of effective reduction Q1 within T1 to the T3 time, the effect of zener diode is the grid peak position of restriction MN1, and namely limit the size of Q1 gate discharge current, its maximum Imax is:

$I_{max}=\frac{1}{2}{u}_{n\_mn1}{c}_{ox\_mn1}\frac{W_{mn1}}{L_{mn1}}(V_{zener}-V_{th\_MN1})2$

Wherein Vzener is the burning voltage at Zener diode two ends, and μ p_mn1 represents the mobility of NMOS tube MN1, and COX_mn1 is gate oxide unit-area capacitance, represent the breadth length ratio of MP1, Vth_MN1 is the threshold voltage of MN1.In like manner the resistance of Q1 is also the velocity of discharge reducing Q1.

According to the switching characteristic figure of IGBT, IGBT after entering the T3 time, the grid voltage of IGBT starts to reduce from threshold voltage point.In the present invention, after IGBT enters the T3 time, when namely the grid voltage of IGBT reaches Vth point, due to the characteristic of the large threshold voltage of IGBT, and now the grid voltage of MN1 is maximum, and MN1 is now in saturation region, discharging current is maximum, effectively can accelerate the shutoff of IGBT like this.

When the grid potential A1 of P4 is low level, the grid potential A2 of P3 is high level, and the grid potential B1 of P2 is high level, and when the grid potential B1 of P1 is low level, Q1 now opens, and Q2 closes.As shown in Figure 6, its operation principle substantially as above for equivalent circuit diagram now.

By above analysis, can find out that the present invention can effectively can effectively prevent di/dt and dV/dt excessive according to the characteristic of of IGBT itself, prevent the peak current opened, the crest voltage of shutoff is excessive.

Claims (1)

1. the drive circuit for IGBT driving chip, comprise a PLDMOS pipe P1, 2nd PLDMOS pipe P2, 3rd PLDMOS pipe P3, first PMOS MP1, second PMOS MP2, first NMOS tube MN1, second NMOS tube MN2, first resistance R1, second resistance R2, 3rd resistance R3, 4th resistance R4, 5th resistance R5, 6th resistance R6, 7th resistance R7, 8th resistance R8, first grid resistance resistance Rg1, second grid resistance resistance Rg2, 3rd grid resistance resistance Rg3, 4th grid resistance resistance Rg4, one IGBT pipe Q1, 2nd IGBT pipe Q2, electric capacity C, first diode D1, second diode D2, first Zener diode Z1 and the second Zener diode Z2, the source electrode of the 4th PLDMOS pipe P4 is by connecing power supply after the 8th resistance R8, and its grid connects the first control signal, and its drain electrode connects the drain electrode of the first NMOS tube MN1, the tie point of the one PLDMOS pipe P4 and the 8th resistance R8 connects the drain electrode of the second PMOS MP2, the grid of the second PMOS MP2 connects the 3rd control signal, and its source electrode connects power supply, the grid of the 3rd PLDMOS pipe P3 connects the second control signal, its source electrode by connecing power supply after the 7th resistance R7, grid by meeting the first NMOS tube MN1 after the first grid resistance resistance Rg1 of its drain electrode, the grid of the 2nd PLDMOS pipe P2 connects the 4th control signal, and its source electrode is by connecing power supply after the 6th resistance R6, and its drain electrode is by connecing negative ultra high voltage power supply after the 3rd resistance R3, the source electrode of the 2nd PLDMOS pipe P2 and the tie point of the 6th resistance R6 connect the drain electrode of the first PMOS MP1, the grid of the first PMOS MP1 connects the 6th control signal, and its source electrode connects power supply, the source electrode of the one PLDMOS pipe P1 is by connecing power supply after the 5th resistance R5, and its grid connects the 5th control signal, and its drain electrode connects the N pole of the second Zener diode Z2, the P of the second Zener diode Z2 amasss and connects negative ultra high voltage power supply, second Zener diode Z2 is in parallel with the 4th resistance R4, the tie point of the second Zener diode Z2 and the 4th resistance R4 is by connecing the drain electrode of the second NMOS tube MN2 after the 4th grid resistance resistance Rg4, the grid of the second NMOS tube MN2 connects the tie point of the 2nd PLDMOS pipe P2 drain electrode and the 3rd resistance R3, and its source electrode connects negative ultra high voltage power supply, the drain electrode of the second NMOS tube MN2 is by connecing the base stage of the 2nd IGBT pipe Q2 after the 3rd grid resistance resistance Rg3, the collector electrode of the 2nd IGBT pipe Q2 connects the negative pole of the second diode D2, and its emitter connects negative ultra high voltage power supply, the positive pole of the second diode D2 connects negative ultra high voltage power supply, second resistance R2 is in parallel with electric capacity C, and the tie point of its one end connects the drain electrode of the 3rd PLDMOS pipe P3 and the N pole of the first Zener diode Z1, and its other end tie point connects the P pole of the first Zener diode Z1, the drain electrode of the 4th PLDMOS pipe P4 is by connecing the source electrode of the first NMOS tube MN1 after the first resistance R1, the drain electrode of the 4th PLDMOS pipe P4 is by connecing the base stage of an IGBT pipe Q1 after the second grid resistance resistance Rg2, the collector electrode of the one IGBT pipe Q1 connects Power Groud, and its emitter connects the positive pole of the first diode D1, the negative pole of the first diode D1 connects Power Groud, the P of the first Zener diode Z1 amasss, the emitter of the negative pole of the positive pole of the first diode D1, the second diode D2, an IGBT pipe Q1, and the tie point of the collector electrode of the 2nd IGBT pipe Q2, the source electrode of the first NMOS tube MN1 and the second resistance R2 and electric capacity C is output.