CN113541662B - Gate drive circuit based on switching transient characteristic optimization - Google Patents
Gate drive circuit based on switching transient characteristic optimization Download PDFInfo
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- 238000005457 optimization Methods 0.000 title claims abstract description 75
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- 239000003990 capacitor Substances 0.000 claims abstract description 17
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K2017/0803—Modifications for protecting switching circuit against overcurrent or overvoltage against radiation hardening
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
An adjustable gate driving circuit based on switching transient characteristic optimization comprises a turn-off characteristic optimization circuit, a turn-on characteristic optimization circuit, a reference circuit, an undervoltage protection circuit, a power-on reset circuit, an input stage Schmitt circuit SMT1, a comparator circuit COM1, AND gate circuits AND1 AND AND2, an inverter circuit INV1, NMOS transistors MN1 AND MN2; the invention optimizes the on and off processes of the external power device separately and realizes adjustability, and when the external power device is turned off, the external power device is turned off by controlling the driving voltage of the NMOS tube at the low side of the internal output stage, thereby realizing the control of the sectional current; and when the power tube is conducted, the grid driving current of the high-side NMOS tube is controlled, and the charging and discharging speed of the grid capacitor is further adjusted to conduct the external power tube. The invention can reduce current and voltage peak, improve electromagnetic interference characteristic, optimize switching characteristic, and protect safety of application system.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a gate driving circuit based on switching transient characteristic optimization.
Background
The power field effect transistor (MOSFET) is a unipolar voltage control device with majority carriers conductive, has the advantages of high switching speed, good high-frequency performance, high input impedance, low noise, low driving power and the like, and is more and more applied to devices such as a switching power supply, an alternating current variable frequency speed regulator, an inverter and the like.
The driving of the MOSFET plays a decisive role in its operation, and in order to obtain good performance, the power device needs a suitable driving circuit, and many researches on the gate driving circuit of the power device are conducted, mainly based on the consideration of the switching speed, the switching loss, the overshoot current, the overshoot voltage and the electromagnetic interference. A fast switching speed will produce higher current, voltage overshoot and EMI and a slow switching speed will produce longer on and off delays and higher switching losses. However, as the working frequency is continuously increased, the requirement on the driving speed becomes higher, and the high on-off speed inevitably causes obvious problems of voltage and current impact, waveform oscillation phenomenon, electromagnetic interference and the like, so that the safety and reliability of power system equipment are seriously affected, and the driving circuit needs to be optimized.
As shown in FIG. 1, the traditional driving circuit adopts a larger grid resistance Ron for driving the conduction of the power device S1, and adopts a lower grid resistance Roff for driving the disconnection of the power device S1, so that the compromise processing method is simpler and can not meet the situation with higher requirements on the switching characteristics; in the prior art, a grid driving circuit with adjustable grid resistance is specifically optimized by using a large grid resistance to inhibit reverse recovery current in the current rising stage of an external power tube S1, and using the large grid resistance to inhibit reverse recovery current in the drain-source of the external power tubeIn the voltage dropping stage, the dropping speed is controlled by using a small gate resistor, so that the switching-on loss is reduced; however, the method of changing the gate resistance is rough, the resistance is generally changed only once in a single switching process, and the on-off is difficult to optimize simultaneously. In the prior art, a control mode of adjusting the grid voltage based on the detection of the drain voltage is also available, the drain voltage of the external power tube S1 is detected and compared with the reference voltage, and the grid driving voltage is adjusted according to the comparison voltage result, so that the purposes of adjusting di/dt and dv/dt are achieved, but the drain detection circuit needs to use a high-voltage circuit, and meanwhile, the detection circuit is complex; there are also many di-based in the prior art C /dt、dv CE The dt closed-loop detection realizes a control mode of optimizing driving, but for closed-loop control, detection precision is difficult to control, and certain delay is necessarily present in feedback, however, the detection precision and the feedback delay have great influence on the performance of control, and circuit optimization is difficult.
Disclosure of Invention
The invention aims to solve the technical problem of providing a grid driving circuit which is reasonable in design, simple in structure, externally adjustable in driving current for on-off and easy to optimize the switching characteristic of a power device and is based on the optimization of the switching transient characteristic.
The technical problems to be solved by the invention are realized by the following technical proposal. The invention relates to a gate driving circuit based on switching transient characteristic optimization, which comprises a turn-off characteristic optimization circuit, a turn-on characteristic optimization circuit, a reference circuit, an undervoltage protection circuit, a power-on reset circuit, an input stage Schmitt circuit SMT1, a comparator circuit COM1, AND gate circuits AND1 AND AND2, an inverter circuit INV1, NMOS transistors MN1 AND MN2;
input signal V IN The input end of the input stage Schmidt circuit SMT1 is connected, and the output V of the input stage Schmidt circuit SMT1 IN1 An output signal V of the power-on reset circuit connected to one input terminal of the AND gate circuit AND1 POR And an output signal V of the undervoltage protection circuit UVLO Respectively connected to the other two input terminals of the AND gate circuit AND1, the input terminal of the inverter circuit INV1 AND the offOne input terminal of the characteristic optimizing circuit is interconnected with AND connected with the output signal V of the AND gate circuit AND1 L1 Connecting; output end V of inverter circuit INV1 H1 One input terminal connected to AND gate AND2 AND one input terminal of the conduction characteristic optimization circuit, output V of the reference circuit REF1 Another input terminal connected to the conduction characteristic optimization circuit; an output signal V of the conduction characteristic optimization circuit N2 Another output terminal V of the conduction characteristic optimization circuit connected to the gate of the NMOS transistor MN2 REF2 The source end of the NMOS tube MN2 is connected with the drain end of the MN1 to be used as an output signal V of the driving circuit OUT For driving an external power device; the drain of MN2 is connected to VCC, the source of MN1 is connected to GND, drive signal V OUT Is connected to the positive input of the comparator circuit COM1, the output signal V of the comparator circuit COM1 CT Connected to the other input of AND gate AND2, output signal V of AND gate AND2 HX Connected to the other input of the shutdown characteristic optimization circuit, the output signal V of the shutdown characteristic optimization circuit N1 Is connected to the gate of NMOS transistor MN 1.
The technical problem to be solved by the present invention can be further solved by the following technical scheme, and for the gate driving circuit based on the optimization of the transient characteristics of the switch, the turn-off characteristic optimization circuit includes: the linear voltage stabilizing circuit LDO, the gating circuit MUX1, the OR circuit OR1, the inverter INV2, the PMOS transistors MP 1-MP 5, the NMOS transistors MN 3-MN 7, and the resistors R1 and R2; the PMOS transistors MP 1-MP 4, the NMOS transistors MN 4-MN 6 and the resistor R1 form a bias circuit; lower tube driving signal V L1 Connected to the gate of NMOS transistor MN7 and one input of OR1, pulse signal V HX A control signal connected to the other input terminal of the OR circuit OR1, the input terminal of the inverter INV2, the gate circuit MUX 1; the output end of the inverter INV2 is connected with the grid electrode of the NMOS tube MN3, and the output signal V of the linear voltage stabilizing circuit LDO LDO And GND signals are connected to two input terminals of the gate circuit MUX1, respectively; output signal V of gating circuit MUX1 TN A gate connected to the NMOS transistor MN 4; the source of NMOS transistor MN4 and the drain of MN3 are connected to a resistorOne end of R1, the other end of the resistor R1, and source stages of NMOS transistors MN3, MN5 and MN7 are connected to GND; the source stages of the PMOS pipes MP1, MP3 and MP5 are connected to VCC, and the grid electrode and the drain stage of the PMOS pipe MP1, and the grid electrode of the PMOS pipe MP3 and the source electrode of the MP2 are connected together; the grid electrode and the drain electrode of MP2 and the grid electrode of MP4 are connected to the drain electrode of NMOS tube MN 4; the drain electrode of the PMOS tube MP3 is connected to the source electrode of the PMOS tube MP 4; the drain of the PMOS tube MP4 and the drain of the NMOS tube MN5 are connected to the drain of the NMOS tube MN 6; output signal V of OR1 LT The grid electrode is connected to the grid electrode of the NMOS tube MN6 and the grid electrode of the PMOS tube MP 5; the source electrode of the NMOS tube MN6, the grid electrode of the MN5 and the drain electrode of the PMOS tube MP5 are connected to one end of a resistor R2, the other end of the resistor R2 is connected to the drain electrode of the NMOS tube MN7, and the output signal V is used as an output signal V of the turn-off characteristic optimization circuit N1 。
The technical problem to be solved by the invention can be further solved by the following technical scheme, and for the gate driving circuit based on the switching transient characteristic optimization, the switching-off characteristic optimization circuit comprises: when V is L1 When the voltage level is changed to a low level, the driving circuit starts to turn off, and the MUX1 circuit and the biasing circuit are controlled by the narrow pulse signal to enable V N1 Outputting a low-voltage narrow pulse driving signal for driving the NMOS tube MN1 to be conducted, and driving an external power device to be turned off by using a lower current, wherein the amplitude of the low-voltage pulse is recorded as V LV1 ，V LV1 A threshold voltage higher than MN1, less than VCC, V after a narrow pulse signal LT Becomes low level, at this time, the bias circuit is turned off to output, V N1 The voltage is raised to VCC voltage by the PMOS tube MP5, and the external power device is driven by a higher current to be turned off rapidly.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and for the gate driving circuit based on the switching transient characteristic optimization, the switching-off characteristic optimization circuit comprises: v (V) LV1 Can be adjusted by changing the size of the resistor R1, thereby adjusting V HX The magnitude of the off-current within the pulse width; the resistor can be adjusted off-chip to adapt to different power devices, and can also be used for driving specific power devices on-chip.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and for the gate driving circuit based on the switching transient characteristic optimization, the switching-off characteristic optimization circuit comprises: v (V) L1 Is the driving signal of the down tube MN2, V HX Is output V OUT Higher than V after shut-off REF2 Is a narrow pulse signal of V LT The driving signal is at V L1 The pulse width is increased by V HX A narrow pulse width; the turn-off characteristic optimizing circuit utilizes V HX The narrow pulse width realizes the sectional control of the turn-off driving current of the external power device, thereby reducing the overshoot voltage and the EMI at the turn-off time.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and for the gate driving circuit based on the switching transient characteristic optimization, the conducting characteristic optimization circuit comprises: operational amplifier OP1, PMOS tubes MP 6-MP 15, NMOS tubes MN 8-MN 14, resistors R3, R4, R5 and a capacitor C1; the PMOS transistors MP 6-MP 9, NMOS transistor MN8, resistors R3 and R4 form a bias circuit 1, the PMOS transistors MP 10-MP 13 and NMOS transistors MN 10-MN 13 form a bias circuit 2, and the source electrode of the PMOS transistor MP6, the source electrode of MP8, the source electrode of MP10, the source electrode of MP12 and the source electrode of MP14 are connected to VCC; one end of the resistor R3, one end of the resistor R4, one end of the source of the NMOS tube MN9, one end of the source of the MN11, one end of the source of the MN12, one end of the source of the MN14 and one end of the capacitor C1 are connected to GND; reference voltage V REF1 The positive input end of the operational amplifier OP1 is connected, the source electrode of the NMOS tube MN8 and the other end of the resistor R3 are connected to the negative input end of the operational amplifier OP1, and the grid electrode and the drain electrode of the PMOS tube MP6 are connected with the source electrode of the MP7, the grid electrode of the MP8 and the grid electrode of the MP 10; the grid and the drain of the PMOS tube MP7 are connected with the grid of the MP9, the grid of the MP11 and the drain of the NMOS tube MN8, the drain of the PMOS tube MP8 is connected with the source of the MP9, and the drain of the PMOS tube MP9 and the other end V of the resistor R4 REF2 Connected together as an output signal of the conduction characteristic optimization circuit; the drain of the PMOS tube MP10 is connected with the source of MP11, the drain of the PMOS tube MP11 is connected with the drain and the grid of the NMOS tube MN10, the grid of the MN13 and the drain of the MN9, and the source of the NMOS tube MN10, the drain of the MN11, the grid of the MN11 and the drain of the NMOS tube MN9The grid of MN12 is connected, the drain of NMOS tube MN12 is connected with the source of MN13, the drain of NMOS tube MN13 is connected with grid and drain of PMOS tube MP13 and grid of MP15, the source of PMOS tube MP13 is connected with grid and drain of MP12 and grid of MP14, the drain of PMOS tube MP14 is connected with the source of MP15, the drain of PMOS tube MP15 is connected with one end of resistor R5 and drain of NMOS tube MN14 together as output driving signal V of conduction characteristic optimizing circuit N2 The other end of the resistor R5 is connected with the other end of the capacitor C1 and is used for feeding a driving signal V H1 Is connected to the gates of NMOS transistors MN9 and MN 14.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and for the gate driving circuit based on the switching transient characteristic optimization, the conducting characteristic optimization circuit comprises: v (V) REF1 Is the reference voltage inside the chip, V H1 Is the driving signal of the upper tube MN2 inside the chip, which is formed by the input signal V IN Signal of logical inversion, reference voltage V REF1 And resistor R3 sets an initial bias current, and the bias circuits 1 and2 amplify the current according to a certain ratio, thereby adjusting the output signal V N2 V of the current driving capability of (1) H1 Control the turn-on and turn-off of the bias circuit 2, and then control the turn-on and turn-off of the upper NMOS transistor MN2, when V H1 When high, the bias circuit 2 is turned off, and the output V of the characteristic optimizing circuit is turned on N2 The signal is low and the upper tube NMOS tube MN2 is turned off.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and for the gate driving circuit based on the switching transient characteristic optimization, the conducting characteristic optimization circuit comprises: the driving current of the internal upper tube MN2 is adjusted by changing the size of the resistor R3; adjusting the reference voltage V by varying the magnitude of the resistor R4 REF2 To adjust the magnitude of the turn-off control signal V HX Is a narrow pulse width of (2); the on speed of the internal upper tube MN2 is adjusted by changing the sizes of the resistors R5 and C1, so that the opening speed of the external power device is adjusted, and the resistors R3, R4, R5 and the capacitor C1 can be adjusted outside the chip to adapt to different power devicesThe method can also be used for driving specific power devices on a chip.
The technical problem to be solved by the invention can be further solved by the following technical scheme, for the grid driving circuit based on the switching transient characteristic optimization, the upper tube and the lower tube of the output stage in the driving circuit are NMOS tubes, the grid driving signal of the lower tube MN1 is provided by the switching-off characteristic optimization circuit, and the grid driving signal of the upper tube MN2 is provided by the switching-on characteristic optimization circuit.
Compared with the prior art, the invention has the remarkable advantages that:
(1) The output stage driving of the invention adopts an NMOS transistor totem pole structure to drive an external power device, thereby improving the current driving capability, and simultaneously, the optimization mode is realized by adjusting the grid driving of an internal output NMOS rather than directly adjusting the grid circuit and the source drain circuit adding circuit of the external power transistor, thereby reducing the interference of a system and improving the reliability;
(2) The invention optimizes the on-off process separately and has adjustable parameters, and when the switch is turned off, the drive voltage of the NMOS tube at the low side of the internal output stage is controlled, so that the switch-off of the external power tube is controlled by the sectional current; when the power tube is conducted, the grid driving current of the high-side NMOS tube is controlled, and the charging and discharging speed of the grid capacitor is further adjusted to conduct the external power tube; the invention reduces the peak of current and voltage, improves the electromagnetic interference characteristic, optimizes the switching characteristic and further protects the safety of the system;
(3) The invention optimizes the switch characteristic of the grid electrode by adjusting the resistor and the capacitor, has simple structure, is easy to integrate the driving circuit and can realize on-chip driving.
Drawings
FIG. 1 is a schematic diagram of a conventional driving circuit;
FIG. 2 is a schematic diagram of a driving circuit according to the present invention;
FIG. 3 is a schematic diagram of a shutdown feature optimization circuit according to the present invention;
FIG. 4 is a schematic diagram of a conduction characteristic optimization circuit according to the present invention;
FIG. 5 is a schematic waveform diagram of the shut-down process optimization of the present invention;
FIG. 6 is a schematic waveform diagram of the optimization of the conduction process according to the present invention;
FIG. 7 is a schematic diagram of a linear voltage regulator circuit in the shutdown characteristic optimization circuit of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 2, an adjustable gate driving circuit based on switching transient characteristic optimization includes a turn-off characteristic optimization circuit 001, a turn-on characteristic optimization circuit 002, a reference circuit 003, an under-voltage protection circuit 004, a power-on reset circuit 005, an input stage schmitt circuit SMT1, a comparator circuit COM1, AND gate circuits AND1 AND2, an inverter circuit INV1, AND NMOS transistors MN1 AND MN2;
input signal V IN The input end of the input stage Schmidt circuit SMT1 is connected, and the output V of the input stage Schmidt circuit SMT1 IN1 An output signal V of the power-on reset circuit 005 connected to one input terminal of the AND gate circuit AND1 POR And an output signal V of the undervoltage protection circuit 004 UVLO Are respectively connected to the other two input terminals of the AND gate circuit AND1, the input terminal of the inverter circuit INV1 AND one input terminal of the off-characteristic optimizing circuit are interconnected AND are connected to the output signal V of the AND gate circuit AND1 L1 Connecting; output end V of inverter circuit INV1 H1 One input terminal connected to the AND gate AND2 AND one input terminal of the conduction characteristic optimization circuit 002, the output V of the reference circuit 003 REF1 Another input terminal connected to the conduction characteristic optimization circuit 002; an output signal V of the conduction characteristic optimization circuit 002 N2 Another output terminal V of the conduction characteristic optimization circuit 002 connected to the gate of the NMOS transistor MN2 REF2 Negative going connected to comparator COM1An input end, a source end of the NMOS tube MN2 and a drain end of the NMOS tube MN1 are connected together and used as an output signal V of the driving circuit OUT For driving an external power device; the drain of MN2 is connected to VCC, the source of MN1 is connected to GND, drive signal V OUT Is connected to the positive input of the comparator circuit COM1, the output signal V of the comparator circuit COM1 CT Connected to the other input of AND gate AND2, AND output signal V of AND gate AND2 HX Is connected to the other input of the shutdown characteristic optimization circuit 001, and the output signal V of the shutdown characteristic optimization circuit 001 N1 A gate connected to the NMOS transistor MN 1;
V IN as the input signal of the driving circuit, an undervoltage protection circuit and a power-on reset circuit are adopted in the chip to respectively output a protection signal V POR And V UVLO Protection signal and V IN Schmidt shaped signal V IN1 Together through a three-input logic AND gate circuit AND1 to output V L1 A signal as one input signal of the off-characteristic optimizing circuit; v (V) L1 Output V after passing through inverter INV1 H1 The signal, which is one input signal of the conduction characteristic optimization circuit, is V, which is the output signal of the comparator circuit COM1 CT Refers to the gate driving signal V OUT Higher than V REF2 After passing through AND gate circuit AND2, output V HX Signal V HX The signal is V IN Output signal V of driving circuit after converting into turn-off signal OUT Higher than V REF2 The off characteristic optimization circuit realizes the off characteristic optimization of the external power device through the narrow pulse.
As shown in fig. 3, the shutdown characteristic optimization circuit 001 includes: the linear voltage stabilizing circuit LDO, the gating circuit MUX1, the OR circuit OR1, the inverter INV2, the PMOS transistors MP 1-MP 5, the NMOS transistors MN 3-MN 7, and the resistors R1 and R2; the PMOS transistors MP 1-MP 4, the NMOS transistors MN 4-MN 6 and the resistor R1 form a bias circuit 201; lower tube driving signal V L1 Connected to the gate of NMOS transistor MN7 and one input of OR1, pulse signal V HX A control signal connected to the other input terminal of the OR gate OR1, the input terminal of the inverter INV2, the gate circuit MUX 1; the output end of the inverter INV2 is connected withThe output signal V of the linear voltage stabilizing circuit LDO is connected with the grid electrode of the NMOS tube MN3 LDO And GND signals are connected to two input terminals of the gate circuit MUX1, respectively; output signal V of gating circuit MUX1 TN A gate connected to the NMOS transistor MN 4; the source stage of the NMOS tube MN4 and the drain stage of the NMOS tube MN3 are connected to one end of a resistor R1, and the other end of the resistor R1 and the source stages of the NMOS tubes MN3, MN5 and MN7 are connected to GND; the source stages of the PMOS pipes MP1, MP3 and MP5 are connected to VCC, and the grid electrode and the drain stage of the PMOS pipe MP1, and the grid electrode of the PMOS pipe MP3 and the source electrode of the MP2 are connected together. The grid electrode and the drain electrode of MP2 and the grid electrode of MP4 are connected to the drain electrode of NMOS tube MN 4; the drain electrode of the PMOS tube MP3 is connected to the source electrode of the PMOS tube MP 4; the drain of the PMOS tube MP4 and the drain of the NMOS tube MN5 are connected to the drain of the NMOS tube MN 6; output signal V of OR1 LT The grid electrode is connected to the grid electrode of the NMOS tube MN6 and the grid electrode of the PMOS tube MP 5; the source electrode of the NMOS tube MN6, the grid electrode of the MN5 and the drain electrode of the PMOS tube MP5 are connected to one end of a resistor R2, the other end of the resistor R2 is connected to the drain electrode of the NMOS tube MN7, and the output signal V is used as an output signal V of the turn-off characteristic optimization circuit N1 ；
V L1 Is the driving signal of the down tube MN2, V HX Is output V OUT Higher than V after shut-off REF2 Is a narrow pulse signal of V LT Is at V L1 The pulse width is increased by V HX A narrow pulse width; the turn-off characteristic optimizing circuit utilizes V HX The narrow pulse width realizes the sectional control of the turn-off driving current of the external power device, thereby reducing the overshoot voltage and the EMI at the turn-off time; when V is L1 When the voltage is changed to a low level, the driving circuit starts to turn off, the MUX1 circuit and the bias circuit are controlled by the narrow pulse signal, the gating circuit MUX1 outputs LDO voltage, the NMOS tube MN4 is driven to turn on, the inverter INV2 outputs the low level, the NMOS tube MN3 is turned off, and the bias circuit 201 enables V to be formed N1 Outputting a low-voltage narrow pulse driving signal for driving the NMOS tube MN1 to be conducted, and driving an external power device to be turned off by using a lower current, wherein the amplitude of the low-voltage pulse is recorded as V LV1 ，V LV1 A threshold voltage higher than MN1, less than VCC, V after a narrow pulse signal LT Becomes low level, at this time, the bias circuit is turned off to output, V N1 The voltage is raised to VCC voltage by the PMOS tube MP5, and the external power device is driven by a higher current to be turned off rapidly.
As shown in fig. 4, the on-characteristic optimizing circuit 002 includes: operational amplifier OP1, PMOS tubes MP 6-MP 15, NMOS tubes MN 8-MN 14, resistors R3, R4, R5 and a capacitor C1; the PMOS transistors MP 6-MP 9, NMOS transistor MN8, resistors R3 and R4 form a bias circuit 1 202, the PMOS transistors MP 10-MP 13 and NMOS transistors MN 10-MN 13 form a bias circuit 2 203, and the source electrode of the PMOS transistor MP6, the source electrode of MP8, the source electrode of MP10, the source electrode of MP12 and the source electrode of MP14 are connected to VCC; one end of the resistor R3 and one end of the resistor R4, and one end of the source electrode of the NMOS tube MN9, the source electrode of the MN11, the source electrode of the MN12, the source electrode of the MN14 and the capacitor C1 are connected to GND; reference voltage V REF1 The positive input end of the operational amplifier OP1 is connected, the source electrode of the NMOS tube MN8 and the other end of the resistor R3 are connected to the negative input end of the operational amplifier OP1, and the grid electrode and the drain electrode of the PMOS tube MP6 are connected with the source electrode of the MP7, the grid electrode of the MP8 and the grid electrode of the MP 10; the grid and the drain of the PMOS tube MP7 are connected with the grid of the MP9, the grid of the MP11 and the drain of the NMOS tube MN8, the drain of the PMOS tube MP8 is connected with the source of the MP9, and the drain of the PMOS tube MP9 and the other end V of the resistor R4 REF2 Connected together as an output signal of the conduction characteristic optimization circuit; the drain of the PMOS tube MP10 is connected with the source of MP11, the drain of the PMOS tube MP11 is connected with the drain of the NMOS tube MN10 and the grid, the grid of MN13 and the drain of MN9, the source of the NMOS tube MN10, the drain of MN11 and the grid of MN12 are connected, the drain of the NMOS tube MN12 is connected with the source of MN13, the drain of NMOS tube MN13 is connected with the grid of the PMOS tube MP13 and the grid of MP15, the source of the PMOS tube MP13 is connected with the grid of MP12 and the grid of MP/4, the drain of the PMOS tube MP14 is connected with the source of MP15, the drain of the PMOS tube MP15 is connected with one end of a resistor R5 and the drain of the NMOS tube MN14 together to serve as an output driving signal V of the conduction characteristic optimizing circuit N2 The other end of the resistor R5 is connected with the other end of the capacitor C1 and is used for feeding a driving signal V H1 Gates connected to NMOS transistors MN9 and MN 14;
V REF1 is the reference voltage inside the chip, V H1 Is the driving signal of the upper tube MN2 inside the chip, and the driving signal is formed by the outputV in IN The signal is logically inverted by the reference voltage V REF1 And resistor R3 sets the initial bias current, as shown in equation 1, voltage V across resistor R4 REF2 As shown in formula 2, the initial bias current is amplified by the bias circuit 2 203, and then V N2 The current capacity of (2) is shown in formula 3, V H1 Control the turn-on and turn-off of the bias circuit 2 203, and further control the turn-on and turn-off of the upper NMOS transistor MN2, when V H1 When the voltage is at a high level, the bias circuit 2 203 is turned off, the NMOS transistor MN14 is turned on, and the output V of the characteristic optimizing circuit is turned on N2 The signal is low level, the upper NMOS tube MN2 is turned off, when V H1 At a low level, the output V of the conduction characteristic optimization circuit N2 The signal is high;
wherein N is 1 Is the ratio of the width-length ratio of MP8 to MP6, N 2 Is the ratio of the width to length ratio of MP10 and MP6, N 3 N is the ratio of the aspect ratio of MN13 to MN10 4 Is the ratio of the aspect ratio of MP14 to MP 12.
FIG. 5 is a schematic waveform diagram of the shutdown characteristic optimization circuit, when V L1 At a high level, V N1 At low level when V L1 When the voltage level is changed from high to low, V is HX With a T HX During this time V N1 Rise and hold to a low level voltage V LV1 The driving circuit outputs V OUT The signal falls with a lower slope when V HX When the pulse signal becomes low, V LT The signal goes low, V N1 Rapidly rise to VCC, drive circuit outputs V OUT The signal drops rapidly with higher slope, and when the actual circuit works, the internal comparator and other circuits have certain response time to drive the output signal and V N1 There is a certain delay between the signals.
FIG. 6 is a schematic waveform diagram of a conduction characteristic optimization circuit, when V L1 At low level, V H1 At a high level, V N2 At low level when V L1 V when changing from low level to high level H1 Becomes low level, V N2 Starts to become high level, V due to the influence of the resistors R5 and C1 N1 The rising time is slower, and the output V of the circuit is driven OUT The rise is smoother, the output voltage V of the driving circuit OUT The magnitude of the high level of (2) is VCC-V GS 。
V LV1 Can be adjusted by changing the magnitude of the resistor R1, and then V is adjusted when the switch-off is started HX The magnitude of the off-current within the pulse width; the reference voltage V can be adjusted by changing the resistance R4 REF2 The narrow pulse width at the start of turn-off is further adjusted, so that the turn-off speed of the external power device is adjusted by changing the sizes of the resistors R1 and R4; the driving current of the inner upper tube MN2 can be adjusted by changing the size of the resistor R3; the conduction speed of the upper tube MN2 is adjusted by changing the sizes of the resistors R5 and C1, so that the opening speed of the external power device is adjusted; the resistors R1, R3, R4, R5 and the capacitor C1 in the on-state characteristic optimizing circuit and the off-state characteristic optimizing circuit can be adjusted off-chip and used for adjusting according to different power devices so as to optimize the switching characteristics of external power devices, and can also be used for driving specific power devices on-chip.
FIG. 7 is a schematic diagram of a linear regulator LDO in a turn-off characteristics optimization circuit, wherein the LDO circuit comprises an operational amplifier OP2, an NMOS transistor MN15, resistors R6 and R7 and a capacitor C2; the positive input end of the operational amplifier OP2 is connected with the reference voltage V REF1 The method comprises the steps of carrying out a first treatment on the surface of the The negative input end is connected with one ends of the resistors R6 and R7, the other end of the resistor R7 is connected with one end of the capacitor C2, the other end of the resistor R6 is connected with the source electrode of the NMOS tube MN15, and the LDO circuit is formedOutput signal V of (2) LDO The method comprises the steps of carrying out a first treatment on the surface of the The output end of the operational amplifier OP2 is connected with the grid electrode of the MN15, and the drain electrode of the MN15 is connected with the VCC.
Claims (9)
1. A gate drive circuit based on switching transient characteristic optimization, characterized by: the power-on/power-off circuit comprises a turn-off characteristic optimizing circuit, a turn-on characteristic optimizing circuit, a reference circuit, an undervoltage protection circuit, a power-on reset circuit, an input stage Schmitt circuit SMT1, a comparator circuit COM1, AND gate circuits AND1 AND AND2, an inverter circuit INV1, NMOS transistors MN1 AND MN2;
input signal V IN The input end of the input stage Schmidt circuit SMT1 is connected, and the output V of the input stage Schmidt circuit SMT1 IN1 An output signal V of the power-on reset circuit connected to one input terminal of the AND gate circuit AND1 POR And an output signal V of the undervoltage protection circuit UVLO Are respectively connected to the other two input terminals of the AND gate circuit AND1, the input terminal of the inverter circuit INV1 AND one input terminal of the off-characteristic optimizing circuit are interconnected AND are connected to the output signal V of the AND gate circuit AND1 L1 Connecting; output end V of inverter circuit INV1 H1 One input terminal connected to AND gate AND2 AND one input terminal of the conduction characteristic optimization circuit, output V of the reference circuit REF1 Another input terminal connected to the conduction characteristic optimization circuit; an output signal V of the conduction characteristic optimization circuit N2 Another output terminal V of the conduction characteristic optimization circuit connected to the gate of the NMOS transistor MN2 REF2 The source end of the NMOS tube MN2 is connected with the drain end of the MN1 to be used as an output signal V of the driving circuit OUT For driving an external power device; the drain of MN2 is connected to VCC, the source of MN1 is connected to GND, drive signal V OUT Is connected to the positive input of the comparator circuit COM1, the output signal V of the comparator circuit COM1 CT Connected to the other input of AND gate AND2, output signal V of AND gate AND2 HX Connected to the other input of the shutdown characteristic optimization circuit, the output signal V of the shutdown characteristic optimization circuit N1 Is connected to the gate of NMOS transistor MN 1.
2. The switching transient characteristic optimized based gate driving circuit according to claim 1, wherein: the turn-off characteristic optimizing circuit includes: the linear voltage stabilizing circuit LDO, the gating circuit MUX1, the OR circuit OR1, the inverter INV2, the PMOS transistors MP 1-MP 5, the NMOS transistors MN 3-MN 7, and the resistors R1 and R2; the PMOS transistors MP 1-MP 4, the NMOS transistors MN 4-MN 6 and the resistor R1 form a bias circuit; lower tube driving signal V L1 Connected to the gate of NMOS transistor MN7 and one input of OR1, pulse signal V HX A control signal connected to the other input terminal of the OR circuit OR1, the input terminal of the inverter INV2, the gate circuit MUX 1; the output end of the inverter INV2 is connected with the grid electrode of the NMOS tube MN3, and the output signal V of the linear voltage stabilizing circuit LDO LDO And GND signals are connected to two input terminals of the gate circuit MUX1, respectively; output signal V of gating circuit MUX1 TN A gate connected to the NMOS transistor MN 4; the source stage of the NMOS tube MN4 and the drain stage of the NMOS tube MN3 are connected to one end of a resistor R1, and the other end of the resistor R1 and the source stages of the NMOS tubes MN3, MN5 and MN7 are connected to GND; the source stages of the PMOS pipes MP1, MP3 and MP5 are connected to VCC, and the grid electrode and the drain stage of the PMOS pipe MP1, and the grid electrode of the PMOS pipe MP3 and the source electrode of the MP2 are connected together; the grid electrode and the drain electrode of MP2 and the grid electrode of MP4 are connected to the drain electrode of NMOS tube MN 4; the drain electrode of the PMOS tube MP3 is connected to the source electrode of the PMOS tube MP 4; the drain of the PMOS tube MP4 and the drain of the NMOS tube MN5 are connected to the drain of the NMOS tube MN 6; output signal V of OR1 LT The grid electrode is connected to the grid electrode of the NMOS tube MN6 and the grid electrode of the PMOS tube MP 5; the source electrode of the NMOS tube MN6, the grid electrode of the MN5 and the drain electrode of the PMOS tube MP5 are connected to one end of a resistor R2, the other end of the resistor R2 is connected to the drain electrode of the NMOS tube MN7, and the output signal V is used as an output signal V of the turn-off characteristic optimization circuit N1 。
3. The switching transient characteristic optimized based gate driving circuit according to claim 2, wherein: the turn-off characteristic optimizing circuit comprises: when V is L1 When the voltage level is changed to a low level, the driving circuit starts to turn off, and the MUX1 circuit and the biasing circuit are controlled by the narrow pulse signal to enable V N1 A low-voltage narrow pulse driving signal is output for driving the conduction of the NMOS tube MN1,the external power device is driven to turn off by a lower current, and the amplitude of the low-voltage narrow pulse is denoted as V LV1 ，V LV1 A threshold voltage higher than MN1, less than VCC, V after a narrow pulse signal LT Becomes low level, at this time, the bias circuit is turned off to output, V N1 The voltage is raised to VCC voltage by the PMOS tube MP5, and the external power device is driven by a higher current to be turned off rapidly.
4. A gate drive circuit based on switching transient characteristic optimization as claimed in claim 3, wherein: the turn-off characteristic optimizing circuit comprises: v (V) LV1 Can be adjusted by changing the size of the resistor R1, thereby adjusting V HX The magnitude of the off-current within the pulse width; the resistor can be adjusted off-chip to adapt to different power devices, and can also be used for driving specific power devices on-chip.
5. The switching transient characteristic optimized based gate driving circuit according to claim 2, wherein: the turn-off characteristic optimizing circuit comprises: v (V) L1 Is the driving signal of the down tube MN2, V HX Is output V OUT Higher than V after shut-off REF2 Is a narrow pulse signal of V LT The driving signal is at V L1 The pulse width is increased by V HX A narrow pulse width; the turn-off characteristic optimizing circuit utilizes V HX The narrow pulse width realizes the sectional control of the turn-off driving current of the external power device, thereby reducing the overshoot voltage and the EMI at the turn-off time.
6. The switching transient characteristic optimized based gate driving circuit according to claim 1, wherein: the conduction characteristic optimization circuit includes: operational amplifier OP1, PMOS tubes MP 6-MP 15, NMOS tubes MN 8-MN 14, resistors R3, R4, R5 and a capacitor C1; PMOS transistors MP 6-MP 9, NMOS transistor MN8, resistors R3 and R4 form a bias circuit 1, PMOS transistors MP 10-MP 13 and NMOS transistors MN 10-MN 13 form a bias circuit 2, the source of the PMOS transistor MP6, the source of MP8, the source of MP10, the source of MP12 and the source of MP14 are connected to VA CC; one end of the resistor R3, one end of the resistor R4, one end of the source of the NMOS tube MN9, one end of the source of the MN11, one end of the source of the MN12, one end of the source of the MN14 and one end of the capacitor C1 are connected to GND; reference voltage V REF1 The positive input end of the operational amplifier OP1 is connected, the source electrode of the NMOS tube MN8 and the other end of the resistor R3 are connected to the negative input end of the operational amplifier OP1, and the grid electrode and the drain electrode of the PMOS tube MP6 are connected with the source electrode of the MP7, the grid electrode of the MP8 and the grid electrode of the MP 10; the grid and the drain of the PMOS tube MP7 are connected with the grid of the MP9, the grid of the MP11 and the drain of the NMOS tube MN8, the drain of the PMOS tube MP8 is connected with the source of the MP9, and the drain of the PMOS tube MP9 and the other end V of the resistor R4 REF2 Connected together as an output signal of the conduction characteristic optimization circuit; the drain of the PMOS tube MP10 is connected with the source of MP11, the drain of the PMOS tube MP11 is connected with the drain of the NMOS tube MN10 and the grid, the grid of MN13 and the drain of MN9, the source of the NMOS tube MN10, the drain of MN11 and the grid of MN12 are connected, the drain of the NMOS tube MN12 is connected with the source of MN13, the drain of the NMOS tube MN13 is connected with the grid of the PMOS tube MP13 and the grid of MP15, the source of the PMOS tube MP13 is connected with the grid of MP12 and the grid of MP14, the drain of the PMOS tube MP14 is connected with the source of MP15, the drain of the PMOS tube MP15 is connected with one end of a resistor R5 and the drain of the NMOS tube MN14 together to serve as an output driving signal V of the conduction characteristic optimization circuit N2 The other end of the resistor R5 is connected with the other end of the capacitor C1 and is used for feeding a driving signal V H1 Is connected to the gates of NMOS transistors MN9 and MN 14.
7. The switching transient characteristic optimized based gate drive circuit of claim 6, wherein: the conduction characteristic optimization circuit comprises: v (V) REF1 Is the reference voltage inside the chip, V H1 Is the driving signal of the upper tube MN2 inside the chip, which is formed by the input signal V IN Signal of logical inversion, reference voltage V REF1 And resistor R3 sets an initial bias current, and the bias circuits 1 and2 amplify the current according to a certain ratio, thereby adjusting the output signal V N2 V of the current driving capability of (1) H1 The bias circuit 2 is controlled to be turned on and off so as to control the upper NMOS tube MN2 on and off, when V H1 When high, the bias circuit 2 is turned off, and the output V of the characteristic optimizing circuit is turned on N2 The signal is low and the upper tube NMOS tube MN2 is turned off.
8. The switching transient characteristic optimized based gate drive circuit of claim 6, wherein: the conduction characteristic optimization circuit comprises: the driving current of the internal upper tube MN2 is adjusted by changing the size of the resistor R3; adjusting the reference voltage V by varying the magnitude of the resistor R4 REF2 To adjust the magnitude of the turn-off control signal V HX Is a narrow pulse width of (2); the on-speed of the internal upper tube MN2 is adjusted by changing the sizes of the resistors R5 and C1, so that the on-speed of the external power device is adjusted, the resistors R3, R4, R5 and the capacitor C1 can be adjusted off-chip, and the internal upper tube MN is suitable for different power devices and can be used for driving specific power devices on-chip.
9. The switching transient characteristic optimized based gate driving circuit according to claim 1, wherein: the upper tube and the lower tube of the output stage in the driving circuit are NMOS tubes, the grid driving signal of the lower tube MN1 is provided by the turn-off characteristic optimizing circuit, and the grid driving signal of the upper tube MN2 is provided by the turn-on characteristic optimizing circuit.
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| CN103490599A (en) * | 2013-09-16 | 2014-01-01 | 电子科技大学 | Power tube subsection grid driving circuit |
| CN107493095A (en) * | 2017-08-09 | 2017-12-19 | 东南大学 | Silicon substrate IGBT and the grid drive system of SiC schottky diode mixing |
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