CN113541662A - Gate drive circuit based on switching transient characteristic optimization - Google Patents

Gate drive circuit based on switching transient characteristic optimization Download PDF

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Publication number
CN113541662A
CN113541662A CN202110705294.8A CN202110705294A CN113541662A CN 113541662 A CN113541662 A CN 113541662A CN 202110705294 A CN202110705294 A CN 202110705294A CN 113541662 A CN113541662 A CN 113541662A
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circuit
drain
gate
tube
nmos
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CN113541662B (en
Inventor
席伟
王廷营
孙彬
张雨
刘忠超
陈大科
罗佳亮
杨静
祝靖
钱钦松
孙伟锋
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Southeast University
Lianyungang Jierui Electronics Co Ltd
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Southeast University
Lianyungang Jierui Electronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K2017/0803—Modifications for protecting switching circuit against overcurrent or overvoltage against radiation hardening
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An adjustable gate drive circuit based on switch transient characteristic optimization comprises a turn-off characteristic optimization circuit, a turn-on characteristic optimization circuit, a reference circuit, an undervoltage protection circuit, a power-on reset circuit, an input stage Schmitt circuit SMT1, a comparator circuit COM1, AND gate circuits AND1 AND AND2, an inverter circuit INV1, an NMOS tube MN1 AND an MN 2; the switching-on and switching-off processes of the external power device are optimized separately and adjustable, and the switching-off of the external power device is controlled by segmented current by controlling the driving voltage of the low-side NMOS tube of the internal output stage during the switching-off process; when the power transistor is conducted, the conduction of an external power transistor is adjusted by controlling the grid drive current of the output level high-side NMOS transistor and the charging and discharging speed of the grid capacitor. The invention can reduce current and voltage peaks, improve electromagnetic interference characteristics, optimize switching characteristics and further protect the safety of an application system.

Description

Gate drive circuit based on switching transient characteristic optimization
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a gate drive circuit based on switching transient characteristic optimization.
Background
A power field effect transistor (MOSFET) is a unipolar voltage control device with majority carriers conducting, and has the advantages of fast switching speed, good high-frequency performance, high input impedance, low noise, low driving power, and the like, so that it is increasingly applied to devices such as switching power supplies, ac frequency conversion speed regulators, inverters, and the like.
The driving of the MOSFET is crucial to its operation, and in order to obtain good performance, the power device needs a suitable driving circuit, and the research on the gate driving circuit of the power device is very much, mainly based on the consideration of the switching speed, the switching loss, the overshoot current, the overshoot voltage and the electromagnetic interference. Fast switching speeds result in higher current, voltage overshoot, and EMI, while slow switching speeds result in longer turn-on and turn-off delays and higher switching losses. However, with the continuous increase of the operating frequency, the requirement for the driving speed becomes higher, and the high on-off speed inevitably causes obvious voltage and current impact, waveform oscillation phenomena, electromagnetic interference and other problems, thereby seriously affecting the safety and reliability of the power system equipment and requiring the optimization of the driving circuit.
As shown in fig. 1, in a conventional driving circuit, a larger gate resistor Ron is used for driving the power device S1 to be turned on, and a lower gate resistor Roff is used for driving the power device S1 to be turned off, so that the compromise processing method is simple and cannot meet the situation with higher requirements on switching characteristics; in the prior art, a gate driving circuit with adjustable gate resistance specifically optimizes the method that in the current rising stage of an external power tube S1, a large gate resistance is used for restraining reverse recovery current, and in the drain-source voltage falling stage of the external power tube, a small gate resistance is used for controlling the falling rate and reducing the turn-on loss; however, the method of changing the gate resistance is rough, the resistance is generally changed only once in a single switching process, and the switching on and off are difficult to optimize simultaneously. In the prior art, a control mode of adjusting the gate voltage based on drain voltage detection is also available, and the purpose of adjusting di/dt and dv/dt is achieved by detecting the drain voltage of an external power tube S1 to be compared with a reference voltage and adjusting the gate driving voltage according to a comparison voltage result, but the drain detection circuit needs a high-voltage circuit and is also complex; there are also a number of prior art di-basedC/dt、dvCEThe/dt closed-loop detection realizes a control mode of optimizing driving, but for closed-loop control, the detection precision is difficult to control, and feedback necessarily has a certain delay, however, the detection precision and the feedback delay have great influence on the control performance, and the circuit is difficult to optimize.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art and provides a grid driving circuit based on switching transient characteristic optimization, which has the advantages of reasonable design, simple structure, externally adjustable on-off driving current and easiness in optimizing the switching characteristic of a power device.
The technical problem to be solved by the present invention is achieved by the following technical means. The invention relates to a gate drive circuit based on switch transient characteristic optimization, which comprises a turn-off characteristic optimization circuit, a conduction characteristic optimization circuit, a reference circuit, an undervoltage protection circuit, a power-on reset circuit, an input stage Schmitt circuit SMT1, a comparator circuit COM1, AND gate circuits AND1 AND AND2, an inverter circuit INV1, an NMOS tube MN1 AND an MN 2;
input signal VINConnected to the input of an input stage Schmitt circuit SMT1 and to the output V of an input stage Schmitt circuit SMT1IN1An output signal V of the power-on reset circuit connected to an input terminal of the AND gate circuit AND1POROutput signal V of under-voltage protection circuitUVLOConnected to the other two input terminals of the AND circuit AND1, respectively, the input terminal of the inverter circuit INV1 AND one input terminal of the shutdown characteristic optimization circuit are connected to each other AND the output signal V of the AND circuit AND1L1Connecting; output end V of inverter circuit INV1H1Connected to one input terminal of the AND gate AND2 AND one input terminal of the conduction characteristic optimizing circuit, AND output V of the reference circuitREF1The other input end is connected to the conduction characteristic optimization circuit; an output signal V of the conduction characteristic optimizing circuitN2The other output terminal V of the conduction characteristic optimization circuit is connected to the grid electrode of the NMOS tube MN2REF2Connected to the negative input terminal of the comparator circuit COM1, the source terminal of the NMOS transistor MN2 and the drain terminal of MN1 are connected together as the output signal V of the driving circuitOUTFor driving an external power device; the drain terminal of MN2 is connected to VCC, the source terminal of MN1 is connected to GND, and the drive signal VOUTConnected to the positive input of the comparator circuit COM1, the output signal V of the comparator circuit COM1CTConnected to the other input terminal of the AND circuit AND2, the output signal V of the AND circuit AND2HXConnected to the other input of the shutdown characteristic optimization circuit, the output signal V of the shutdown characteristic optimization circuitN1Is connected to the gate of the NMOS transistor MN 1.
The technical problems to be solved by the present invention can also be solved by the following techniquesThe present invention is further achieved by a gate driving circuit optimized based on switching transient characteristics as described above, wherein the gate driving circuit includes: the LDO linear voltage stabilizing circuit, the gating circuit MUX1, the OR gate OR1, the inverter INV2, the PMOS tubes MP 1-MP 5, the NMOS tubes MN 3-MN 7, and the resistors R1 and R2; PMOS tubes MP 1-MP 4, NMOS tubes MN 4-MN 6 and a resistor R1 form a bias circuit; lower tube drive signal VL1Connected to one input terminal of the gate OR1 of the NMOS transistor MN7HXA control signal connected to the other input terminal of the OR gate OR1, the input terminal of the inverter INV2, the gating circuit MUX 1; the output end of the inverter INV2 is connected with the grid electrode of the NMOS tube MN3, and the output signal V of the linear voltage stabilizing circuit LDOLDOAnd the GND signal are respectively connected to two input terminals of the gating circuit MUX 1; output signal V of gating circuit MUX1TNA gate connected to the NMOS transistor MN 4; the source of the NMOS transistor MN4 and the drain of the NMOS transistor MN3 are connected to one end of a resistor R1, and the other end of the resistor R1 and the source of the NMOS transistors MN3, MN5 and MN7 are connected to GND; the source electrodes of the PMOS tubes MP1, MP3 and MP5 are connected to VCC, the grid electrode and the drain electrode of the PMOS tube MP1, the grid electrode of the PMOS tube MP3 and the source electrode of the MP2 are connected together; the gate and drain of MP2, and the gate of MP4 are connected to the drain of NMOS transistor MN 4; the drain of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP 4; the drain of the PMOS transistor MP4 and the drain of the NMOS transistor MN5 are connected to the drain of the NMOS transistor MN 6; output signal V of OR gate OR1LTThe grid electrode of the NMOS transistor MN6 and the grid electrode of the PMOS transistor MP5 are connected; the source of the NMOS transistor MN6, the gate of the MN5 and the drain of the PMOS transistor MP5 are connected to one end of a resistor R2, the other end of the resistor R2 is connected to the drain of the NMOS transistor MN7, and the output signal V is used as an output signal of the turn-off characteristic optimization circuitN1。
The technical problem to be solved by the present invention can be further solved by the following technical solution, in the gate driving circuit based on the switching transient characteristic optimization, the turn-off characteristic optimization circuit comprises: when V isL1When the level goes low, the driver circuit starts to turn off, and first the MUX1 circuit and the bias circuit are controlled by the narrow pulse signal so that V isN1Outputting a low-voltage narrow-pulse driving signal for driving the NMOS transistor MN1 to be conducted to be lowThe current drives the external power device to turn off, and the amplitude of the low-voltage pulse is recorded as VLV1，VLV1Above the threshold voltage of MN1, below the VCC voltage, after a narrow pulse signal, VLTBecomes low level, at which time the bias circuit is turned off to output VN1The voltage is raised to VCC by the PMOS transistor MP5, and the external power device is driven to turn off rapidly by a higher current.
The technical problem to be solved by the present invention can be further solved by the following technical solution, in the gate driving circuit based on the switching transient characteristic optimization, the turn-off characteristic optimization circuit comprises: vLV1Can be adjusted by changing the size of the resistor R1, and then the V is adjustedHXThe magnitude of the off current within the pulse width; the resistor can be adjusted outside the chip to adapt to different power devices, and can also be used for driving a specific power device on the chip.
The technical problem to be solved by the present invention can be further solved by the following technical solution, in the gate driving circuit based on the switching transient characteristic optimization, the turn-off characteristic optimization circuit comprises: vL1Is the drive signal, V, of down tube MN2HXIs an output VOUTHigher than V after shut-offREF2Of narrow pulse signal VLTThe drive signal is at VL1A V is added on the basis of the pulse widthHXA narrow pulse width; the turn-off characteristic optimizing circuit utilizes VHXThe narrow pulse width realizes the sectional control of the turn-off driving current of an external power device, thereby reducing the overshoot voltage and EMI at the turn-off time.
The technical problem to be solved by the present invention can be further solved by the following technical solution, where for the gate driving circuit based on the switching transient characteristic optimization, the turn-on characteristic optimization circuit includes: the operational amplifier OP1, PMOS tubes MP 6-MP 15, NMOS tubes MN 8-MN 14, resistors R3, R4, R5 and a capacitor C1; PMOS tubes MP 6-MP 9, NMOS tube MN8, resistors R3 and R4 form a bias circuit 1, PMOS tubes MP 10-MP 13 and NMOS tubes MN 10-MN 13 form a bias circuit 2, and the source electrode of PMOS tube MP6, MP8, MP10 and MP12 are respectively connected with a power supplyThe pole and source of MP14 are connected to VCC; one end of the resistor R3, one end of the resistor R4, the source of the NMOS transistor MN9, the source of the NMOS transistor MN11, the source of the NMOS transistor MN12, the source of the NMOS transistor MN14 and one end of the capacitor C1 are connected to GND; reference voltage VREF1The power amplifier is connected to a positive input end of an operational amplifier OP1, a source electrode of an NMOS transistor MN8 and the other end of a resistor R3 are connected to a negative input end of an operational amplifier OP1, and a gate and a drain of a PMOS transistor MP6 are connected with a source electrode of MP7, a gate electrode of MP8 and a gate electrode of MP 10; the grid and the drain of the PMOS tube MP7 are connected with the grid of MP9, the grid of MP11 and the drain of the NMOS tube MN8, the drain of the PMOS tube MP8 is connected with the source of MP9, the drain of the PMOS tube MP9 and the other end V of the resistor R4REF2Connected together as an output signal of the conduction characteristic optimizing circuit; the drain of a PMOS tube MP10 is connected with the source of an MP11, the drain of a PMOS tube MP11 is connected with the drain and the gate of an NMOS tube MN10, the gate of MN13 and the drain of MN9, the source of an NMOS tube MN10, the drain of MN11 and the gate of MN11 are connected with the gate of MN12, the drain of an NMOS tube MN12 is connected with the source of MN13, the drain of an NMOS tube MN13 is connected with the gate and the drain of a PMOS tube MP13 and the gate of MP15, the source of a PMOS tube MP13 is connected with the gate and the drain of MP12 and the gate of MP14, the drain of a PMOS tube MP14 is connected with the source of MP15, the drain of a PMOS tube MP15 is connected with one end of a resistor R5 and the drain of an NMOS tube MN14, and is used as an output driving signal V of a conduction characteristic optimization circuitN2The other end of the resistor R5 is connected to the other end of the capacitor C1, and the upper tube driving signal VH1And the grid electrodes of the NMOS tubes MN9 and MN14 are connected.
The technical problem to be solved by the present invention can be further solved by the following technical solution, in the gate driving circuit based on the switching transient characteristic optimization, the switching characteristic optimization circuit includes: vREF1Is the reference voltage, V, inside the chipH1Is the driving signal of upper tube MN2 inside the chip, which is formed by input signal VINSignal for performing logical inversion, reference voltage VREF1And a resistor R3 for setting initial bias current, amplifying the current according to a certain ratio by a bias circuit 1 and a bias circuit 2, and adjusting the output signal VN2Current driving capability of VH1Controlling the bias circuit 2Turning on and off to control the on and off of the upper tube NMOS tube MN2 when V isH1When the voltage is high, the bias circuit 2 is turned off, and the output V of the characteristic optimizing circuit is turned onN2The signal is low and the upper pipe NMOS transistor MN2 is off.
The technical problem to be solved by the present invention can be further solved by the following technical solution, in the gate driving circuit based on the switching transient characteristic optimization, the switching characteristic optimization circuit includes: the driving current of the internal upper tube MN2 is adjusted by changing the size of the resistor R3; adjusting the reference voltage V by varying the magnitude of the resistor R4REF2Is used to turn off the control signal VHXA narrow pulse width of (d); the on-state speed of the internal upper tube MN2 is adjusted by changing the sizes of the resistor R5 and the resistor C1, so that the on-state speed of an external power device is adjusted, and the resistors R3, R4, R5 and the capacitor C1 can be adjusted outside a chip to adapt to different power devices and can also be used for driving a specific power device on the chip.
The technical problem to be solved by the present invention can be further solved by the following technical solution, for the above-mentioned gate driving circuit based on the switching transient characteristic optimization, both the upper tube and the lower tube of the output stage in the driving circuit are NMOS tubes, the gate driving signal of the lower tube MN1 is provided by the turn-off characteristic optimization circuit, and the gate driving signal of the upper tube MN2 is provided by the turn-on characteristic optimization circuit.
Compared with the prior art, the invention has the following remarkable advantages:
(1) the output stage drive adopts an NMOS tube totem-pole structure to drive an external power device, so that the current drive capability is improved, meanwhile, the optimization mode is realized by adjusting the grid drive of the internal output NMOS, and the adjustment is not directly carried out by adding circuits to a grid circuit and a source drain stage circuit of the external power tube, so that the interference of a system is reduced, and the reliability is improved;
(2) the invention optimizes the turn-on and turn-off processes separately and has adjustable parameters, and the turn-off of the external power tube is controlled by controlling the driving voltage of the low-side NMOS tube of the internal output stage during the turn-off process so as to realize the turn-off of the external power tube by sectional current; when the power transistor is conducted, the conduction of an external power transistor is adjusted by controlling the grid drive current of the output level high-side NMOS transistor and the charge-discharge speed of the grid capacitor; according to the invention, the current and voltage spikes are reduced, the electromagnetic interference characteristic is improved, the switching characteristic is optimized, and the safety of the system is further protected;
(3) the invention optimizes the grid switch characteristic by adjusting the resistor and the capacitor, has simple structure, is easy to integrate the driving circuit and can realize on-chip driving.
Drawings
FIG. 1 is a diagram of a conventional driving circuit;
FIG. 2 is a schematic diagram of a driving circuit according to the present invention;
FIG. 3 is a schematic diagram of a turn-off characteristic optimization circuit according to the present invention;
FIG. 4 is a schematic diagram of a circuit for optimizing the turn-on characteristics according to the present invention;
FIG. 5 is a waveform diagram illustrating the optimization of the turn-off process according to the present invention;
FIG. 6 is a waveform diagram illustrating the optimization of the conduction process according to the present invention;
FIG. 7 is a diagram of a linear voltage regulator circuit in the shutdown characteristic optimization circuit of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, an adjustable gate driving circuit based on switching transient characteristic optimization includes a turn-off characteristic optimization circuit 001, a turn-on characteristic optimization circuit 002, a reference circuit 003, an undervoltage protection circuit 004, a power-on reset circuit 005, an input stage schmitt circuit SMT1, a comparator circuit COM1, AND gate circuits AND1 AND2, an inverter circuit INV1, AND NMOS transistors MN1 AND MN 2;
input signal VINConnected to the input of an input stage Schmitt circuit SMT1 and to the output V of an input stage Schmitt circuit SMT1IN1An output signal V of the power-on-reset circuit 005 connected to one input terminal of the AND circuit AND1PORAnd the output signal V of the undervoltage protection circuit 004UVLOConnected to the other two input terminals of the AND circuit AND1, respectively, the input terminal of the inverter circuit INV1 AND one input terminal of the shutdown characteristic optimization circuit are connected to each other AND the output signal V of the AND circuit AND1L1Connecting; output end V of inverter circuit INV1H1An output V of the reference circuit 003 is connected to one input terminal of the AND gate AND2 AND one input terminal of the on-characteristic optimizing circuit 002REF1Another input terminal connected to the on characteristic optimizing circuit 002; an output signal V of the on-characteristic optimizing circuit 002N2Another output terminal V of the conduction characteristic optimizing circuit 002 connected to the gate of the NMOS transistor MN2REF2Connected to the negative input terminal of the comparator COM1, the source terminal of the NMOS transistor MN2 and the drain terminal of MN1 are connected together as the output signal V of the driving circuitOUTFor driving an external power device; the drain terminal of MN2 is connected to VCC, the source terminal of MN1 is connected to GND, and the drive signal VOUTConnected to the positive input of the comparator circuit COM1, the output signal V of the comparator circuit COM1CTConnected to the other input of AND gate AND2, the output signal V of AND gate AND2HXConnected to the other input of the shutdown characteristic optimization circuit 001, the output signal V of the shutdown characteristic optimization circuit 001N1A gate connected to the NMOS transistor MN 1;
VINas the input signal of the drive circuit, the chip adopts an undervoltage protection circuit and a power-on reset circuit to respectively output a protection signal VPORAnd VUVLOProtection signal and VINSchmidt shaped signal VIN1The V is output after passing through a three-input logic AND gate circuit AND1L1A signal as an input signal of the shutdown characteristic optimization circuit; vL1Outputs V after passing through an inverter INV1H1The signal as an input signal of the on-characteristic optimizing circuit, the output signal of the comparator circuit COM1 is VCTRefers to the gate drive signal VOUTHigher than VREF2The square wave signal of (2) is output V after passing through an AND circuit AND2HXSignal, VHXThe signal being VINOutput signal V of driving circuit after being converted into turn-off signalOUTHigher than VREF2The turn-off characteristic optimizing circuit optimizes the turn-off characteristic of the external power device by the narrow pulse.
As shown in fig. 3, the shutdown characteristic optimization circuit 001 includes: the LDO linear voltage stabilizing circuit, the gating circuit MUX1, the OR gate OR1, the inverter INV2, the PMOS tubes MP 1-MP 5, the NMOS tubes MN 3-MN 7, and the resistors R1 and R2; PMOS tubes MP 1-MP 4, NMOS tubes MN 4-MN 6 and resistor R1 form a bias circuit 201; lower tube drive signal VL1Connected to one input terminal of the gate OR1 of the NMOS transistor MN7HXA control signal connected to the other input terminal of the OR gate OR1, the input terminal of the inverter INV2, the gating circuit MUX 1; the output end of the inverter INV2 is connected with the grid electrode of the NMOS tube MN3, and the output signal V of the linear voltage stabilizing circuit LDOLDOAnd the GND signal are respectively connected to two input terminals of the gating circuit MUX 1; output signal V of gating circuit MUX1TNA gate connected to the NMOS transistor MN 4; the source of the NMOS transistor MN4 and the drain of the NMOS transistor MN3 are connected to one end of a resistor R1, and the other end of the resistor R1 and the source of the NMOS transistors MN3, MN5 and MN7 are connected to GND; the source electrodes of the PMOS tubes MP1, MP3 and MP5 are connected to VCC, the grid electrode and the drain electrode of the PMOS tube MP1, the grid electrode of the PMOS tube MP3 and the source electrode of the MP2 are connected together. The gate and drain of MP2, and the gate of MP4 are connected to the drain of NMOS transistor MN 4; the drain of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP 4; the drain of the PMOS transistor MP4 and the drain of the NMOS transistor MN5 are connected to the drain of the NMOS transistor MN 6; output signal V of OR gate OR1LTThe grid electrode of the NMOS transistor MN6 and the grid electrode of the PMOS transistor MP5 are connected; the source of the NMOS transistor MN6, the gate of the MN5 and the drain of the PMOS transistor MP5 are connected to one end of a resistor R2, the other end of the resistor R2 is connected to the drain of the NMOS transistor MN7, and the output signal V is used as an output signal of the turn-off characteristic optimization circuitN1；
VL1Is the drive signal, V, of down tube MN2HXIs an output VOUTHigher than V after shut-offREF2Of narrow pulse signal VLTIs at VL1A V is added on the basis of the pulse widthHXA narrow pulse width; the turn-off characteristic optimizing circuit utilizes VHXThe narrow pulse width realizes the sectional control of the turn-off driving current of an external power device, thereby reducing the overshoot voltage and EMI at the turn-off time; when V isL1When the voltage is changed to be low level, the driving circuit starts to be switched off, firstly, the MUX1 circuit and the biasing circuit are controlled through the narrow pulse signal, the gating circuit MUX1 outputs LDO voltage to drive the NMOS tube MN4 to be switched on, at the moment, the inverter INV2 outputs low level, the NMOS tube MN3 is switched off, and the biasing circuit 201 enables V to be changed into V to enable V to be switched offN1Outputting a low-voltage narrow pulse driving signal for driving the NMOS transistor MN1 to be switched on and driving an external power device to be switched off by a lower current, wherein the amplitude of the low-voltage pulse is recorded as VLV1，VLV1Above the threshold voltage of MN1, below the VCC voltage, after a narrow pulse signal, VLTBecomes low level, at which time the bias circuit is turned off to output VN1The voltage is raised to VCC by the PMOS transistor MP5, and the external power device is driven to turn off rapidly by a higher current.
As shown in fig. 4, the on-characteristic optimizing circuit 002 includes: the operational amplifier OP1, PMOS tubes MP 6-MP 15, NMOS tubes MN 8-MN 14, resistors R3, R4, R5 and a capacitor C1; PMOS tubes MP 6-MP 9, NMOS tube MN8, resistors R3 and R4 form a bias circuit 1202, PMOS tubes MP 10-MP 13 and NMOS tubes MN 10-MN 13 form a bias circuit 2203, and the source electrode of the PMOS tube MP6, the source electrode of the MP8, the source electrode of the MP10, the source electrode of the MP12 and the source electrode of the MP14 are connected to VCC; one end of the resistor R3 and one end of the resistor R4, the source of the NMOS transistor MN9, the source of MN11, the source of MN12, the source of MN14 and one end of the capacitor C1 are connected to GND; reference voltage VREF1The power amplifier is connected to a positive input end of an operational amplifier OP1, a source electrode of an NMOS transistor MN8 and the other end of a resistor R3 are connected to a negative input end of an operational amplifier OP1, and a gate and a drain of a PMOS transistor MP6 are connected with a source electrode of MP7, a gate electrode of MP8 and a gate electrode of MP 10; the grid and the drain of the PMOS tube MP7 are connected with the grid of MP9, the grid of MP11 and the drain of the NMOS tube MN8, the drain of the PMOS tube MP8 is connected with the source of MP9, the drain of the PMOS tube MP9 and the other end V of the resistor R4REF2Connected together as an output signal of the conduction characteristic optimizing circuit;the drain of a PMOS tube MP10 is connected with the source of an MP11, the drain of a PMOS tube MP11 is connected with the drain and the gate of an NMOS tube MN10, the gate of MN13 and the drain of MN9, the source of an NMOS tube MN10, the drain of MN11 and the gate of MN11 are connected with the gate of MN12, the drain of an NMOS tube MN12 is connected with the source of MN13, the drain of an NMOS tube MN13 is connected with the gate and the drain of a PMOS tube MP13 and the gate of MP15, the source of a PMOS tube MP13 is connected with the gate and the drain of MP12 and the gate of MP/4, the drain of a PMOS tube MP14 is connected with the source of MP15, the drain of a PMOS tube MP15 is connected with one end of a resistor R5 and the drain of an NMOS tube MN14, and is used as an output driving signal V of a conduction characteristic optimization circuitN2The other end of the resistor R5 is connected to the other end of the capacitor C1, and the upper tube driving signal VH1Gates connected to NMOS transistors MN9 and MN 14;
VREF1is the reference voltage, V, inside the chipH1Is the driving signal of upper tube MN2 inside the chip, which is driven by input VINThe signal being logically inverted by a reference voltage VREF1And resistor R3 sets the initial bias current, as shown in equation 1, the voltage V across resistor R4REF2Is shown in formula 2, after the initial bias current is amplified by the bias circuit 2203, V isN2The current capacity of (A) is shown in equation 3, VH1Controlling the on and off of the bias circuit 2203, and further controlling the on and off of the upper tube NMOS tube MN2 when V isH1When the voltage is high, the bias circuit 2203 is turned off, the NMOS transistor MN14 is turned on, and the output V of the characteristic optimization circuit is turned onN2The signal is low level, the upper tube NMOS tube MN2 is turned off when V isH1At a low level, the output V of the on-characteristic optimizing circuitN2The signal is high level;
Figure BDA0003130942300000121
Figure BDA0003130942300000122
Figure BDA0003130942300000123
wherein N is1Ratio of width to length of MP8 to MP6, N2Is the ratio of the width to length ratios of MP10 and MP6, N3Is the ratio of width to length ratios of MN13 and MN10, N4Is the ratio of the width to length ratios of MP14 and MP 12.
FIG. 5 is a waveform diagram of the shutdown characteristic optimization circuit when VL1At high level, VN1At a low level, when VL1When changing from high level to low level, at this time VHXHaving a THXDuring the time of the pulse signal of (V)N1Rises and holds to a low level voltage VLV1The output V of the driving circuitOUTThe signal falls with a lower slope when VHXWhen the pulse signal becomes low, VLTThe signal changes to low level, VN1Rises to VCC quickly, drives circuit output VOUTThe signal is rapidly reduced at a higher slope, and when the actual circuit works, the internal comparator and other circuits have certain response time to drive the output signal and VN1There is a certain delay between the signals.
FIG. 6 is a waveform diagram of the on-state characteristic optimizing circuit when V isL1At low level, VH1Is at a high level, at this time VN2At a low level, when VL1When changing from low level to high level, VH1Change to low level, VN2Initially goes high, V due to the influence of resistors R5 and C1N1The rise time is slower, and the output V of the driving circuitOUTThe rising is smooth, and the output voltage V of the driving circuitOUTThe high level amplitude value is VCC-VGS。
VLV1Can be adjusted by changing the size of the resistor R1, and then adjusting V when starting to turn offHXThe magnitude of the off current within the pulse width; the reference voltage V can be adjusted by changing the size of the resistor R4REF2To adjust the narrow pulse width at the start of turn-off, thus adjusting the turn-off speed of the external power device by changing the size of the resistors R1 and R4;the driving current of the internal upper tube MN2 can be adjusted by changing the size of the resistor R3; the conduction speed of the upper tube MN2 is adjusted by changing the sizes of the resistors R5 and C1, so that the starting speed of an external power device is adjusted; the resistors R1, R3, R4 and R5 and the capacitor C1 in the on-characteristic optimization circuit and the off-characteristic optimization circuit can be adjusted outside the chip and used for adjusting according to different power devices, optimizing the switching characteristic of an external power device and driving a specific power device on the chip.
FIG. 7 is a schematic diagram of a structure of a linear regulator LDO circuit in a turn-off characteristic optimization circuit, wherein the LDO circuit comprises an operational amplifier OP2, an NMOS transistor MN15, resistors R6 and R7, and a capacitor C2; the positive input end of the operational amplifier OP2 is connected with a reference voltage VREF1(ii) a The negative input end of the resistor R is connected with one ends of the resistors R6 and R7, the other end of the resistor R7 and one end of the capacitor C2 are connected with GND, the other end of the resistor R6 and the other end of the capacitor C2 are connected with the source electrode of an NMOS (N-channel metal oxide semiconductor) tube MN15, and the negative input end of the resistor R is used as an output signal V of the LDO (low dropout regulator) circuitLDO(ii) a The output end of the operational amplifier OP2 is connected with the gate of the MN15, and the drain of the MN15 is connected with VCC.

Claims (9)

1. A gate drive circuit based on switching transient characteristic optimization is characterized in that: the under-voltage protection circuit comprises a turn-off characteristic optimization circuit, a conduction characteristic optimization circuit, a reference circuit, an under-voltage protection circuit, a power-on reset circuit, an input stage Schmitt circuit SMT1, a comparator circuit COM1, AND circuits AND1 AND AND2, an inverter circuit INV1, an NMOS tube MN1 AND an MN 2;
input signal VINConnected to the input of an input stage Schmitt circuit SMT1 and to the output V of an input stage Schmitt circuit SMT1IN1An output signal V of the power-on reset circuit connected to an input terminal of the AND gate circuit AND1POROutput signal V of under-voltage protection circuitUVLOConnected to the other two input terminals of the AND circuit AND1, respectively, the input terminal of the inverter circuit INV1 AND one input terminal of the shutdown characteristic optimization circuit are connected to each other AND the output signal V of the AND circuit AND1L1Connecting; output end V of inverter circuit INV1H1Connected to one input terminal of AND gate AND2, one input terminal of the conduction characteristic optimization circuit, AND the output terminal of the reference circuitGo out VREF1The other input end is connected to the conduction characteristic optimization circuit; an output signal V of the conduction characteristic optimizing circuitN2The other output terminal V of the conduction characteristic optimization circuit is connected to the grid electrode of the NMOS tube MN2REF2Connected to the negative input terminal of the comparator circuit COM1, the source terminal of the NMOS transistor MN2 and the drain terminal of MN1 are connected together as the output signal V of the driving circuitOUTFor driving an external power device; the drain terminal of MN2 is connected to VCC, the source terminal of MN1 is connected to GND, and the drive signal VOUTConnected to the positive input of the comparator circuit COM1, the output signal V of the comparator circuit COM1CTConnected to the other input terminal of the AND circuit AND2, the output signal V of the AND circuit AND2HXConnected to the other input of the shutdown characteristic optimization circuit, the output signal V of the shutdown characteristic optimization circuitN1Is connected to the gate of the NMOS transistor MN 1.
2. The switching transient characteristic optimization-based gate drive circuit of claim 1, wherein: the shutdown characteristic optimization circuit includes: the LDO linear voltage stabilizing circuit, the gating circuit MUX1, the OR gate OR1, the inverter INV2, the PMOS tubes MP 1-MP 5, the NMOS tubes MN 3-MN 7, and the resistors R1 and R2; PMOS tubes MP 1-MP 4, NMOS tubes MN 4-MN 6 and a resistor R1 form a bias circuit; lower tube drive signal VL1Connected to one input terminal of the gate OR1 of the NMOS transistor MN7HXA control signal connected to the other input terminal of the OR gate OR1, the input terminal of the inverter INV2, the gating circuit MUX 1; the output end of the inverter INV2 is connected with the grid electrode of the NMOS tube MN3, and the output signal V of the linear voltage stabilizing circuit LDOLDOAnd the GND signal are respectively connected to two input terminals of the gating circuit MUX 1; output signal V of gating circuit MUX1TNA gate connected to the NMOS transistor MN 4; the source of the NMOS transistor MN4 and the drain of the NMOS transistor MN3 are connected to one end of a resistor R1, and the other end of the resistor R1 and the source of the NMOS transistors MN3, MN5 and MN7 are connected to GND; the source electrodes of the PMOS tubes MP1, MP3 and MP5 are connected to VCC, the grid electrode and the drain electrode of the PMOS tube MP1, the grid electrode of the PMOS tube MP3 and the source electrode of the MP2 are connected together; the gate and drain of MP2 and the gate of MP4 are connected to NMOS transistor MN4The drain of (1); the drain of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP 4; the drain of the PMOS transistor MP4 and the drain of the NMOS transistor MN5 are connected to the drain of the NMOS transistor MN 6; output signal V of OR gate OR1LTThe grid electrode of the NMOS transistor MN6 and the grid electrode of the PMOS transistor MP5 are connected; the source of the NMOS transistor MN6, the gate of the MN5 and the drain of the PMOS transistor MP5 are connected to one end of a resistor R2, the other end of the resistor R2 is connected to the drain of the NMOS transistor MN7, and the output signal V is used as an output signal of the turn-off characteristic optimization circuitN1。
3. The switching transient characteristic optimization-based gate drive circuit of claim 2, wherein: in the shutdown characteristic optimization circuit: when V isL1When the level goes low, the driver circuit starts to turn off, and first the MUX1 circuit and the bias circuit are controlled by the narrow pulse signal so that V isN1Outputting a low-voltage narrow pulse driving signal for driving the NMOS transistor MN1 to be switched on and driving an external power device to be switched off by a lower current, wherein the amplitude of the low-voltage pulse is recorded as VLV1，VLV1Above the threshold voltage of MN1, below the VCC voltage, after a narrow pulse signal, VLTBecomes low level, at which time the bias circuit is turned off to output VN1The voltage is raised to VCC by the PMOS transistor MP5, and the external power device is driven to turn off rapidly by a higher current.
4. The switching transient characteristic optimization-based gate drive circuit of claim 3, wherein: in the shutdown characteristic optimization circuit: vLV1Can be adjusted by changing the size of the resistor R1, and then the V is adjustedHXThe magnitude of the off current within the pulse width; the resistor can be adjusted outside the chip to adapt to different power devices, and can also be used for driving a specific power device on the chip.
5. The switching transient characteristic optimization-based gate drive circuit of claim 2, wherein: in the shutdown characteristic optimization circuit: vL1Is the drive signal, V, of down tube MN2HXIs an output VOUTHigher than V after shut-offREF2Of narrow pulse signal VLTThe drive signal is at VL1A V is added on the basis of the pulse widthHXA narrow pulse width; the turn-off characteristic optimizing circuit utilizes VHXThe narrow pulse width realizes the sectional control of the turn-off driving current of an external power device, thereby reducing the overshoot voltage and EMI at the turn-off time.
6. The switching transient characteristic optimization-based gate drive circuit of claim 1, wherein: the on-state characteristic optimizing circuit includes: the operational amplifier OP1, PMOS tubes MP 6-MP 15, NMOS tubes MN 8-MN 14, resistors R3, R4, R5 and a capacitor C1; PMOS tubes MP 6-MP 9, NMOS tube MN8, resistors R3 and R4 form a bias circuit 1, PMOS tubes MP 10-MP 13 and NMOS tubes MN 10-MN 13 form a bias circuit 2, and the source electrode of the PMOS tube MP6, the source electrode of the MP8, the source electrode of the MP10, the source electrode of the MP12 and the source electrode of the MP14 are connected to VCC; one end of the resistor R3, one end of the resistor R4, the source of the NMOS transistor MN9, the source of the NMOS transistor MN11, the source of the NMOS transistor MN12, the source of the NMOS transistor MN14 and one end of the capacitor C1 are connected to GND; reference voltage VREF1The power amplifier is connected to a positive input end of an operational amplifier OP1, a source electrode of an NMOS transistor MN8 and the other end of a resistor R3 are connected to a negative input end of an operational amplifier OP1, and a gate and a drain of a PMOS transistor MP6 are connected with a source electrode of MP7, a gate electrode of MP8 and a gate electrode of MP 10; the grid and the drain of the PMOS tube MP7 are connected with the grid of MP9, the grid of MP11 and the drain of the NMOS tube MN8, the drain of the PMOS tube MP8 is connected with the source of MP9, the drain of the PMOS tube MP9 and the other end V of the resistor R4REF2Connected together as an output signal of the conduction characteristic optimizing circuit; the drain of a PMOS tube MP10 is connected with the source of MP11, the drain of a PMOS tube MP11 is connected with the drain and the gate of an NMOS tube MN10, the gate of MN13 and the drain of MN9, the source of an NMOS tube MN10, the drain of MN11 and the gate of MN11 are connected with the gate of MN12, the drain of an NMOS tube MN12 is connected with the source of MN13, the drain of an NMOS tube MN13 is connected with the gate and the drain of a PMOS tube MP13 and the gate of MP15, the source of a PMOS tube MP13 is connected with the gate and the drain of MP12 and the gate of MP14, the drain of a PMOS tube MP14 is connected with the source of MP15, the drain of a PMOS tube MP15 is connected with one end of a resistor R5 and the drain of an NMOS tube MN14As an output drive signal V of the on-characteristic optimizing circuitN2The other end of the resistor R5 is connected to the other end of the capacitor C1, and the upper tube driving signal VH1And the grid electrodes of the NMOS tubes MN9 and MN14 are connected.
7. The switching transient characteristic optimization-based gate drive circuit of claim 6, wherein: in the conduction characteristic optimization circuit: vREF1Is the reference voltage, V, inside the chipH1Is the driving signal of upper tube MN2 inside the chip, which is formed by input signal VINSignal for performing logical inversion, reference voltage VREF1And a resistor R3 for setting initial bias current, amplifying the current according to a certain ratio by a bias circuit 1 and a bias circuit 2, and adjusting the output signal VN2Current driving capability of VH1Controlling the on and off of the bias circuit 2, and further controlling the on and off of the upper tube NMOS tube MN2 when V isH1When the voltage is high, the bias circuit 2 is turned off, and the output V of the characteristic optimizing circuit is turned onN2The signal is low and the upper pipe NMOS transistor MN2 is off.
8. The switching transient characteristic optimization-based gate drive circuit of claim 6, wherein: in the conduction characteristic optimization circuit: the driving current of the internal upper tube MN2 is adjusted by changing the size of the resistor R3; adjusting the reference voltage V by varying the magnitude of the resistor R4REF2Is used to turn off the control signal VHXA narrow pulse width of (d); the on-state speed of the internal upper tube MN2 is adjusted by changing the sizes of the resistor R5 and the resistor C1, so that the on-state speed of an external power device is adjusted, and the resistors R3, R4, R5 and the capacitor C1 can be adjusted outside a chip to adapt to different power devices and can also be used for driving a specific power device on the chip.
9. The switching transient characteristic optimization-based gate drive circuit of claim 1, wherein: an output stage upper tube and a lower tube in the driving circuit are NMOS tubes, a gate driving signal of the lower tube MN1 is provided by a turn-off characteristic optimization circuit, and a gate driving signal of the upper tube MN2 is provided by a turn-on characteristic optimization circuit.
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Publication number Priority date Publication date Assignee Title
CN103490599A (en) * 2013-09-16 2014-01-01 电子科技大学 Power tube subsection grid driving circuit
CN107493095A (en) * 2017-08-09 2017-12-19 东南大学 Silicon substrate IGBT and the grid drive system of SiC schottky diode mixing
CN108762363A (en) * 2018-06-25 2018-11-06 电子科技大学 A kind of LDO circuit of push-pull output stage
CN109951178A (en) * 2019-04-03 2019-06-28 电子科技大学 A kind of system protection method of GaN gate drive circuit
CN110149042A (en) * 2019-06-14 2019-08-20 电子科技大学 A kind of power tube gate driving circuit with drive part by part function
CN111293860A (en) * 2020-03-20 2020-06-16 电子科技大学 High-side conductance enhanced power switch driving circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103490599A (en) * 2013-09-16 2014-01-01 电子科技大学 Power tube subsection grid driving circuit
CN107493095A (en) * 2017-08-09 2017-12-19 东南大学 Silicon substrate IGBT and the grid drive system of SiC schottky diode mixing
CN108762363A (en) * 2018-06-25 2018-11-06 电子科技大学 A kind of LDO circuit of push-pull output stage
CN109951178A (en) * 2019-04-03 2019-06-28 电子科技大学 A kind of system protection method of GaN gate drive circuit
CN110149042A (en) * 2019-06-14 2019-08-20 电子科技大学 A kind of power tube gate driving circuit with drive part by part function
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