CN103001475A - Short-circuit protecting circuit applied to synchronous boost type direct current-direct current (DC-DC) converter - Google Patents
Short-circuit protecting circuit applied to synchronous boost type direct current-direct current (DC-DC) converter Download PDFInfo
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- CN103001475A CN103001475A CN2012104707915A CN201210470791A CN103001475A CN 103001475 A CN103001475 A CN 103001475A CN 2012104707915 A CN2012104707915 A CN 2012104707915A CN 201210470791 A CN201210470791 A CN 201210470791A CN 103001475 A CN103001475 A CN 103001475A
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Abstract
The invention discloses a short-circuit protecting circuit applied to a synchronous boost type direct current-direct current (DC-DC) converter and mainly solves the problems that the response speed is low and short wave (SW) signals are overshot in terms of short-circuit protecting circuits in prior art. The circuit comprises a p-channel metal oxide semiconductor (PMOS) substrate selection circuit, a hiccup logical circuit, a counter, a logic signal processing module, a PMOS switch control circuit, a drive circuit and a high-end PMOS pipe (PH), the hiccup logical circuit is connected with the logic signal processing module, the logic signal processing module is connected with the counter, the counter is connected with the hiccup logical circuit, the drive circuit is connected with a grid electrode of the high-end PMOS pipe (PH), the PMOS substrate selection circuit is connected between the hiccup logical circuit and a substrate of the high-end PMOS pipe (PH) in a crossing mode and used for determining whether a short circuit occurs or not and providing substrate electric potential for the high-end PMOS pipe (PH), and the PMOS switch control circuit is connected between the logic signal processing module and the drive circuit in the crossing mode and used for controlling connection and disconnection speeds of the high-end PMOS pipe (PH). By means of the short-circuit protecting circuit applied to the synchronous boost type DC-DC converter, the response speed of the short-circuit protection is increased, the SW signals are prevented from being overshot, and the short-circuit protecting circuit can be used for a device with a DC-DC switching power supply.
Description
Technical field
The invention belongs to the electronic circuit technology field, relate to protective circuit, can be used for analog integrated circuit.
Background technology
In field of power management, the main switch of synchronous boost type DC-DC transducer adopts high-end PMOS pipe and low side NMOS to manage two types, the source electrode of NMOS pipe is held GND with being connected to, drains to be the output pin SW of DC-DC transducer, and the source electrode of PMOS pipe is connected to the output pin V of DC-DC transducer
OUT, drain electrode is connected to the output pin SW of DC-DC transducer.So when chip exterior is short-circuited, V
OUTBe forced to end, the drain terminal voltage SW meeting overshoot of high-end PMOS pipe causes high-end PMOS pipe to flow through very large short circuit current, and high-end PMOS pipe is burnt with being shorted to.Therefore, short-circuit protection circuit is widely used in the synchronous boost type DC-DC transducer chip effectively being protected.
Short-circuit protection circuit is by detecting VOUT voltage or its voltage division signal FB; when its value is lower than a certain particular value; namely judge the chip short circuit; thereby make corresponding variation by logical circuit; turn-off high-end PMOS pipe and low side NMOS pipe; inside circuit and short circuit current are kept apart, and the protection chip is not burned.
Fig. 1 has provided the structure chart of a synchronous boost type DC-DC transducer, input voltage V
INBe connected to the SW end by inductance L, low side NMOS is connected between SW and the GND, when opening inductance is charged, and high-end PMOS is connected to SW and V
OUTBetween, when opening inductance is discharged, finish discharging and recharging of inductive current by the switch motion of NMOS and PMOS, thereby realize stable direct current boosting power signal V of output
OUT
Fig. 2 has provided a traditional short-circuit protection circuit figure, V
OUTVoltage division signal FB and reference voltage REF07 are connected respectively to two inputs of comparator; The output signal FBLOW of comparator and overheat protector signal OTP are connected respectively to two inputs of Hicup logical circuit; The output signal EnHicup of Hicup logical circuit and benchmark start two inputs that settling signal ON is connected respectively to counter module; After the output signal ToHicup process logical signal processing module of the complete signal GO of counting of counter module output and Hicup logical circuit, react on high-end PMOS pipe P with drive circuit one
HThe grid end, control high-end PMOS pipe P
HShutoff and conducting.When the chip short circuit, V
OUTBe pulled to GND, so the FB signal also is pulled to GND, like this can be so that high-end PMOS pipe P be turn-offed in the comparator upset
HPipe keeps this state to count simultaneously; After rolling counters forward finished, if still short circuit of chip, then chip was in the process of beginning soft start, and the output level of trigger comparator turn-offs high-end PMOS pipe P again
H, repeat the state of above short-circuit protection; If chip is short circuit no longer, then chip can normally start.But in the process of this short-circuit protection, the FB signal is pulled to the speed ratio V of GND
OUTBe shorted to GND and want slow, and the response speed of voltage comparator is also slow, might be so that the partial short circuit electric current flows through high-end PMOS pipe P
H, cause high-end PMOS pipe P
HDamage.And the output signal of logical signal processing module is direct and drive circuit one reacts on high-end PMOS pipe P
HThe grid end, turn-off rapidly easily or open high-end PMOS pipe P
H, cause the SW overshoot, cause high-end PMOS pipe P
HFlow through very large electric current, damage circuit.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned existing short-circuit protection circuit; a kind of short-circuit protection circuit that is applied to synchronous boost type DC-DC transducer is provided; to improve the response speed of short-circuit protection circuit; and the function of providing substrate electric potential to select for simultaneously high-end PMOS pipe, thereby the phenomenon of SW overshoot occurs when avoiding high-end PMOS pipe to carry out switch motion.
For achieving the above object, short-circuit protection circuit of the present invention comprises Hicup logical circuit 2, counter 3, logical signal processing module 4, drive circuit 6 and high-end PMOS pipe P
HThe first output a of Hicup logical circuit 2 is connected to the first input end b of logical signal processing module 4; The second input c of logical signal processing module 4 is connected to the output d of counter 3; The second input e of counter 3 is connected to the second Ausgang of Hicup logical circuit 2, is used for the control short-circuit protection time; The output g of drive circuit 6 is connected to high-end PMOS pipe P
HGrid, be used for controlling high-end PMOS pipe P
HConducting and shutoff; High-end PMOS pipe P
HSource electrode be connected to output pin V
OUT, drain electrode is connected to output pin SW; It is characterized in that:
The first input end h of Hicup logical circuit 2 and high-end PMOS pipe P
HSubstrate between cross-over connection have the PMOS substrate to select circuit 1, be used for judging the whether short circuit of synchronous boost type DC-DC transducer, and be that high-end PMOS manages P
HSubstrate electric potential is provided;
Cross-over connection has PMOS ON-OFF control circuit 5 between the output i of logical signal processing module 4 and the output g of drive circuit 6, is used for controlling high-end PMOS pipe P
HConducting and turn-off speed.
As preferably, above-mentioned short-circuit protection circuit, wherein said PMOS substrate is selected circuit 1, comprises seven PMOS pipes, seven NMOS pipes, two logic inverters (INV1, INV2), resistance R 1 and current source I1;
Described PMOS pipe MP1, its grid link to each other with the grid of the 2nd PMOS pipe MP2 and consist of active electric current mirror structure, and its source electrode links to each other with an end of resistance R 1, and its drain electrode links to each other with the drain electrode of the 2nd NMOS pipe MN2;
Described the 2nd PMOS pipe MP2, its drain electrode links to each other with the drain electrode of the 4th NMOS pipe MN4, consists of output signal O
1Be connected to the grid of the 3rd PMOS pipe MP3, its source electrode selects the second input of circuit 1 to link to each other with the PMOS substrate;
Described the 3rd PMOS pipe MP3, its source electrode is as the first input end of PMOS substrate selection circuit 1, and its grid is connected to the drain electrode of the 2nd PMOS pipe MP2, and its drain electrode links to each other with the drain electrode of the 5th NMOS pipe MN5 and consists of output signal O
2Be connected to the input of the first logic inverter INV1;
Described the 4th PMOS pipe MP4 and the 6th NMOS pipe MN6 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit 1, and input is connected to the second output that the PMOS substrate is selected circuit 1, and output is connected to the grid of the 5th PMOS pipe MP5;
Described the 5th PMOS pipe MP5, its grid is connected to the drain electrode of the 4th PMOS pipe MP4, and be connected to the drain electrode that the 6th NMOS manages MN6, and its source electrode is connected to the first input end that the PMOS substrate is selected circuit 1, and its drain electrode is connected to the first output that the PMOS substrate is selected circuit 1;
Described the 6th PMOS pipe MP6, its grid is connected to the drain electrode of the 7th PMOS pipe MP7, and be connected to the drain electrode that the 7th NMOS manages MN7, and its source electrode is connected to the second input that the PMOS substrate is selected circuit 1, and its drain electrode is connected to the first output that the PMOS substrate is selected circuit 1;
Described the 7th PMOS pipe MP7 and the 7th NMOS pipe MN7 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit 1, and input is connected to the grid of the 5th PMOS pipe MP5, and output is connected to the grid of the 6th PMOS pipe MP6;
Described NMOS pipe MN1, the 4th NMOS pipe MN4 and the 5th NMOS pipe MN5, their source electrode altogether, and grid links to each other and consists of active electric current mirror structure, and their drain electrode is connected respectively to the output of current source I1, the drain electrode of the 2nd PMOS pipe MP2 and the drain electrode of the 3rd PMOS pipe MP3;
Described the 2nd NMOS pipe MN2, its source electrode is connected to the drain electrode of the 3rd NMOS pipe MN3, and its grid is connected to the grid of NMOS pipe MN1, and its drain electrode links to each other with the drain electrode of PMOS pipe MP1;
Described the 3rd NMOS pipe MN3, its source ground, its drain electrode links to each other with the source electrode of the 2nd NMOS pipe MN2, and its grid is connected with the output of the first logic inverter INV1, consists of sluggish feedback control loop;
Described the first logic inverter INV1 and the second logic inverter INV2 consist of series connection structure, and the input of the first logic inverter INV1 is connected to output node O
2, the output of the first logic inverter INV1 is connected to the input of the second logic inverter INV2 and the grid of the 3rd NMOS pipe MN3, and the output of the second logic inverter INV2 is selected the second output of circuit 1 as the PMOS substrate;
One end of described resistance R 1 is connected to the source electrode of PMOS pipe MP1, and the other end is connected to first input end;
The output of described current source I1 is connected to the drain electrode of NMOS pipe MN1, selects circuit 1 for the PMOS substrate bias current is provided.
As preferably, above-mentioned short-circuit protection circuit, wherein said PMOS ON-OFF control circuit 5 comprises PMOS pipe PM1, two switches (K1, K2), current source I0 and two logic inverters (INV1, INV2);
Described PMOS pipe PM1, its source electrode is connected to the first output that the PMOS substrate is selected circuit 1, and its grid links to each other with drain electrode, and is connected to the d end of second switch K2;
Described the first K switch 1, one end c is connected to the input of current source I0, and other end a links to each other with the f end of second switch K2, and is connected to the output of PMOS ON-OFF control circuit 5, is used for controlling high-end PMOS pipe P
HConducting and turn-off speed, its control end b is connected to the output of the second not gate INV2;
Described second switch K2, one end d are connected to the drain electrode of PMOS pipe PM1, and other end f links to each other with a end of the first K switch 1, and is connected to the output of PMOS ON-OFF control circuit 5, and control end e is connected to the output of the first logic inverter INV1;
Described current source I0, its input is connected output head grounding with the c end of the first logic switch K1;
Described the first logic inverter INV1, its input is connected to the output of logical signal processing module 4, and its output is connected with the input of the second logic inverter INV2, and is connected to the control end e of second switch K2, conducting and the shutoff of control second switch K2;
Described the second logic inverter INV2, its input is connected to the output of the first logic inverter INV1, and output links to each other the conducting of control switch K1 and shutoff with the control end b of the first K switch 1.
The present invention compared with prior art has the following advantages:
(1) the present invention is high-end PMOS pipe P by PMOS substrate selection circuit
HSubstrate electric potential is provided, makes high-end PMOS pipe P
HSubstrate can be connected to maximum potential all the time, avoided high-end PMOS pipe P
HThe parasitic diode conducting of substrate has prevented high-end PMOS pipe P
HThe SW overshoot causes damage to circuit in the switch motion process;
(2) the present invention is owing to select circuit to output signal V by the PMOS substrate
OUTWith input signal V
INSubtract 500 millivolts of later voltage swings and compare, thereby judge in advance the short-circuit condition of chip, accelerated the response speed of short-circuit protection circuit.
(3) the present invention is owing to manage P by the PMOS ON-OFF control circuit to high-end PMOS
HConducting and shutoff control so that the pipe of the high-end PMOS among the present invention P
HConducting and turn-off speed than the high-end PMOS pipe P of traditional short-circuit protection circuit
HConducting and turn-off speed slow, avoided at high-end PMOS pipe P
HThe damage that the SW overshoot causes circuit during switch motion.
Description of drawings
Fig. 1 is the circuit structure block diagram of synchronous boost type DC-DC transducer;
Fig. 2 is traditional short-circuit protection circuit structured flowchart;
Fig. 3 is the structured flowchart of short-circuit protection circuit of the present invention;
Fig. 4 is the schematic diagram that the PMOS substrate is selected circuit the 1st embodiment among the present invention;
Fig. 5 is the schematic diagram that the PMOS substrate is selected circuit the 2nd embodiment among the present invention;
Fig. 6 is the schematic diagram of PMOS ON-OFF control circuit the 1st embodiment among the present invention;
Fig. 7 is the schematic diagram of PMOS ON-OFF control circuit the 2nd embodiment among the present invention.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and embodiment.
With reference to Fig. 3, the short-circuit protection circuit that the present invention is applied to synchronous boost type DC-DC transducer comprises: the PMOS substrate is selected circuit 1, Hicup logical circuit 2, counter 3, logical signal processing module 4, PMOS ON-OFF control circuit 5, drive circuit 6 and high-end PMOS pipe P
HWherein the first output a of Hicup logical circuit 2 is connected to the first input end b of logical signal processing module 4; The second input c of logical signal processing module 4 is connected to the output d of counter 3; The second input e of counter 3 is connected to the second Ausgang of Hicup logical circuit 2, is used for the control short-circuit protection time; The output g of drive circuit 6 is connected to high-end PMOS pipe P
HGrid, be used for controlling high-end PMOS pipe P
HConducting and shutoff; High-end PMOS pipe P
HSource electrode be connected to output pin V
OUT, drain electrode is connected to output pin SW; The first input end h of Hicup logical circuit 2 and high-end PMOS pipe P
HSubstrate between cross-over connection have the PMOS substrate to select circuit 1, be used for judging the whether short circuit of synchronous boost type DC-DC transducer, and be that high-end PMOS manages P
HSubstrate electric potential is provided; Cross-over connection has PMOS ON-OFF control circuit 5 between the output i of logical signal processing module 4 and the output g of drive circuit 6, is used for controlling high-end PMOS pipe P
HConducting and turn-off speed;
Described PMOS substrate selects the first input end i of circuit 1 to be connected to input signal V
IN, the second input j is connected to output signal V
OUT, the first output l is connected to high-end PMOS pipe P
HSubstrate, the second output m is connected to the first input end h of Hicup logical circuit 2;
The second input n of described Hicup logical circuit 2 is connected to overheat protector signal OTP;
The first input end o of described counter 3 is connected to enabling signal ON;
The input p of described PMOS ON-OFF control circuit 5 is connected to the output i of logical signal processing module 4, and output q is connected to the output g of drive circuit 6.
Below provide circuit structure of the present invention:
Embodiment 1
Described Hicup logical circuit 2 is made of the logical AND NOR gate, is used for the logical signal of input is carried out logical process, the output logic level signal.
Described counter 3, can but be not limited only to be consisted of by logical AND NOR gate, d type flip flop and oscillator, wherein, oscillator provides clock signal for this counter, d type flip flop is counted clock signal, the logical AND NOR gate by input signal is carried out logical process control d type flip flop begin the counting.
Described logical signal processing module 4 is made of the logical AND NOR gate, is used for the logical signal of input is carried out logical process, the output logic level signal.
Described drive circuit 6, can but the not gate that is not limited only to amplify by different size, step by step consist of.
Described PMOS substrate is selected circuit 1, and as shown in Figure 4, it comprises seven PMOS pipes, seven NMOS pipes, the first logic inverter INV1, the second logic inverter INV2, resistance R 1 and current source I1, wherein:
The one PMOS manages MP1, and its grid links to each other with the grid of the 2nd PMOS pipe MP2 and consists of active electric current mirror structure, and its source electrode links to each other with an end of resistance R 1, and its drain electrode links to each other with the drain electrode of the 2nd NMOS pipe MN2;
The 2nd PMOS manages MP2, and its drain electrode links to each other with the drain electrode of the 4th NMOS pipe MN4, consists of output signal O
1Be connected to the grid of the 3rd PMOS pipe MP3, its source electrode selects the second input of circuit 1 to link to each other with the PMOS substrate;
The 3rd PMOS manages MP3, and its source electrode is as the first input end of PMOS substrate selection circuit 1, and its grid is connected to the drain electrode of the 2nd PMOS pipe MP2, and its drain electrode links to each other with the drain electrode of the 5th NMOS pipe MN5 and consists of output signal O
2Be connected to the input of the first logic inverter INV1;
The 4th PMOS pipe MP4 and the 6th NMOS pipe MN6 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit 1, and input is connected to the second output that the PMOS substrate is selected circuit 1, and output is connected to the grid of the 5th PMOS pipe MP5;
The 5th PMOS manages MP5, and its grid is connected to the drain electrode of the 4th PMOS pipe MP4, and is connected to the drain electrode of the 6th NMOS pipe MN6, and its source electrode is connected to the first input end that the PMOS substrate is selected circuit 1, and its drain electrode is connected to the first output that the PMOS substrate is selected circuit 1;
The 6th PMOS manages MP6, and its grid is connected to the drain electrode of the 7th PMOS pipe MP7, and is connected to the drain electrode of the 7th NMOS pipe MN7, and its source electrode is connected to the second input that the PMOS substrate is selected circuit 1, and its drain electrode is connected to the first output that the PMOS substrate is selected circuit 1;
The 7th PMOS pipe MP7 and the 7th NMOS pipe MN7 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit 1, and input is connected to the grid of the 5th PMOS pipe MP5, and output is connected to the grid of the 6th PMOS pipe MP6;
The one NMOS pipe MN1, the 4th NMOS pipe MN4 and the 5th NMOS pipe MN5, their source electrode altogether, and grid links to each other and consists of active electric current mirror structure, and their drain electrode is connected respectively to the output of current source I1, the drain electrode of the 2nd PMOS pipe MP2 and the drain electrode of the 3rd PMOS pipe MP3;
The 2nd NMOS manages MN2, and its source electrode is connected to the drain electrode of the 3rd NMOS pipe MN3, and its grid is connected to the grid of NMOS pipe MN1, and its drain electrode links to each other with the drain electrode of PMOS pipe MP1;
The 3rd NMOS manages MN3, its source ground, and its drain electrode links to each other with the source electrode of the 2nd NMOS pipe MN2, and its grid is connected with the output of the first logic inverter INV1, consists of sluggish feedback control loop;
The first logic inverter INV1 and the second logic inverter INV2 consist of series connection structure, and the input of the first logic inverter INV1 is connected to output node O
2, the output of the first logic inverter INV1 is connected to the input of the second logic inverter INV2 and the grid of the 3rd NMOS pipe MN3, and the output of the second logic inverter INV2 is selected the second output of circuit 1 as the PMOS substrate;
One end of resistance R 1 is connected to the source electrode of PMOS pipe MP1, and the other end is connected to first input end;
The output of current source I1 is connected to the drain electrode of NMOS pipe MN1, selects circuit 1 for the PMOS substrate bias current is provided.
Described PMOS ON-OFF control circuit 5, as shown in Figure 6, it comprises PMOS pipe PM1, the first K switch 1, second switch K2, current source I0, the first logic inverter INV1 and the second logic inverter INV2; Wherein:
PMOS manages PM1, and its source electrode is connected to the first output that the PMOS substrate is selected circuit 1, and its grid links to each other with drain electrode, and is connected to the d end of second switch K2;
The first K switch 1, one end c is connected to the input of current source I0, and other end a links to each other with the f end of second switch K2, and is connected to the output of PMOS ON-OFF control circuit 5, is used for controlling high-end PMOS pipe P
HConducting and turn-off speed, its control end b is connected to the output of the second not gate INV2;
Second switch K2, one end d are connected to the drain electrode of PMOS pipe PM1, and other end f links to each other with a end of the first K switch 1, and is connected to the output of PMOS ON-OFF control circuit 5, and control end e is connected to the output of the first logic inverter INV1;
Current source I0, its input is connected output head grounding with the c end of the first logic switch K1;
The first logic inverter INV1, its input is connected to the output of logical signal processing module 4, and its output is connected with the input of the second logic inverter INV2, and is connected to the control end e of second switch K2, conducting and the shutoff of control second switch K2;
The second logic inverter INV2, its input is connected to the output of the first logic inverter INV1, and output links to each other with the control end b of the first K switch 1, controls conducting and the shutoff of the first K switch 1.
The Hicup logical circuit 2 of this example, counter 3, logical signal processing module 4 are identical with embodiment 1 with drive circuit 6 modules;
Described PMOS substrate is selected circuit 1, and as shown in Figure 5, it comprises ten PMOS pipes, seven NMOS pipes, the first logic inverter INV1, the second logic inverter INV2 and current source I1;
The one PMOS manages MP1, and its grid links to each other with the grid of the 2nd PMOS pipe MP2 and consists of active electric current mirror structure, and its source electrode links to each other with the drain electrode of the tenth PMOS pipe MP10, and its drain electrode links to each other with the drain electrode of the 2nd NMOS pipe MN2;
The 2nd PMOS manages MP2, and its drain electrode links to each other with the drain electrode of the 4th NMOS pipe MN4, consists of output signal O
1Be connected to the grid of the 3rd PMOS pipe MP3, its source electrode selects the second input of circuit 1 to link to each other with the PMOS substrate;
The 3rd PMOS manages MP3, and its source electrode is connected to the first input end that the PMOS substrate is selected circuit 1, and its grid is connected to the drain electrode of the 2nd PMOS pipe MP2, and its drain electrode links to each other with the drain electrode of the 5th NMOS pipe MN5 and consists of output signal O
2Be connected to the input of the first logic inverter INV1;
The 4th PMOS pipe MP4 and the 6th NMOS pipe MN6 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit 1, and input is connected to the second output that the PMOS substrate is selected circuit 1, and output is connected to the grid of the 5th PMOS pipe MP5;
The 5th PMOS manages MP5, and its grid is connected to the drain electrode of the 4th PMOS pipe MP4, and is connected to the drain electrode of the 6th NMOS pipe MN6, and its source electrode is connected to the first input end that the PMOS substrate is selected circuit 1, and its drain electrode is connected to the first output that the PMOS substrate is selected circuit 1;
The 6th PMOS manages MP6, and its grid is connected to the drain electrode of the 7th PMOS pipe MP7, and is connected to the drain electrode of the 7th NMOS pipe MN7, and its source electrode is connected to the second input that the PMOS substrate is selected circuit 1, and its drain electrode is connected to the first output that the PMOS substrate is selected circuit 1;
The 7th PMOS pipe MP7 and the 7th NMOS pipe MN7 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit 1, and input is connected to the grid of the 5th PMOS pipe MP5, and output is connected to the grid of the 6th PMOS pipe MP6;
The 8th PMOS pipe MP8, the 9th PMOS pipe MP9 and the tenth PMOS pipe MP10 consist of cascaded structure, their grid links to each other and is connected to the drain electrode that the tenth PMOS manages MP10, the drain electrode of the tenth PMOS pipe MP10 links to each other with grid and is connected to the source electrode that a PMOS manages MP1, and the source electrode of the 8th PMOS pipe is selected the first input end of circuit 1 as the PMOS substrate;
The one NMOS pipe MN1, the 4th NMOS pipe MN4 and the 5th NMOS pipe MN5, their source electrode altogether, and grid links to each other and consists of active electric current mirror structure, and their drain electrode is connected respectively to the output of current source I1, the drain electrode of the 2nd PMOS pipe MP2 and the drain electrode of the 3rd PMOS pipe MP3;
The 2nd NMOS manages MN2, and its source electrode is connected to the drain electrode of the 3rd NMOS pipe MN3, and its grid is connected to the grid of NMOS pipe MN1, and its drain electrode links to each other with the drain electrode of PMOS pipe MP1;
The 3rd NMOS manages MN3, its source ground, and its drain electrode links to each other with the source electrode of the 2nd NMOS pipe MN2, and its grid is connected with the output of the first logic inverter INV1, consists of sluggish feedback control loop;
The first logic inverter INV1 and the second logic inverter INV2 consist of series connection structure, and the input of the first logic inverter INV1 is connected to output node O
2, the output of the first logic inverter INV1 is connected to the input of the second logic inverter INV2 and the grid of the 3rd NMOS pipe MN3, and the output of the second logic inverter INV2 is selected the second output of circuit 1 as the PMOS substrate;
The output of current source I1 is connected to the drain electrode of NMOS pipe MN1, selects circuit 1 for the PMOS substrate bias current is provided.
Described PMOS ON-OFF control circuit 5, as shown in Figure 7, it comprises diode D1, the first K switch 1, second switch K2, current source I0, the first logic inverter INV1 and the second logic inverter INV2;
Diode D1, its forward end are connected to the first output that the PMOS substrate is selected circuit 1, and its negative end is connected to the d end of second switch K2;
The first K switch 1, one end c is connected to the input of current source I0, and other end a links to each other with the f end of second switch K2, and is connected to the output of PMOS ON-OFF control circuit 5, is used for controlling high-end PMOS pipe P
HConducting and turn-off speed, its control end b is connected to the output of the second not gate INV2;
Second switch K2, one end d is connected to the negative end of diode D1, and other end f links to each other with a end of the first K switch 1, and is connected to the output of PMOS ON-OFF control circuit 5, and control end e is connected to the output of the first logic inverter INV1;
Current source I0, its input is connected output head grounding with the c end of the first logic switch K1;
The first logic inverter INV1, its input is connected to the output of logical signal processing module 4, and its output is connected with the input of the second logic inverter INV2, and is connected to the control end e of second switch K2, conducting and the shutoff of control second switch K2;
The second logic inverter INV2, its input is connected to the output of the first logic inverter INV1, and output links to each other with the control end b of the first K switch 1, controls conducting and the shutoff of the first K switch 1.
Operation principle of the present invention is: in the short-circuit protection circuit of synchronous boost type DC-DC transducer, the PMOS substrate is selected circuit 1, consists of the polygonal mirror main body image tube by PMOS pipe MP1, the 2nd PMOS pipe MP2 and resistance R 1, to output voltage V
OUTWith input voltage V
INCompare, and output comparison signal POK, be used for judging the whether short circuit of synchronous boost type DC-DC transducer, suppose to work as simultaneously output voltage V
OUTGreater than input voltage V
INWhen subtracting 500 millivolts, comparison signal POK is low level, judges that synchronous boost type DC-DC transducer is in normal operating conditions; At this moment, the 5th PMOS pipe MP5 cut-off, the 6th PMOS pipe MP6 conducting is with output signal V
MAXBe pulled to output voltage V
OUTOtherwise judge that synchronous boost type DC-DC transducer is in short-circuit condition, output signal V
MAXBe pulled to input voltage V
INTherefore the PMOS substrate is selected the output signal V of circuit
MAXAll the time be the maximum potential in the circuit, avoid at high-end PMOS pipe P
HWhen carrying out switch motion, high-end PMOS pipe P
HThe conducting of body parasitic diode cause circuit to be damaged so that the SW signal produces very large overshoot.The PMOS substrate selects the comparison signal POK of circuit 1 output to be connected to Hicup logical circuit 2, carries out output overcurrent guard signal ToHicup and counting commencing signal EnHicup after the logical operation with overheat protector signal OTP.Overcurrent protection signal ToHicup is connected to logical signal processing module 4; when it becomes high level; represent that namely chip is in short-circuit condition or over-temperature condition; after carrying out logical process with timing end signal GO; output control signal PI is connected to PMOS ON-OFF control circuit 5, and control circuit 5 output drive signal DRVP control high-end PMOS pipe P
HTurn-off, the short-circuit protection state starts.After the short-circuit protection state starts; counting commencing signal EnHicup is input to counter 3; carry out with enabling signal ON that control counter 3 begins counting after the logical process; synchronous boost type DC-DC transducer quits work and has a rest during the counting, until timing is exported count end signal GO after finishing.Timing end signal GO is connected to logical signal processing module 4, carry out logical process with overcurrent protection signal ToHicup after, output control signal PI is connected to PMOS ON-OFF control circuit 5, control circuit 5 output drive signal DRVP control high-end PMOS pipe P
HOpen.And then judge in the logical signal processing module whether chip still is in short-circuit condition or over-temperature condition, if so, then repeats said process, if not, then synchronous boost type DC-DC transducer begins normal startup after counting finishes.Opening or turn-offing high-end PMOS pipe P
HThe switch motion process in, PMOS ON-OFF control circuit 5 can by control PMOS pipe PM1 consist of on draw diode, the speed of high-end PMOS pipe PH conducting and shutoff is controlled in and conducting and the shutoff of the pull-down current that consists of of current source I0; The little electric current of current source I0, and the diode structure that PMOS pipe PM1 consists of can be so that high-end PMOS pipe P
HConducting slower than traditional short-circuit protection circuit with turn-off speed, thereby avoid because the overshoot phenomenon of the SW signal that causes too rapidly of switch motion prevents that synchronous boost type DC-DC transducer is breakdown.
Below only be two preferred example of the present invention, do not consist of any limitation of the invention, obviously under design of the present invention, can carry out different changes and improvement to its circuit, but these are all at the row of protection of the present invention.
Claims (5)
1. a short-circuit protection circuit that is applied to synchronous boost type DC-DC transducer comprises Hicup logical circuit (2), counter (3), logical signal processing module (4), drive circuit (6) and high-end PMOS pipe P
HThe first output a of Hicup logical circuit (2) is connected to the first input end b of logical signal processing module (4); The second input c of logical signal processing module (4) is connected to the output d of counter (3); The second input e of counter (3) is connected to the second Ausgang of Hicup logical circuit (2), is used for the control short-circuit protection time; The output g of drive circuit (6) is connected to high-end PMOS pipe P
HGrid, be used for controlling high-end PMOS pipe P
HConducting and shutoff; High-end PMOS pipe P
HSource electrode be connected to output pin V
OUT, drain electrode is connected to output pin SW; It is characterized in that:
The first input end h of Hicup logical circuit (2) and high-end PMOS pipe P
HSubstrate between cross-over connection have the PMOS substrate to select circuit (1), be used for judging the whether short circuit of synchronous boost type DC-DC transducer, and be that high-end PMOS manages P
HSubstrate electric potential is provided;
Cross-over connection has PMOS ON-OFF control circuit (5) between the output g of the output i of logical signal processing module (4) and drive circuit (6), is used for controlling high-end PMOS pipe P
HConducting and turn-off speed.
2. short-circuit protection circuit according to claim 1 is characterized in that described PMOS substrate selection circuit (1), comprises seven PMOS pipes, seven NMOS pipes, two logic inverters (INV1, INV2), resistance R 1 and current source I1;
Described PMOS pipe MP1, its grid link to each other with the grid of the 2nd PMOS pipe MP2 and consist of active electric current mirror structure, and its source electrode links to each other with an end of resistance R 1, and its drain electrode links to each other with the drain electrode of the 2nd NMOS pipe MN2;
Described the 2nd PMOS pipe MP2, its drain electrode links to each other with the drain electrode of the 4th NMOS pipe MN4, consists of output signal O
1Be connected to the grid of the 3rd PMOS pipe MP3, its source electrode selects the second input of circuit (1) to link to each other with the PMOS substrate;
Described the 3rd PMOS pipe MP3, its source electrode is as the first input end of PMOS substrate selection circuit (1), and its grid is connected to the drain electrode of the 2nd PMOS pipe MP2, and its drain electrode links to each other with the drain electrode of the 5th NMOS pipe MN5 and consists of output signal O
2Be connected to the input of the first logic inverter INV1;
Described the 4th PMOS pipe MP4 and the 6th NMOS pipe MN6 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit (1), and input is connected to the second output that the PMOS substrate is selected circuit (1), and output is connected to the grid of the 5th PMOS pipe MP5;
Described the 5th PMOS pipe MP5, its grid is connected to the drain electrode of the 4th PMOS pipe MP4, and be connected to the drain electrode that the 6th NMOS manages MN6, and its source electrode is connected to the first input end that the PMOS substrate is selected circuit (1), and its drain electrode is connected to the first output that the PMOS substrate is selected circuit (1);
Described the 6th PMOS pipe MP6, its grid is connected to the drain electrode of the 7th PMOS pipe MP7, and be connected to the drain electrode that the 7th NMOS manages MN7, and its source electrode is connected to the second input that the PMOS substrate is selected circuit (1), and its drain electrode is connected to the first output that the PMOS substrate is selected circuit (1);
Described the 7th PMOS pipe MP7 and the 7th NMOS pipe MN7 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit (1), and input is connected to the grid of the 5th PMOS pipe MP5, and output is connected to the grid of the 6th PMOS pipe MP6;
Described NMOS pipe MN1, the 4th NMOS pipe MN4 and the 5th NMOS pipe MN5, their source electrode altogether, and grid links to each other and consists of active electric current mirror structure, and their drain electrode is connected respectively to the output of current source I1, the drain electrode of the 2nd PMOS pipe MP2 and the drain electrode of the 3rd PMOS pipe MP3;
Described the 2nd NMOS pipe MN2, its source electrode is connected to the drain electrode of the 3rd NMOS pipe MN3, and its grid is connected to the grid of NMOS pipe MN1, and its drain electrode links to each other with the drain electrode of PMOS pipe MP1;
Described the 3rd NMOS pipe MN3, its source ground, its drain electrode links to each other with the source electrode of the 2nd NMOS pipe MN2, and its grid is connected with the output of the first logic inverter INV1, consists of sluggish feedback control loop;
Described the first logic inverter INV1 and the second logic inverter INV2 consist of series connection structure, and the input of the first logic inverter INV1 is connected to output node O
2, the output of the first logic inverter INV1 is connected to the input of the second logic inverter INV2 and the grid of the 3rd NMOS pipe MN3, and the output of the second logic inverter INV2 is selected the second output of circuit (1) as the PMOS substrate;
One end of described resistance R 1 is connected to the source electrode of PMOS pipe MP1, and the other end is connected to first input end;
The output of described current source I1 is connected to the drain electrode of NMOS pipe MN1, selects circuit (1) for the PMOS substrate bias current is provided.
3. short-circuit protection circuit according to claim 1 is characterized in that described PMOS substrate selection circuit (1), comprises ten PMOS pipes, seven NMOS pipes, two logic inverters (INV1, INV2) and current source I1;
Described PMOS pipe MP1, its grid link to each other with the grid of the 2nd PMOS pipe MP2 and consist of active electric current mirror structure, and its source electrode links to each other with the drain electrode of the tenth PMOS pipe MP10, and its drain electrode links to each other with the drain electrode of the 2nd NMOS pipe MN2;
Described the 2nd PMOS pipe MP2, its drain electrode links to each other with the drain electrode of the 4th NMOS pipe MN4, consists of the grid that output signal O1 is connected to the 3rd PMOS pipe MP3, and its source electrode selects the second input of circuit (1) to link to each other with the PMOS substrate;
Described the 3rd PMOS pipe MP3, its source electrode is connected to the first input end that the PMOS substrate is selected circuit (1), and its grid is connected to the drain electrode of the 2nd PMOS pipe MP2, and its drain electrode links to each other with the drain electrode of the 5th NMOS pipe MN5 and consists of output signal O
2Be connected to the input of the first logic inverter INV1;
Described the 4th PMOS pipe MP4 and the 6th NMOS pipe MN6 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit (1), and input is connected to the second output that the PMOS substrate is selected circuit (1), and output is connected to the grid of the 5th PMOS pipe MP5;
Described the 5th PMOS pipe MP5, its grid is connected to the drain electrode of the 4th PMOS pipe MP4, and be connected to the drain electrode that the 6th NMOS manages MN6, and its source electrode is connected to the first input end that the PMOS substrate is selected circuit (1), and its drain electrode is connected to the first output that the PMOS substrate is selected circuit (1);
Described the 6th PMOS pipe MP6, its grid is connected to the drain electrode of the 7th PMOS pipe MP7, and be connected to the drain electrode that the 7th NMOS manages MN7, and its source electrode is connected to the second input that the PMOS substrate is selected circuit (1), and its drain electrode is connected to the first output that the PMOS substrate is selected circuit (1);
Described the 7th PMOS pipe MP7 and the 7th NMOS pipe MN7 connect into non-door; The low level ground connection of non-door, high level are connected to the first output that the PMOS substrate is selected circuit (1), and input is connected to the grid of the 5th PMOS pipe MP5, and output is connected to the grid of the 6th PMOS pipe MP6;
Described the 8th PMOS pipe MP8, the 9th PMOS pipe MP9 and the tenth PMOS pipe MP10 consist of cascaded structure, their grid links to each other and is connected to the drain electrode that the tenth PMOS manages MP10, the drain electrode of the tenth PMOS pipe MP10 links to each other with grid and is connected to the source electrode that a PMOS manages MP1, and the source electrode of the 8th PMOS pipe is selected the first input end of circuit (1) as the PMOS substrate;
Described NMOS pipe MN1, the 4th NMOS pipe MN4 and the 5th NMOS pipe MN5, their source electrode altogether, and grid links to each other and consists of active electric current mirror structure, and their drain electrode is connected respectively to the output of current source I1, the drain electrode of the 2nd PMOS pipe MP2 and the drain electrode of the 3rd PMOS pipe MP3;
Described the 2nd NMOS pipe MN2, its source electrode is connected to the drain electrode of the 3rd NMOS pipe MN3, and its grid is connected to the grid of NMOS pipe MN1, and its drain electrode links to each other with the drain electrode of PMOS pipe MP1;
Described the 3rd NMOS pipe MN3, its source ground, its drain electrode links to each other with the source electrode of the 2nd NMOS pipe MN2, and its grid is connected with the output of the first logic inverter INV1, consists of sluggish feedback control loop;
Described the first logic inverter INV1 and the second logic inverter INV2 consist of series connection structure, and the input of the first logic inverter INV1 is connected to output node O
2, the output of the first logic inverter INV1 is connected to the input of the second logic inverter INV2 and the grid of the 3rd NMOS pipe MN3, and the output of the second logic inverter INV2 is selected the second output of circuit (1) as the PMOS substrate;
The output of described current source I1 is connected to the drain electrode of NMOS pipe MN1, selects circuit (1) for the PMOS substrate bias current is provided.
4. short-circuit protection circuit according to claim 1 is characterized in that PMOS ON-OFF control circuit (5), comprises PMOS pipe PM1, two switches (K1, K2), current source I0 and two logic inverters (INV1, INV2);
Described PMOS pipe PM1, its source electrode is connected to the first output that the PMOS substrate is selected circuit (1), and its grid links to each other with drain electrode, and is connected to the d end of second switch K2;
Described the first K switch 1, one end c is connected to the input of current source I0, other end a links to each other with the f end of second switch K2, and be connected to the output of PMOS ON-OFF control circuit (5), be used for controlling conducting and the turn-off speed of high-end PMOS pipe PH, its control end b is connected to the output of the second not gate INV2;
Described second switch K2, one end d are connected to the drain electrode of PMOS pipe PM1, and other end f links to each other with a end of the first K switch 1, and is connected to the output of PMOS ON-OFF control circuit (5), and control end e is connected to the output of the first logic inverter INV1;
Described current source I0, its input is connected output head grounding with the c end of the first logic switch K1;
Described the first logic inverter INV1, its input is connected to the output of logical signal processing module (4), its output is connected with the input of the second logic inverter INV2, and is connected to the control end e of second switch K2, conducting and the shutoff of control second switch K2;
Described the second logic inverter INV2, its input is connected to the output of the first logic inverter INV1, and output links to each other with the control end b of the first K switch 1, controls conducting and the shutoff of the first K switch 1.
5. short-circuit protection circuit according to claim 1 is characterized in that PMOS ON-OFF control circuit (5), comprises diode D1, two switches (K1, K2), current source I0 and two logic inverters (INV1, INV2);
Described diode D1, its forward end are connected to the first output that the PMOS substrate is selected circuit (1), and its negative end is connected to the d end of second switch K2;
Described the first K switch 1, one end c is connected to the input of current source I0, and other end a links to each other with the f end of second switch K2, and is connected to the output of PMOS ON-OFF control circuit (5), is used for controlling high-end PMOS pipe P
HConducting and turn-off speed, its control end b is connected to the output of the second not gate INV2;
Described second switch K2, one end d is connected to the negative end of diode D1, and other end f links to each other with a end of the first K switch 1, and is connected to the output of PMOS ON-OFF control circuit (5), and control end e is connected to the output of the first logic inverter INV1;
Described current source I0, its input is connected output head grounding with the c end of the first logic switch K1;
Described the first logic inverter INV1, its input is connected to the output of logical signal processing module (4), its output is connected with the input of the second logic inverter INV2, and is connected to the control end e of second switch K2, conducting and the shutoff of control second switch K2;
Described the second logic inverter INV2, its input is connected to the output of the first logic inverter INV1, and output links to each other with the control end b of the first K switch 1, controls conducting and the shutoff of the first K switch 1.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210470791.5A CN103001475B (en) | 2012-11-19 | 2012-11-19 | Short-circuit protecting circuit applied to synchronous boost type direct current-direct current (DC-DC) converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210470791.5A CN103001475B (en) | 2012-11-19 | 2012-11-19 | Short-circuit protecting circuit applied to synchronous boost type direct current-direct current (DC-DC) converter |
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| CN108847654A (en) * | 2018-06-26 | 2018-11-20 | 南京微盟电子有限公司 | A kind of shutdown of PFM synchronous boost DC-DC converter and protection circuit |
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| CN113965195A (en) * | 2021-12-22 | 2022-01-21 | 芯昇科技有限公司 | Universal input/output interface anti-creeping circuit, chip and electronic equipment |
| CN115167598A (en) * | 2022-07-26 | 2022-10-11 | 圣邦微电子(苏州)有限责任公司 | Power supply voltage selection circuit |
| CN115167598B (en) * | 2022-07-26 | 2024-03-15 | 圣邦微电子(苏州)有限责任公司 | Power supply voltage selection circuit |
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Address after: Room 308, 3 / F, information port building, No.9, Gaoxin Third Road, hi tech Zone, Xi'an City, Shaanxi Province Patentee after: Xi'an Jie Semiconductor Co.,Ltd. Address before: High road high tech Zone of Xi'an City, Shaanxi province 710075 Xi'an City No. 33 new Department building block B room 2203 Patentee before: XI'AN SANYU SEMICONDUCTOR Co.,Ltd. |