CN107579064B - Stacked electrostatic discharge protection circuit - Google Patents
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Abstract
The invention discloses a stacked electrostatic discharge protection circuit, which comprises a power supply module, a first bias module, a second bias module, a first control module, a second control module, a first driving module, a second driving module and an M driving module, the first large transistor and the second large transistor are used for outputting a driving signal by the control module until the Mth large transistor is reached when the control module detects a positive ESD event, the driving module at the same level with the control module receives the driving signal and then controls the large transistors at the same level to be conducted so as to discharge ESD current, and the power module directly supplies power to each driving module respectively. In the invention, each large transistor has high starting speed, ensures that the stacked electrostatic discharge protection circuit can rapidly respond to an ESD event, increases the gate driving voltage of each large transistor, reduces the on-resistance, improves the ESD current discharging capability, and further improves the reliability of the chip.
Description
Technical Field
The present invention relates to the field of electronic devices, and in particular, to a stacked electrostatic discharge protection circuit.
Background
ESD (Electro Static Discharge ) events can have damaging consequences for the electronic device, which is a major cause of chip failure, and in order to improve the reliability of the chip, a technician typically designs an ESD protection circuit to prevent the internal circuitry of the chip from being damaged. The ESD protection circuit can be divided into an input/output protection circuit and a power ground (V DD -to-V SS ) The protection circuit, wherein the power ground protection circuit can provide an electrostatic discharge path, plays an important role in protecting the internal circuit of the chip, and in order to meet the voltage-withstanding requirement of the internal device of the chip, the design of the power ground protection circuit is generally carried out by combining the stacking technology.
Referring to fig. 1, a conventional power ground esd protection circuit is formed by stacking two-stage RC-triggered power ground protection circuits, and is formed in a power module V DD And ground V SS Each RC trigger power ground protection circuit comprises a bias module, a control module, a driving module and a large transistor, wherein the power end of the driving module is connected with the power module, the bias voltage end of the driving module is connected with the power end of the driving module of the next RC trigger power ground protection circuit and the output end of the bias module, the input end of the driving module is connected with the control voltage end of the control module, and the output end of the driving module is connected with the large transistorThe gates of the transistors are connected. When a positive ESD event occurs on the power module, the control module controls the driving module of the same stage to drive the large transistor of the same stage to start so as to discharge the ESD current, and the ESD current is discharged from V DD Flow direction V SS The electrostatic discharge path is composed of a first large transistor and a second large transistor, at the moment, the starting speed of the second large transistor at the bottom is limited by the bias voltage output by the bias module at the same level, which is started slowly, and meanwhile, the power module can uniformly supply power to the two-stage driving module, so that the grid driving voltage of the first large transistor and the grid driving voltage of the second large transistor can be reduced, further, the on-resistance of the first large transistor and the on-resistance of the second large transistor are larger at the moment, the ESD current discharge is hindered, and even the internal circuit of the chip can be possibly damaged.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The invention aims to provide a stacked electrostatic discharge protection circuit, when a positive ESD event occurs, a power supply module directly supplies power to M driving modules respectively, the starting of each large transistor is not limited by the driving modules, the starting speed is higher, the stacked electrostatic discharge protection circuit can be ensured to rapidly correspond to the ESD event, meanwhile, the gate driving voltage of each large transistor is increased, the on-resistance is reduced, the ESD current discharging capacity is improved, and the reliability of a chip is further improved.
In order to solve the technical problems, the invention provides a stacked electrostatic discharge protection circuit, which comprises a power supply module, a first bias module, a second bias module, a first control module, a second control module, a first driving module, a second driving module and an Mth driving module, the first large transistor, the second large transistor and the Mth large transistor, M is an integer not less than 2, wherein:
the power supply end of the first driving module is respectively connected with the power supply module and the drain electrode of the first large transistor, the output end of each driving module is connected with the grid electrode of the large transistor at the same level, the output end of each driving module except for the Mth driving module is also connected with the power supply end of the driving module at the next level, the source electrode of each large transistor except for the Mth large transistor is connected with the drain electrode of the large transistor at the next level, the source electrode of the Mth large transistor is respectively connected with the ground and the bias voltage end of the Mth control module, and the power supply module is used for respectively supplying power to M driving modules directly when positive ESD events occur;
and the bias voltage end of each driving module is connected with the output end of the bias module at the same level, and the input end of each driving module is connected with the control voltage end of the control module at the same level, so that when the control module detects a positive ESD event, a driving signal is output, and the driving module at the same level with the control module receives the driving signal and controls the large transistor at the same level to be conducted so as to discharge the ESD current.
Preferably, each driving module includes a first inverter, a second inverter, and up to an nth inverter connected in series in sequence, each of the inverters includes a first transistor and a second transistor, and N is an odd number, where:
the grid electrode of the first transistor is connected with the grid electrode of the second transistor, the common end of the grid electrode of the first transistor is used as the input end of the inverter, the drain electrode of the first transistor is connected with the drain electrode of the second transistor, the common end of the grid electrode of the first transistor is used as the output end of the inverter, the output end of each inverter except the N-th inverter is connected with the input end of the adjacent inverter, the output end of the N-th inverter is used as the output end of the driving module where the N-th inverter is located, the sources of the N-th second transistors are connected with each other, the common end of the N-th inverter is used as the bias voltage end of the driving module where the N-th inverter is located, the sources of the N-th first transistors are connected with each other, the common end of the N-th inverter is used as the power end of the driving module where the N-th inverter is located, and the input end of the first inverter is used as the input end of the driving module where the N-th inverter is located.
Preferably, each control module includes a capacitor, a first end of the capacitor in each control module except the first control module is connected with an output end of a bias module at a previous stage of the control module where the first end is located, and meanwhile, as a control voltage end of the control module where the first end is located, a second end of the capacitor in each control module except the mth control module is connected with an output end of a bias module at a same stage, and an output end of the mth control module is connected with ground;
the first control module further comprises a resistor, a first end of the resistor is connected with a first end of a capacitor in the first control module, a common end of the resistor is used as a control voltage end of the first control module, and a second end of the resistor is connected with the power supply module.
Preferably, the input end of the first bias module is connected with the power module, the output end of each bias module except the mth bias module is connected with the input end of the next stage bias module, and the output end of the mth bias module is connected with the ground.
Preferably, the large transistor is an NMOS transistor.
Preferably, the large transistor is a bipolar transistor.
Preferably, the first transistor is a PMOS transistor.
Preferably, the second transistor is an NMOS transistor.
The invention provides a stacked electrostatic discharge protection circuit, which is used for outputting a driving signal by a control module when the control module detects a positive ESD event, and controlling the large transistor of the same level to be conducted after the driving signal is received by the driving module of the same level of the control module so as to discharge ESD current, wherein the power module directly supplies power to each driving module respectively. In the invention, each large transistor has high starting speed, ensures that the stacked electrostatic discharge protection circuit can rapidly respond to an ESD event, increases the gate driving voltage of each large transistor, reduces the on-resistance, improves the ESD current discharging capability, and further improves the reliability of the chip.
Therefore, in practical application, when the stacked electrostatic discharge protection circuit provided by the invention has a positive ESD event, the power supply module directly supplies power to the M driving modules respectively, so that the starting of each large transistor is not limited by the driving modules, the starting speed is higher, the stacked electrostatic discharge protection circuit can rapidly respond to the ESD event, meanwhile, the grid driving voltage of each large transistor is increased, the on-resistance is reduced, the ESD current discharging capability is improved, and the reliability of the chip is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional two-stage stacked ESD protection circuit;
FIG. 2 is a schematic diagram of a stacked ESD protection circuit according to the present invention;
fig. 3 is a schematic diagram of another structure of a stacked esd protection circuit according to the present invention.
Detailed Description
The core of the invention is to provide a stacked electrostatic discharge protection circuit, when a positive ESD event occurs, a power module directly supplies power to M driving modules respectively, the starting of each large transistor is not limited by the driving modules, the starting speed is higher, the stacked electrostatic discharge protection circuit can be ensured to rapidly correspond to the ESD event, meanwhile, the gate driving voltage of each large transistor is increased, the on-resistance is reduced, the ESD current discharging capacity is improved, and the reliability of a chip is further improved.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a stacked esd protection circuit provided by the present invention, including a power module 1, a first bias module 21, a second bias module 22, up to an mth bias module 2M, a first control module 31, a second control module 32, up to an mth control module 3M, a first driving module 41, a second driving module 42, up to an mth driving module 4M, a first large transistor 51, a second large transistor 52, up to an mth large transistor 5M, M being an integer not smaller than 2, wherein:
the power end of the first driving module 41 is respectively connected with the power module 1 and the drain electrode of the first large transistor 51, the output end of each driving module is connected with the grid electrode of the large transistor of the same level, the output end of each driving module except for the Mth driving module 4M is also connected with the power end of the driving module of the next level, the source electrode of each large transistor except for the Mth large transistor 5M is connected with the drain electrode of the large transistor of the next level, the source electrode of the Mth large transistor 5M is respectively connected with the ground and the bias voltage end of the Mth control module 3M, and the power module 1 is used for directly supplying power to the M driving modules when positive ESD events occur;
the bias voltage end of each driving module is connected with the output end of the bias module at the same level, the input end of each driving module is connected with the control voltage end of the control module at the same level, and the driving module at the same level is used for outputting a driving signal when the control module detects that a positive ESD event exists, and the driving module at the same level with the control module receives the driving signal and controls the large transistor at the same level to be conducted so as to discharge the ESD current.
Specifically, when the detection module detects that a positive ESD event occurs in the circuit, a driving signal is output, and the driving module controls the large transistor of the same level to be conducted after receiving the driving signal, and discharges the ESD current. Specifically, the power module 1 supplies power to the driving module, so that the driving module can work normally, and by adopting the design scheme of the stacked electrostatic discharge protection circuit, the driving module of each stage can be ensured to be powered by the power module 1, so that the large transistor at the bottom of the stacked structure can be rapidly conducted, the electrostatic discharge protection circuit can rapidly respond to an ESD event, meanwhile, the gate driving voltage of each large transistor is increased, the on-resistance is reduced, and the current discharging capacity of each large transistor is improved.
The invention discloses a stacked electrostatic discharge protection circuit, which is used for outputting a driving signal by a control module when the control module detects a positive ESD event, and controlling the large transistor of the same level to be conducted after the driving signal is received by the driving module of the same level of the control module so as to discharge ESD current, wherein the power module directly supplies power to each driving module respectively. In the invention, each large transistor has high starting speed, ensures that the stacked electrostatic discharge protection circuit can rapidly respond to an ESD event, increases the gate driving voltage of each large transistor, reduces the on-resistance, improves the ESD current discharging capability, and further improves the reliability of the chip.
Therefore, in practical application, when the stacked electrostatic discharge protection circuit provided by the invention has a positive ESD event, the power supply module directly supplies power to the M driving modules respectively, so that the starting of each large transistor is not limited by the driving modules, the starting speed is higher, the stacked electrostatic discharge protection circuit can rapidly respond to the ESD event, meanwhile, the grid driving voltage of each large transistor is increased, the on-resistance is reduced, the ESD current discharging capability is improved, and the reliability of the chip is further improved.
Referring to fig. 3, fig. 3 is a schematic diagram of another structure of a stacked esd protection circuit according to the present invention, wherein the stacked esd protection circuit is based on the above embodiments:
as a preferred embodiment, each driving module includes a first inverter, a second inverter, and up to an nth inverter connected in series, each inverter including a first transistor and a second transistor, N being an odd number, wherein:
the grid electrode of the first transistor is connected with the grid electrode of the second transistor, the common end of the first transistor is used as the input end of the inverter, the drain electrode of the first transistor is connected with the drain electrode of the second transistor, the common end of the first transistor is used as the output end of the inverter, the output end of each inverter except for the N-th inverter is connected with the input end of the adjacent inverter, the output end of the N-th inverter is used as the output end of the driving module where the N-th inverter is located, the source electrodes of the N-th second transistors are connected with each other, the common end of the N-th second transistors is used as the bias voltage end of the driving module where the N-th second transistors are located, the source electrodes of the N-th first transistors are connected with each other, the common end of the N-th transistor is used as the power end of the driving module where the N-th inverter is located, and the input end of the first inverter is used as the input end of the driving module where the N-th inverter is located.
Specifically, when no ESD event occurs, the control voltage end of the control module is low, and when a positive ESD event occurs, the ESD voltage has a fast rising speed, and the control voltage of the control module cannot keep up with the rising speed of the ESD voltage due to the delay effect of the control module, so that the output voltage end of the control module is low, that is, the input end of the driving module is low, after the output end of the driving module passes through the odd number of inverters, that is, the grid electrode of the large transistor connected with the output end of the driving module is high, at this time, the large transistor is turned on, and the ESD current is discharged, wherein the power supply end of each driving module is provided with the power supply voltage by the power supply module 1, so that the starting speed of the first transistor of the inverter is fast, the bias voltage end of each driving module is provided with the power supply voltage by the bias module, and the first transistor and the second transistor of each inverter alternately work, so that each inverter in the driving module is in a normal working state, and the stacked electrostatic discharge protection circuit provided by the invention can rapidly respond to the ESD event.
As a preferred embodiment, each control module includes a capacitor, a first end of the capacitor in each other control module except the first control module 31 is connected to an output end of a bias module at a previous stage of the control module where the first end is located, and a second end of the capacitor in each other control module except the mth control module 3M is connected to an output end of a bias module at a same stage as a control voltage end of the control module where the first end is located, and an output end of the mth control module 3M is connected to ground;
the first control module 31 further includes a resistor, a first end of the resistor is connected to a first end of a capacitor in the first control module 31, a common end of the resistor is used as a control voltage end of the first control module 31, and a second end of the resistor is connected to the power module 1.
Specifically, the starting speed of the large transistors except the large transistor positioned at the top of the stack is influenced by the bias module, so that in order to ensure that all ESD current can be discharged, the turn-on time of the large transistor is longer, the turn-on time of the large transistor is limited by the delay time of the control module, and the control module needs a large resistor and capacitor to ensure the delay time of the large transistor, thereby increasing the design cost.
As a preferred embodiment, the input terminal of the first bias module 21 is connected to the power module 1, and the output terminal of each bias module except the mth bias module 2M is connected to the input terminal of the next bias module, and the output terminal of the mth bias module 2M is connected to ground.
Specifically, the bias module consists of a plurality of transistors with short-circuited gates and drains, and provides bias voltage for bias voltage ends of the driving modules, so that the inverters in the driving modules are in a normal working state, and the stacked electrostatic discharge protection circuit provided by the invention can rapidly respond to an ESD event.
Of course, the bias module may be composed of a plurality of transistors with short-circuited gates and drains, and may be composed of different devices by using different connection methods, which is not limited herein.
As a preferred embodiment, the large transistor is an NMOS transistor.
Specifically, the NMOS tube is an N-channel MOS tube, has high input impedance, obvious buffering effect, small area, simple manufacturing process and lower cost, and can further improve the current discharge capacity on the premise of not increasing the area of the chip.
Of course, the large transistor may be other than an NMOS transistor, and the present invention is not limited herein.
As a preferred embodiment, the large transistor is a bipolar transistor.
Specifically, the bipolar transistor has the characteristics of small volume, light weight, long service life and the like, reduces layout area to a certain extent, and saves cost.
Of course, the large transistor may be other than an NMOS transistor, and the present invention is not limited herein.
As a preferred embodiment, the first transistor is a PMOS transistor.
Specifically, the PMOS transistor is a P-channel MOS transistor, the process is simple, the price is low, and the design cost is saved.
Of course, the first transistor may be other transistors besides PMOS transistors, which is not limited herein.
As a preferred embodiment, the second transistor is an NMOS transistor.
Specifically, the NMOS tube is an N-type MOS tube, has high input impedance, obvious driving effect, small area, simple manufacturing process and lower cost, further ensures that the area of a chip is not increased, and reduces the cost.
Of course, the second transistor may be other transistors besides an NMOS transistor, which is not limited herein.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. The utility model provides a stacked electrostatic discharge protection circuit which characterized in that, including power module, first biasing module, second biasing module until the Mth biasing module, first control module, second control module until the Mth control module, first drive module, second drive module until the Mth drive module, first big transistor, second big transistor until the Mth big transistor, M is not less than 2 integers, wherein:
the power supply end of the first driving module is respectively connected with the power supply module and the drain electrode of the first large transistor, the output end of each driving module is connected with the grid electrode of the large transistor at the same level, the output end of each driving module except for the Mth driving module is also connected with the power supply end of the driving module at the next level, the source electrode of each large transistor except for the Mth large transistor is connected with the drain electrode of the large transistor at the next level, the source electrode of the Mth large transistor is respectively connected with the ground and the bias voltage end of the Mth control module, and the power supply module is used for respectively supplying power to M driving modules directly when positive ESD events occur;
and the bias voltage end of each driving module is connected with the output end of the bias module at the same level, and the input end of each driving module is connected with the control voltage end of the control module at the same level, so that when the control module detects a positive ESD event, a driving signal is output, and the driving module at the same level with the control module receives the driving signal and controls the large transistor at the same level to be conducted so as to discharge the ESD current.
2. The stacked electrostatic discharge protection circuit of claim 1, wherein each drive module comprises a first inverter, a second inverter, and up to an nth inverter in series, each of the inverters comprising a first transistor and a second transistor, N being an odd number, wherein:
the grid electrode of the first transistor is connected with the grid electrode of the second transistor, the common end of the grid electrode of the first transistor is used as the input end of the inverter, the drain electrode of the first transistor is connected with the drain electrode of the second transistor, the common end of the grid electrode of the first transistor is used as the output end of the inverter, the output end of each inverter except the N-th inverter is connected with the input end of the adjacent inverter, the output end of the N-th inverter is used as the output end of the driving module where the N-th inverter is located, the sources of the N-th second transistors are connected with each other, the common end of the N-th inverter is used as the bias voltage end of the driving module where the N-th inverter is located, the sources of the N-th first transistors are connected with each other, the common end of the N-th inverter is used as the power end of the driving module where the N-th inverter is located, and the input end of the first inverter is used as the input end of the driving module where the N-th inverter is located.
3. The stacked electrostatic discharge protection circuit of claim 1, wherein each control module includes a capacitor, a first end of the capacitor in each of the other control modules except the first control module is connected to an output end of a bias module at a previous stage of the control module where the first control module is located, and a second end of the capacitor in each of the other control modules except the mth control module is connected to an output end of a bias module at a same stage as a control voltage end of the control module where the first control module is located, and an output end of the mth control module is connected to ground;
the first control module further comprises a resistor, a first end of the resistor is connected with a first end of a capacitor in the first control module, a common end of the resistor is used as a control voltage end of the first control module, and a second end of the resistor is connected with the power supply module.
4. The stacked electrostatic discharge protection circuit of claim 1, wherein an input of the first bias module is connected to a power module, an output of each of the bias modules except the mth bias module is connected to an input of a next stage bias module, and an output of the mth bias module is connected to ground.
5. The stacked electrostatic discharge protection circuit of any one of claims 1-4, wherein the large transistor is an NMOS transistor.
6. The stacked electrostatic discharge protection circuit of claim 5, wherein the large transistor is a bipolar transistor.
7. The stacked electrostatic discharge protection circuit of claim 2, wherein the first transistor is a PMOS transistor.
8. The stacked electrostatic discharge protection circuit of claim 2, wherein the second transistor is an NMOS transistor.
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| US10886729B2 (en) * | 2017-06-01 | 2021-01-05 | Richwave Technology Corp. | Electrostatic discharge protection device for high supply voltage operations |
| US11289472B2 (en) * | 2020-07-30 | 2022-03-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with electrostatic discharge protection |
| CN114582282B (en) * | 2022-03-30 | 2023-07-25 | 武汉华星光电半导体显示技术有限公司 | ESD protection circuit and display device |
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