CN104283201A - Input stage esd protection circuit - Google Patents
Input stage esd protection circuit Download PDFInfo
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- CN104283201A CN104283201A CN201410461667.1A CN201410461667A CN104283201A CN 104283201 A CN104283201 A CN 104283201A CN 201410461667 A CN201410461667 A CN 201410461667A CN 104283201 A CN104283201 A CN 104283201A
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Abstract
The invention discloses an input stage ESD protection circuit which comprises a power source clamp ESD protection circuit, a ballast module, a transmission gate module, a phase inverter driving module and a diode module. According to the input stage ESD protection circuit, existing detection signal resources in the power source clamp ESD protection circuit are reasonably utilized, the transmission gate module and the ballast module are synchronous driven, it is effectively achieved that electrostatic charges are released through a designed releasing channel under the worst ESD impact situation, the undamped transmission of data is ensured when a chip is normally operated, and meanwhile it is ensured that the additional domain overhead brought to the chip by the ESD protection design is quite small.
Description
Technical field
The present invention relates to integrated circuit electrostatic discharge resist technology field, more specifically relate to a kind of input stage esd protection circuit.
Background technology
Static discharge (Electronic Static Discharge, ESD) phenomenon is physical phenomenon common in daily life, when removing the object contacting other low-resistance after the object with electric charge removes touching chip pin or chip oneself brings electrostatic, electric charge can shift between not iso-electric object.The transfer process of electric charge is the process of transient high-current, and for integrated circuit (IC) chip, the transient high-current pulse brought by esd event usually can cause the inefficacy of semiconductor device in chip.Be no matter the ESD impact of any pattern, its instantaneous peak current can reach several even magnitude of tens of amperes, greatly exceed the electric current normal range of operation of semiconductor device in integrated circuit.
For chip provides ESD protection on sheet to be the Focal point and difficult point of semiconductor industry about reliability design; the esd protection policy mandates of full chip is for the forward between any pin and negative sense ESD impact pattern, and protective circuit can effectively for electrostatic charge provides the path of releasing of low-resistance.Input stage esd protection circuit provides effective charge discharging resisting path mainly for the ESD impact between input pressure welding point pin different from other; because latter linked first functional circuit module of the input pressure welding point of most of chip is input stage inverter; so the gate oxide of protection input stage inverter is the principal concern of input stage esd protection circuit design.
Fig. 1 is the structural representation of input stage esd protection circuit common under traditional handicraft; in Fig. 1; under pressure welding point forward ESD impact over the ground; electrostatic charge to be released to ground by diode D1 and power clamp ESD protective circuit; in the case; the bleeder resistance that charge discharging resisting path flows through is maximum, causes the clamp voltage in pressure welding point maximum, so this situation is the worst case that the design of input stage esd protection circuit faces.In traditional handicraft, because the thickness of gate oxide is thicker, the gate oxide of input stage inverter can bear certain high pressure usually, in addition resistance R in Fig. 1
bto the buffer action between the gate oxide of input stage inverter and pressure welding point, the gate oxide of input stage inverter occurs that under ESD impact the problem of over-voltage breakdown is not very severe.
The progress of technique allows the semiconductor device in integrated circuit do less and less, and correspondingly, its puncture voltage is also more and more less.Under the technique of advanced person; the gate oxide of input stage inverter is when the ESD impact of input generation worst case; often face cause because of overvoltage puncture inefficacy, now, traditional input stage esd protection circuit no longer can the gate oxide of available protecting input stage inverter.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is how when the ESD impact of worst case; input stage esd protection circuit effectively can impact the big current brought by static electricity discharge; the gate oxide of protection input stage inverter is not breakdown; and ensure the undamped transmission of data under normal circumstances, make ESD protect the chip area Least-cost brought simultaneously.
(2) technical scheme
In order to solve the problems of the technologies described above, the invention provides a kind of input stage esd protection circuit, it is characterized in that, comprise diode (led) module, power clamp ESD protective circuit, ballasting module, transmission gate module, inverter drive module;
Described diode (led) module is used for when there is ESD impact between pressure welding point and other chip pin, effectively electrostatic charge is directed to design release on path, when chip normally works, provide data path and power line V
dDbetween isolation;
Described power clamp ESD protective circuit is for detecting described power line V
dDand the over-voltage events that pressure welding point occurs; when there being ESD impact to cause overvoltage phenomenon; described power clamp ESD protective circuit sends useful signal; triggering is released transistor turns; disconnect the electrical connection between pressure welding point and input stage inverter gate oxide, and increase input stage inverter and described power line V
dDbetween contact resistance, guaranteeing that the path of releasing that electrostatic charge passes through to design is released, when not having over-voltage events to be detected, guaranteeing the undamped transmission of data, and ensure that transistor of releasing is in strict off state;
The signal that described inverter drive module is used for providing according to described power clamp ESD protective circuit drives described transmission gate module and described ballasting module, make the transmission gate transistor in two modules when the esd event of worst case occurs, turn off completely, when transfer of data, open completely;
Described ballasting module is used for the drive singal sent according to described inverter drive module, dynamic change input stage inverter PMOS transistor M
psource electrode and described power line V
dDbetween resistance, when an esd event occurs, increase the M of input stage inverter PMOS transistor
psource electrode and described power line V
dDbetween resistance, guarantee that the path of releasing that electrostatic charge passes through to design is released, when chip normal running, significantly reduce input stage inverter PMOS transistor M
psource electrode and described power line V
dDbetween resistance, guarantee that voltage is unattenuated;
Described transmission gate module is used for the drive singal sent according to described inverter drive module, when over-voltage events occurs, electrical connection between the gate oxide of disconnection pressure welding point and input stage inverter, simultaneously, the input voltage of input stage inverter is forced to be biased to zero, when chip normal running, guarantee the normal transmission of data.
Preferably, described power clamp ESD circuit comprises the transistor M that releases
big, resistance R, R
2, diode D
3, D
4, D
5, D
6, PMOS transistor M
p1, nmos pass transistor M
fb, inverter INV4, INV5; The described transistor M that releases
bigfor nmos pass transistor, its grid connects described inverter drive module; One end of described resistance R, described PMOS transistor M
p1source electrode, described in release transistor M
bigdrain electrode all with described power line V
dDconnect; The other end of described resistance R and described diode D
3input, described PMOS transistor M
p1grid, described nmos pass transistor M
fbdrain electrode connect; Described PMOS transistor M
p1drain electrode, described nmos pass transistor M
fbgrid, described resistance R
2one end be all connected with the input of described inverter INV4; The output of described inverter INV4 is connected with the input of described inverter INV5, the output of described inverter INV5 and the described transistor M that releases
biggrid connect, described supply voltage V
dDfor described inverter INV4, INV5 power; Described diode D
3negative electrode and described diode D
4anode connect, described diode D
4negative electrode and described diode D
5anode connect, described diode D
5negative electrode and described diode D
6anode connect, described diode D
6negative electrode, described nmos pass transistor M
fbsource electrode, described resistance R
2the other end, described in release transistor M
bigsource electrode all with described ground wire V
sSconnect.
Preferably, described inverter drive module comprises inverter INV1, INV2, INV3; The described transistor M that releases
biggrid voltage drive through described inverter INV1, INV2, output overvoltage detectable signal ESD; Described overvoltage detectable signal ESD carries out logic reversal through described inverter INV3, exports reverse overvoltage detectable signal ESDX; Pressure welding point voltage is that described inverter INV1, INV2 power, supply voltage V
dDfor described inverter INV3 powers.
Preferably, described ballasting module comprises nmos pass transistor M
nb, PMOS transistor M
pband resistance R
1;
Described nmos pass transistor M
nbgrid driven by described reverse overvoltage detectable signal ESDX, described PMOS transistor M
pbgrid drive by described overvoltage detectable signal ESD; Described nmos pass transistor M
nbdrain electrode, described PMOS transistor M
pbsource electrode, described resistance R
1one end all connect described power line V
dD; Described nmos pass transistor M
nbsource electrode, described PMOS transistor M
pbdrain electrode, described resistance R
1the other end all connect PMOS transistor M in input pole inverter
psource electrode.
Preferably, described transmission gate module comprises PMOS transistor M
pt, nmos pass transistor M
nta, nmos pass transistor M
nt;
Described PMOS transistor M
pt, nmos pass transistor M
ntagrid all drive by described overvoltage detectable signal ESD, described nmos pass transistor M
ntgrid drive by described reverse overvoltage detectable signal ESDX; Described PMOS transistor M
ptsource electrode, described nmos pass transistor M
ntdrain electrode all connect described pressure welding point; Described PMOS transistor M
ptdrain electrode, described nmos pass transistor M
ntsource electrode, described nmos pass transistor M
ntadrain electrode all connect the input of described input stage inverter; Described nmos pass transistor M
ntasource ground.
Preferably, described inverter INV1, INV2, INV3, INV4, INV5 are CMOS inverter.
(3) beneficial effect
The invention provides a kind of input stage esd protection circuit; by detectable signal resource existing in Appropriate application power clamp ESD protective circuit; synchronously transmission gate module and ballasting module are driven; effectively achieve in the worst ESD impact situation; electrostatic charge is released by the path of releasing designed, and when chip normal running, ensures the undamped transmission of data; meanwhile, ensure that esd protection designs the extra domain expense brought to chip very little.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of input stage esd protection circuit common in traditional handicraft;
Fig. 2 is the structural representation of input stage esd protection circuit of the present invention;
Fig. 3 is the circuit diagram of input stage esd protection circuit of the present invention;
Fig. 4 is input stage esd protection circuit of the present invention when IN end carries out back stagnant dc sweeps, and IN1 end, overvoltage detectable signal, oppositely overvoltage detectable signal are along with the simulation result schematic diagram that time stagnant scanning voltage changes;
Fig. 5 is chip when normally working, the time dependent simulation result schematic diagram of voltage of IN end, IN1 end, INNER end and overvoltage detectable signal in input stage esd protection circuit of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Following examples for illustration of the present invention, but can not be used for limiting the scope of the invention.
Fig. 2 is the structural representation of input stage esd protection circuit of the present invention, and described input stage esd protection circuit comprises diode (led) module, power clamp ESD protective circuit, ballasting module, transmission gate module, inverter drive module.
Described diode (led) module is used for when there is ESD impact between pressure welding point and other chip pin, effectively electrostatic charge is directed to design release on path, when chip normally works, provide data path and power line V
dDbetween isolation.
Described power clamp ESD protective circuit is for detecting described power line V
dDand the over-voltage events that pressure welding point occurs; when there being ESD impact to cause overvoltage phenomenon; power clamp ESD protective circuit sends useful signal; triggering is released transistor turns; disconnect the electrical connection between pressure welding point and input stage inverter gate oxide, and increase input stage inverter and described power line V
dDbetween contact resistance, guaranteeing that the path of releasing that electrostatic charge passes through to design is released, when not having over-voltage events to be detected, guaranteeing the undamped transmission of data, and ensure that transistor of releasing is in strict off state.
The signal that described inverter drive module is used for providing according to power clamp ESD protective circuit drives transmission gate module and ballasting module; make the transmission gate transistor in two modules when the esd event of worst case occurs; turn off completely, when transfer of data, open completely.
Described ballasting module is used for the drive singal sent according to inverter drive module, dynamic change input stage inverter PMOS transistor M
psource electrode and described V
dDbetween resistance, when an esd event occurs, increase the M of input stage inverter PMOS transistor
psource electrode and described power line V
dDbetween resistance, guarantee that the path of releasing that electrostatic charge passes through to design is released, when chip normal running, significantly reduce input stage inverter PMOS transistor M
psource electrode and described power line V
dDbetween resistance, guarantee that voltage is unattenuated.
Described transmission gate module is used for the drive singal sent according to inverter drive module, when over-voltage events occurs, electrical connection between the gate oxide of disconnection pressure welding point and input stage inverter, simultaneously, the input voltage of input stage inverter is forced to be biased to zero, when chip normal running, guarantee the normal transmission of data.
Input stage esd protection circuit provided by the invention; by detectable signal resource existing in Appropriate application power clamp ESD protective circuit; synchronously transmission gate module and ballasting module are driven; effectively achieve in the worst ESD impact situation; electrostatic charge is released by the path of releasing designed, and when chip normal running, ensures the undamped transmission of data; meanwhile, ensure that esd protection designs the extra domain expense brought to chip very little.
Fig. 3 is the circuit diagram of input stage esd protection circuit of the present invention; Described diode (led) module comprises diode D
1, diode and D
2.Described diode D
1anode be connected with the pressure welding point of described input stage esd protection circuit, described diode D
1negative electrode and the described power line V of described input stage esd protection circuit
dDbe connected.Described diode D
2anode and the described ground wire V of described input stage esd protection circuit
sSbe connected, described diode D
2negative electrode be connected with the pressure welding point of described input stage esd protection circuit.
Described power clamp ESD circuit comprises the transistor M that releases
big, resistance R, R
2, diode D
3, D
4, D
5, D
6, PMOS transistor M
p1, nmos pass transistor M
fb, inverter INV4, INV5; The described transistor M that releases released on path
bigfor nmos pass transistor, its grid connects described inverter drive module.One end of described resistance R, described PMOS transistor M
p1source electrode, described in release transistor M
bigdrain electrode all with described power line V
dDconnect; The other end of described resistance R and the input of described diode D3, described PMOS transistor M
p1grid, described nmos pass transistor M
fbdrain electrode connect; Described PMOS transistor M
p1drain electrode, described nmos pass transistor M
fbgrid, described resistance R
2one end be all connected with the input of described inverter INV4; The output of described inverter INV4 is connected with the input of described inverter INV5, the output of described inverter INV5 and the described transistor M that releases
biggrid connect, described supply voltage is that described inverter INV4, INV5 power; Described diode D
3negative electrode and described diode D
4anode connect, described diode D
4negative electrode and described diode D
5anode connect, described diode D
5negative electrode and described diode D
6anode connect, described diode D
6negative electrode, described nmos pass transistor M
fbsource electrode, described resistance R
2the other end, described in release transistor M
bigsource electrode all with described ground wire V
sSconnect.Preferably described inverter INV4, INV5 are CMOS inverter.
Described inverter drive module comprises inverter INV1, INV2, INV3, and release described in the input connection of described inverter INV1 transistor M
biggrid, its output connects the input of described inverter INV2; The output of described inverter INV2 connects described inverter INV3 input, and the output signal of described inverter INV3 is the output signal of reverse overvoltage detectable signal ESDX, described inverter INV2 is overvoltage detectable signal ESD; The voltage of described pressure welding point, namely end points IN voltage is that described inverter INV1, INV2 power; Described supply voltage is that described inverter INV3 powers.Described inverter INV1, INV2, INV3 are preferably CMOS inverter.
Described ballasting module comprises described ballasting module and comprises nmos pass transistor M
nb, PMOS transistor M
pband resistance R
1; Described nmos pass transistor M
nbgrid drive by described reverse overvoltage detectable signal ESDX, described PMOS transistor M
pbgrid drive by described overvoltage detectable signal ESD; Described nmos pass transistor M
nbdrain electrode, described PMOS transistor M
pbsource electrode, described resistance R
1one end all connect described power line V
dD; Described nmos pass transistor M
nbsource electrode, described PMOS transistor M
pbdrain electrode, described resistance R
1the other end all connect PMOS transistor M in input pole inverter
psource electrode.Described input pole inverter comprises PMOS transistor M
p, nmos pass transistor M
n, described PMOS transistor M
pdrain electrode and described nmos pass transistor M
ndrain electrode, internal circuit connect, described PMOS transistor M
pgrid connect described nmos pass transistor M
ngrid connect, described nmos pass transistor M
nsource electrode connect described ground wire V
sS.
Described transmission gate module comprises PMOS transistor M
pt, nmos pass transistor M
nta, nmos pass transistor M
nt; Described PMOS transistor M
pt, nmos pass transistor M
ntagrid all drive by described overvoltage detectable signal ESD, described nmos pass transistor M
ntgrid described in oppositely overvoltage detectable signal ESDX driven; Described PMOS transistor M
ptsource electrode, described nmos pass transistor M
ntdrain electrode all connect described pressure welding point; Described PMOS transistor M
ptdrain electrode, described nmos pass transistor M
ntsource electrode, described nmos pass transistor M
ntadrain electrode all connect the input of described input stage inverter; Described nmos pass transistor M
ntasource ground.
As shown in Figure 3, when the esd event of worst case occurs, first overvoltage phenomenon appears at pressure welding point.Due to pressure welding point and described power line V
dDbetween there is forward biased diode D
1, therefore power line V
dDon also there will be overvoltage phenomenon, power line V
dDon overvoltage phenomenon by resistance R and diode D
3, D
4, D
5and D
6detected, now, PMOS transistor M
p1drain electrode output logic high level, this level be exactly over-voltage events occur significant level.PMOS transistor M
p1the logic high of drain terminal, first after two-stage inverter INV4, INV5, triggers the transistor M that releases
big, meanwhile, release transistor M
biggrid voltage again after inverter drive module drive, export effective overvoltage detectable signal ESD and reverse overvoltage detectable signal ESDX, in described inverter drive module, the supply power voltage design of inverter is not consistent, this is needed to turn off completely under the ESD impact event of worst case by the transistor in transmission gate module and ballasting module, when chip normal running, the designing requirement of opening completely is needed to determine.After transmission gate module receives effective ESD signal and ESDX signal, transmission gate transistor M
ptand M
ntturn off completely, disconnect the electrical connection between input stage inverter input and pressure welding point, meanwhile, nmos pass transistor M
ntabe biased and enter conducting state, force the input signal zero setting input stage inverter, more a step ensure that the safety of its gate oxide.After ballasting module receives effective ESD signal and ESDX signal, transmission gate transistor M
pband M
nbturn off completely, they and resistance R
1at described power line V after parallel connection
dDand form larger resistance between input stage inverter, guarantee the PMOS transistor M in input stage inverter
pdo not become the weakness of electrostatic breakdown.
For the integrated circuit technology of 65nm, the normal working voltage of chip is 2.5V, and the gate oxide breakdown voltage of input stage inverter is 6.0V.What Figure 4 shows that over-voltage events returns stagnant scanning simulation result, as seen from the figure: when IN end reaches 4.8V relative to the forward overvoltage on ground, the high jump of ESD signal, ESDX signal are jumped low, the generation of indication over-voltage events, IN1 signal now after transmission gate module no longer follows the change of IN signal, but is forced to be biased to zero.When adopting reverse scan, the result of Fig. 4 shows: the trip point that IN1 signal follows IN signal intensity is again lower than the trip point departed from before, and this is by the nmos pass transistor M in power clamp ESD protective circuit
fbdetermine, regulate M
fbsize can change the spacing of two trip points.In Fig. 4, the trip point voltage that IN1 signal follows IN signal intensity is again 3.8V, is enough to the surplus of the normal operating voltage 2.5V of chip, 1.3V.
When chip normally works, the MG signal of input stage esd protection circuit of the present invention is logic low, and now ESD signal and ESDX are respectively logic low and logic is high, and indication does not have over-voltage events to occur.Transmission gate transistor M
ptand M
ntopen completely, guarantee the normal transmission of data, transmission gate transistor M
pband M
nbalso open completely, make described power line V
dDpMOS transistor M in input stage inverter
pthe resistance of source is very little, ensures the transmission that voltage is harmless.Fig. 5 is the simulation result schematic diagram of chip when normally working, and in figure, ESD signal maintains very low level all the time, shows the generation not having over-voltage events, and the signal of IN end can be sent to IN1 end smoothly, holds to INNER through reverse transfer meanwhile.
Input stage esd protection circuit of the present invention is when ensureing to occur in the ESD impact of worst case; input stage inverter gate oxide is not by under the prerequisite of over-voltage breakdown; guarantee that esd protection designs the extra domain expense brought to chip very little, there is very large actual application value.
Above execution mode is only for illustration of the present invention, but not limitation of the present invention.Although with reference to embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, various combination, amendment or equivalent replacement are carried out to technical scheme of the present invention, do not depart from the spirit and scope of technical solution of the present invention, all should be encompassed in the middle of right of the present invention.
Claims (6)
1. an input stage esd protection circuit, is characterized in that, comprises diode (led) module, power clamp ESD protective circuit, ballasting module, transmission gate module, inverter drive module;
Described diode (led) module is used for when there is ESD impact between pressure welding point and other chip pin, effectively electrostatic charge is directed to design release on path, when chip normally works, provide data path and power line V
dDbetween isolation;
Described power clamp ESD protective circuit is for detecting described power line V
dDand the over-voltage events that pressure welding point occurs; when there being ESD impact to cause overvoltage phenomenon; described power clamp ESD protective circuit sends useful signal; triggering is released transistor turns; disconnect the electrical connection between pressure welding point and input stage inverter gate oxide, and increase input stage inverter and described power line V
dDbetween contact resistance, guaranteeing that the path of releasing that electrostatic charge passes through to design is released, when not having over-voltage events to be detected, guaranteeing the undamped transmission of data, and ensure that transistor of releasing is in strict off state;
The signal that described inverter drive module is used for providing according to described power clamp ESD protective circuit drives described transmission gate module and described ballasting module, make the transmission gate transistor in two modules when the esd event of worst case occurs, turn off completely, when transfer of data, open completely;
Described ballasting module is used for the drive singal sent according to described inverter drive module, dynamic change input stage inverter PMOS transistor M
psource electrode and described power line V
dDbetween resistance, when an esd event occurs, increase the M of input stage inverter PMOS transistor
psource electrode and described power line V
dDbetween resistance, guarantee that the path of releasing that electrostatic charge passes through to design is released, when chip normal running, significantly reduce input stage inverter PMOS transistor M
psource electrode and described power line V
dDbetween resistance, guarantee that voltage is unattenuated;
Described transmission gate module is used for the drive singal sent according to described inverter drive module, when over-voltage events occurs, electrical connection between the gate oxide of disconnection pressure welding point and input stage inverter, simultaneously, the input voltage of input stage inverter is forced to be biased to zero, when chip normal running, guarantee the normal transmission of data.
2. input stage esd protection circuit according to claim 1, is characterized in that, described power clamp ESD circuit comprises the transistor M that releases
big, resistance R, R
2, diode D
3, D
4, D
5, D
6, PMOS transistor M
p1, nmos pass transistor M
fb, inverter INV4, INV5; The described transistor M that releases
bigfor nmos pass transistor, its grid connects described inverter drive module; One end of described resistance R, described PMOS transistor M
p1source electrode, described in release transistor M
bigdrain electrode all with described power line V
dDconnect; The other end of described resistance R and described diode D
3input, described PMOS transistor M
p1grid, described nmos pass transistor M
fbdrain electrode connect; Described PMOS transistor M
p1drain electrode, described nmos pass transistor M
fbgrid, described resistance R
2one end be all connected with the input of described inverter INV4; The output of described inverter INV4 is connected with the input of described inverter INV5, the output of described inverter INV5 and the described transistor M that releases
biggrid connect, described supply voltage V
dDfor described inverter INV4, INV5 power; Described diode D
3negative electrode and described diode D
4anode connect, described diode D
4negative electrode and described diode D
5anode connect, described diode D
5negative electrode and described diode D
6anode connect, described diode D
6negative electrode, described nmos pass transistor M
fbsource electrode, described resistance R
2the other end, described in release transistor M
bigsource electrode all with described ground wire V
sSconnect.
3. input stage esd protection circuit according to claim 1, is characterized in that, described inverter drive module comprises inverter INV1, INV2, INV3; The described transistor M that releases
biggrid voltage drive through described inverter INV1, INV2, output overvoltage detectable signal ESD; Described overvoltage detectable signal ESD carries out logic reversal through described inverter INV3, exports reverse overvoltage detectable signal ESDX; Pressure welding point voltage is that described inverter INV1, INV2 power, supply voltage V
dDfor described inverter INV3 powers.
4. input stage esd protection circuit according to claim 1, is characterized in that, described ballasting module comprises nmos pass transistor M
nb, PMOS transistor M
pband resistance R
1;
Described nmos pass transistor M
nbgrid driven by described reverse overvoltage detectable signal ESDX, described PMOS transistor M
pbgrid drive by described overvoltage detectable signal ESD; Described nmos pass transistor M
nbdrain electrode, described PMOS transistor M
pbsource electrode, described resistance R
1one end all connect described power line V
dD; Described nmos pass transistor M
nbsource electrode, described PMOS transistor M
pbdrain electrode, described resistance R
1the other end all connect PMOS transistor M in input pole inverter
psource electrode.
5. input stage esd protection circuit according to claim 1, is characterized in that, described transmission gate module comprises PMOS transistor M
pt, nmos pass transistor M
nta, nmos pass transistor M
nt;
Described PMOS transistor M
pt, nmos pass transistor M
ntagrid all drive by described overvoltage detectable signal ESD, described nmos pass transistor M
ntgrid drive by described reverse overvoltage detectable signal ESDX; Described PMOS transistor M
ptsource electrode, described nmos pass transistor M
ntdrain electrode all connect described pressure welding point; Described PMOS transistor M
ptdrain electrode, described nmos pass transistor M
ntsource electrode, described nmos pass transistor M
ntadrain electrode all connect the input of described input stage inverter; Described nmos pass transistor M
ntasource ground.
6. input stage esd protection circuit according to claim 1, is characterized in that, described inverter INV1, INV2, INV3, INV4, INV5 are CMOS inverter.
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| CN201410461667.1A CN104283201B (en) | 2014-09-11 | 2014-09-11 | Input stage esd protection circuit |
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|---|---|---|---|
| CN201410461667.1A CN104283201B (en) | 2014-09-11 | 2014-09-11 | Input stage esd protection circuit |
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| CN104283201B CN104283201B (en) | 2017-02-15 |
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| US10734806B2 (en) | 2016-07-21 | 2020-08-04 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
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| CN113131913A (en) * | 2019-12-30 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | Input stage circuit, drive circuit and power supply system |
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| CN112218513B (en) * | 2020-10-13 | 2023-08-22 | Oppo广东移动通信有限公司 | Chip, antenna module and terminal |
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