CN104347622A - Direct current triggering power supply clamp ESD (electronic static discharge) protection circuit - Google Patents

Direct current triggering power supply clamp ESD (electronic static discharge) protection circuit Download PDF

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Publication number
CN104347622A
CN104347622A CN201410461041.0A CN201410461041A CN104347622A CN 104347622 A CN104347622 A CN 104347622A CN 201410461041 A CN201410461041 A CN 201410461041A CN 104347622 A CN104347622 A CN 104347622A
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CN
China
Prior art keywords
transistor
direct current
big
protective circuit
grid
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CN201410461041.0A
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Chinese (zh)
Inventor
王源
陆光易
曹健
贾嵩
张兴
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北京大学
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Priority to CN201410461041.0A priority Critical patent/CN104347622A/en
Publication of CN104347622A publication Critical patent/CN104347622A/en

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Abstract

The invention relates to the field of integrated circuit chip ESD protection, in particular to a direct current triggering power supply clamp ESD (electronic static discharge) protection circuit. The direct current triggering power supply clamp ESD protection circuit comprises a discharge transistor M<big> and a direct current voltage detection circuit, wherein the discharge transistor M<big> is used for discharging static charges, and the direct current voltage detection circuit is connected between a power supply wire V<DD> and a ground wire V<SS>, is connected with the discharge transistor M<big> and is used for judging whether the pulse on the power supply wire VDD is the static discharge pulse or not; if so, the corresponding signals are sent to the discharge transistor M<big>. The direct current triggering power supply clamp ESD protection circuit has the advantages that in the normal work process, the electricity leakage is little, when ESD events occur, the triggering voltage and the maintenance voltage can fall in the range of an ESD protection window in the advanced process, and the effective ESD protection is formed.

Description

A kind of direct current flip-over type power clamp ESD protective circuit

Technical field

The present invention relates to integrated circuit (IC) chip static discharge (Electronic Static Discharge, ESD) and protect field, particularly relate to a kind of direct current flip-over type power clamp ESD protective circuit.

Background technology

The esd protection design of semiconductor integrated circuit chip is the Focal point and difficult point of semiconductor industry about reliability design always.Along with the continuous progress of semiconductor technology, the window that integrated circuit ESD designs constantly narrows, and on sheet, esd protection becomes difficulty all the more.Structure as esd protection on sheet should have following feature: trigger voltage should higher than the normal operating voltage of chip, simultaneously lower than the failure voltage of chip internal device; ME for maintenance is higher than the normal working voltage of chip, and meanwhile, secondary breakdown current is large as much as possible, and opening resistor is little as much as possible.

Power clamp ESD protective circuit is the esd protection unit be positioned between power line and ground wire, and its effect is when the ESD impact of different mode occurs, and ensures phenomenon chip power line not occurring overvoltage, avoids internal components to produce inefficacy because of overvoltage with this.Common power clamp ESD protective circuit transient soundings module identifies esd event, and when having detected esd event, transistor of releasing proceeds to opening rapidly, static electricity discharge electric charge, ensures the safety of chip internal device.The disadvantage of transient soundings mechanism is: release transistor easily by transient noise false triggering, cause unnecessary power loss.The detection of direct current flip-over type power clamp ESD protective circuit be the amplitude of voltage on power line, when voltage magnitude large to a certain extent after, circuits for triggering provide useful signal to transistor of releasing, and guarantee the safety of internal components in order to static electricity discharge electric charge.

Accompanying drawing 1 and attachedly Figure 2 shows that direct current flip-over type power clamp ESD protective circuit of the prior art; operation principle is: resistance and diode string determine the direct current trigger voltage of protective circuit; when the voltage on power line exceedes this direct current trigger voltage; static electricity discharge electric charge opened by transistor of releasing; meanwhile, feedback transistor (M fb) be also triggered.M fbbe triggered two benefits: one is that transistor of guaranteeing to release all remains on opening within the whole period of esd event; Two is that guarantee the to release shutoff voltage of transistor is less than cut-in voltage, electrostatic charge is released more complete.

In the integrated circuit technology of advanced person, the failure voltage of device constantly reduces, and realize effective chip esd protection, and the trigger voltage of power clamp ESD protective circuit also should reduce accordingly.Thus, there are the following problems for power clamp ESD protective circuit shown in accompanying drawing 1 and accompanying drawing 2: the protective circuit shown in accompanying drawing 1 uses resistance to add the detecting strategy of two diodes, although can realize less trigger voltage, the electric leakage under normal bias is very large; The resistance that protective circuit shown in accompanying drawing 2 uses adds the detecting strategy of four diodes, and electric leakage when can ensure normal bias is less, but can not meet the demand of less trigger voltage.

Therefore, for above deficiency, need to provide a kind of direct current flip-over type power clamp ESD protective circuit, protective circuit is leaked electricity when chip normally works very little; When esd event occurs, under its trigger voltage and ME for maintenance can drop on advanced technologies, ESD protects in window ranges, forms effective esd protection, guarantees the safety of internal components.

Summary of the invention

(1) technical problem that will solve

The technical problem to be solved in the present invention is ensureing, under the prerequisite that under normal bias, leakage current is little, to realize when esd event occurs, and under trigger voltage and ME for maintenance drop on advanced technologies, ESD protects in window ranges.

(2) technical scheme

In order to solve the problems of the technologies described above, the invention provides a kind of direct current flip-over type power clamp ESD protective circuit, being positioned over the power line V of chip dDwith ground wire V sSbetween, described direct current flip-over type power clamp ESD protective circuit comprises

Release transistor M big, for static electricity discharge electric charge;

Direct voltage detection circuit, is connected to described power line V dDwith described ground wire V sSbetween, and with the described transistor M that releases bigbe connected; For differentiating described power line V dDon pulse whether be electrostatic discharge pulses, if so, then send corresponding signal to the described transistor M that releases big;

Wherein, described direct voltage detection circuit comprises resistance R g, described resistance R gone end and described ground wire V sSbe connected, for ensureing when chip normally works, described in release transistor M biggrid have a direct current to ground path, release described in making transistor M bigremain on off state.

Preferably, release described in transistor M bigfor nmos pass transistor, described in release transistor M bigsource electrode and described ground wire V sSbe connected, described in release transistor M bigdrain electrode and described power line V dDbe connected, described in release transistor M biggrid and described resistance R gthe other end be connected.

Preferably, described detection circuit also comprises diode, the feedback transistor M of resistance R, the series connection of multiple forward successively fband transistor M p1, wherein, described feedback transistor M fbfor nmos pass transistor, described transistor M p1for PMOS transistor; One end of described resistance R and described transistor M p1grid be connected, the other end of described resistance R and described power line V dDbe connected; Described transistor M p1drain electrode and the described transistor M that releases biggrid be connected, described transistor M p1source electrode and described power line V dDbe connected; Described feedback transistor M fbsource electrode and described ground wire V sSbe connected, described feedback transistor M fbdrain electrode and described transistor M p1grid be connected, described feedback transistor M fbgrid and described transistor M p1drain electrode be connected; The anode of the described diode of multiple series connection of forward successively and described transistor M p1grid be connected, the negative electrode of the described diode of multiple forward successively series connection and described ground wire V sSbe connected.

Preferably, the described diode of multiple series connection of forward is successively according to the difference of technique, and number is 3-5.

(3) beneficial effect

Technique scheme tool of the present invention has the following advantages: this direct current flip-over type power clamp ESD protective circuit, when chip normally works, is leaked electricity very little; When esd event occurs, under its trigger voltage and ME for maintenance can drop on advanced technologies, ESD protects in window ranges, forms effective esd protection, guarantees the safety of internal components.

Accompanying drawing explanation

Fig. 1 is a kind of direct current flip-over type power clamp ESD protective circuit structural representation in prior art;

Fig. 2 is another kind of direct current flip-over type power clamp ESD protective circuit structural representation in prior art;

Fig. 3 is the direct current flip-over type power clamp ESD protective circuit structural representation of the embodiment of the present invention one;

Fig. 4 be the unlatching of circuit shown in Fig. 1, shutoff voltage and normal bias time the direct current simulation result schematic diagram of electric leakage;

Fig. 5 be the unlatching of circuit shown in Fig. 2, shutoff voltage and normal bias time the direct current simulation result schematic diagram of electric leakage;

Fig. 6 be the unlatching of circuit shown in Fig. 3, shutoff voltage and normal bias time the direct current simulation result schematic diagram of electric leakage.

Embodiment

Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.

Embodiment one

Be illustrated in figure 3 the direct current flip-over type power clamp ESD protective circuit structural representation that the embodiment of the present invention provides.

This direct current flip-over type power clamp ESD protective circuit comprises: direct voltage detection circuit and the transistor M that releases big.Wherein, described direct voltage detection circuit comprises: transistor M p1, feedback transistor M fb, resistance R, resistance R g; Diode D 1, D 2, D 3with D 4.Wherein, described transistor M p1for PMOS transistor, described feedback transistor M fbfor nmos pass transistor; Described transistor M p1grid be connected with one end of described resistance R, the other end of described resistance R and the power line V of described direct current flip-over type power clamp ESD protective circuit dDbe connected, described transistor M p1source electrode and described power line V dDbe connected, described transistor M p1drain electrode and described resistance R gone end be connected, described resistance R gthe other end and the ground wire V of described direct current flip-over type power clamp ESD protective circuit sSbe connected, described feedback transistor M fbgrid and described transistor M p1drain electrode be connected, described feedback transistor M fbsource electrode and described ground wire V sSbe connected, described feedback transistor M fbdrain electrode and described transistor M p1grid be connected, described diode D 1anode and described transistor M p1grid be connected, described diode D 1negative electrode and described diode D 2anode be connected, described diode D 2negative electrode and described diode D 3anode be connected, described diode D 3negative electrode and described diode D 4anode be connected, described diode D 4negative electrode and described ground wire V sSbe connected.The described transistor M that releases bigfor nmos pass transistor, its grid and transistor M p1drain electrode be connected, its source electrode and described ground wire V sSbe connected, its drain electrode and described power line V dDbe connected.

Wherein, due to the difference of manufacture craft, in direct voltage detection circuit, the optional scope of the number of diode is 3-5, the present embodiment towards technique in, 4 diodes be designed to optimum, but not as limit.

Further, described direct voltage detection circuit is used for judging to occur in described power line V according to the amplitude of pulse dDon pulse whether meet the direct voltage criterion of ESD impact, if meet, then send response signal to the described transistor M that releases big, release described in making transistor M bigopen and ensure all to maintain opening during whole ESD impact.In ESD impact temporarily, release described in transistor M bigenter its deflated state according to response signal, the electrostatic charge that ESD impact of effectively releasing is brought, prevent chip internal device from suffering damage.

The present embodiment does esd protection design for the integrated circuit technology of 65nm, and the puncture voltage of its internal components is 6.0V, and the normal working voltage of chip is 2.5V.

In traditional design scheme shown in Fig. 1, in order to meet the demand of esd protection under advanced technologies, resistance is adopted to add the direct voltage detecting strategy of two diodes.Fig. 4 be in Fig. 1 direct current flip-over type power clamp ESD protective circuit open, shutoff voltage and normal bias time the direct current simulation result of electric leakage; as can be seen from Figure 4; the cut-in voltage of power clamp ESD protective circuit shown in Fig. 1 is 5.0V, and shutoff voltage is 4.0V.The size of the cut-in voltage of circuit shown in Fig. 1 and shutoff voltage meets the requirement that ESD under advanced technologies protects window, can form effective esd protection scheme, and effectively can prevent the generation of latch-up.But the electric leakage of circuit shown in Fig. 1 under the normal DC of 2.5V is biased reaches 31.7 μ A; the electric leakage of esd protection structure when normal bias that usual industry requires should in nA magnitude; so the electric leakage of circuit shown in Fig. 1 when normal bias does not meet the demands.

In traditional design scheme shown in Fig. 2, in order to make the electric leakage of protective circuit when normal bias less, resistance is adopted to add the direct voltage detecting strategy of four diodes.Fig. 5 be in Fig. 2 direct current flip-over type power clamp ESD protective circuit open, shutoff voltage and normal bias time the direct current simulation result of electric leakage; as can be seen from Figure 5; the electric leakage of circuit shown in Fig. 2 under the normal DC of 2.5V is biased is 36.2nA, can meet the requirement that industry is leaked electricity under normal bias condition to esd protection structure.But as can be seen from Figure 5, the trigger voltage of circuit shown in Fig. 2 reaches 9.2V, greatly exceed the puncture voltage of chip internal device under 65nm technique, esd protection on effective sheet cannot be formed.

Based on the above-mentioned fact, the direct current flip-over type power clamp ESD protective circuit that the present invention proposes as shown in Figure 3.The protective circuit that the present invention proposes is compared with traditional design scheme; eliminate the nmos pass transistor on signal transmission pathway required for conventional inverter; when esd event occurs; without the effect that nmos pass transistor drags down transistor grid voltage of releasing; making to release transistor can unlatching comparatively early, meets the demand that ESD under advanced technologies protects window.Circuit shown in Fig. 3 also add the resistance R be connected with transistor gate of releasing relative to traditional design g, in order to ensure when chip normally works, the grid of transistor of releasing has a direct current to the path on ground, makes it remain on the state of shutoff.The trigger voltage of the direct current flip-over type power clamp ESD protective circuit that the present invention proposes can by changing R gsize regulate, its ME for maintenance can by change M fbsize regulate.

Figure 6 shows that the direct current flip-over type power clamp ESD protective circuit that the present invention proposes is opened, shutoff voltage and normal bias time the direct current simulation result of electric leakage.As can be seen from Figure 6, the direct current flip-over type power clamp ESD protective circuit cut-in voltage that the present invention proposes is 5.0V, and shutoff voltage is 4.2V, can meet ESD under advanced technologies preferably and protect the requirement of window.Meanwhile, the electric leakage of direct current flip-over type power clamp ESD protective circuit under 2.5V direct current biasing that the present invention proposes is 30.6nA, also meets the requirement that industry is leaked electricity under normal bias condition to esd protection structure.

In sum; the direct current flip-over type power clamp ESD protective circuit that the present invention proposes overcomes Traditional DC flip-over type power clamp ESD protective circuit Problems existing; under the drain conditions less when normal work; achieve rational ESD protection Design window, meet the requirement of ESD design under advanced technologies.

Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.

Claims (4)

1. a direct current flip-over type power clamp ESD protective circuit, is positioned over the power line V of chip dDwith ground wire V sSbetween, it is characterized in that, described direct current flip-over type power clamp ESD protective circuit comprises
Release transistor M big, for static electricity discharge electric charge;
Direct voltage detection circuit, is connected to described power line V dDwith described ground wire V sSbetween, and with the described transistor M that releases bigbe connected; For differentiating described power line V dDon pulse whether be electrostatic discharge pulses, if so, then send corresponding signal to the described transistor M that releases big;
Wherein, described direct voltage detection circuit comprises resistance R g, described resistance R gone end and described ground wire V sSbe connected, for ensureing when chip normally works, described in release transistor M biggrid have a direct current to ground path, release described in making transistor M bigremain on off state.
2. direct current flip-over type power clamp ESD protective circuit according to claim 1, is characterized in that, described in release transistor M bigfor nmos pass transistor, described in release transistor M bigsource electrode and described ground wire V sSbe connected, described in release transistor M bigdrain electrode and described power line V dDbe connected, described in release transistor M biggrid and described resistance R gthe other end be connected.
3. direct current flip-over type power clamp ESD protective circuit according to claim 2, is characterized in that, described detection circuit also comprises diode, the feedback transistor M of resistance R, the series connection of multiple forward successively fband transistor M p1, wherein, described feedback transistor M fbfor nmos pass transistor, described transistor M p1for PMOS transistor; One end of described resistance R and described transistor M p1grid be connected, the other end of described resistance R and described power line V dDbe connected; Described transistor M p1drain electrode and the described transistor M that releases biggrid be connected, described transistor M p1source electrode and described power line V dDbe connected; Described feedback transistor M fbsource electrode and described ground wire V sSbe connected, described feedback transistor M fbdrain electrode and described transistor M p1grid be connected, described feedback transistor M fbgrid and described transistor M p1drain electrode be connected; The anode of the described diode of multiple series connection of forward successively and described transistor M p1grid be connected, the negative electrode of the described diode of multiple forward successively series connection and described ground wire V sSbe connected.
4. direct current flip-over type power clamp ESD protective circuit according to claim 3, is characterized in that, the described diode of multiple series connection of forward is successively according to the difference of technique, and number is 3-5.
CN201410461041.0A 2014-09-11 2014-09-11 Direct current triggering power supply clamp ESD (electronic static discharge) protection circuit CN104347622A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110518561A (en) * 2019-07-26 2019-11-29 北京大学 A kind of power clamp ESD protective circuit and integrated circuit structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6069782A (en) * 1998-08-26 2000-05-30 Integrated Device Technology, Inc. ESD damage protection using a clamp circuit
US6411480B1 (en) * 1999-03-01 2002-06-25 International Business Machines Corporation Substrate pumped ESD network with trench structure
CN1658388A (en) * 2004-02-18 2005-08-24 富士通株式会社 Electrostatic discharge protection circuit
CN102170118A (en) * 2011-04-28 2011-08-31 北京大学 Power supply clamping position ESD (electronic static discharge) protecting circuit
CN103248033A (en) * 2013-05-09 2013-08-14 北京大学 Transient and DC synchronous triggering type power supply clamping ESD protection circuit
CN103646945A (en) * 2013-12-03 2014-03-19 北京中电华大电子设计有限责任公司 Integrated circuit power supply esd protection circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6069782A (en) * 1998-08-26 2000-05-30 Integrated Device Technology, Inc. ESD damage protection using a clamp circuit
US6411480B1 (en) * 1999-03-01 2002-06-25 International Business Machines Corporation Substrate pumped ESD network with trench structure
CN1658388A (en) * 2004-02-18 2005-08-24 富士通株式会社 Electrostatic discharge protection circuit
CN102170118A (en) * 2011-04-28 2011-08-31 北京大学 Power supply clamping position ESD (electronic static discharge) protecting circuit
CN103248033A (en) * 2013-05-09 2013-08-14 北京大学 Transient and DC synchronous triggering type power supply clamping ESD protection circuit
CN103646945A (en) * 2013-12-03 2014-03-19 北京中电华大电子设计有限责任公司 Integrated circuit power supply esd protection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110518561A (en) * 2019-07-26 2019-11-29 北京大学 A kind of power clamp ESD protective circuit and integrated circuit structure

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