CN103795026B - Input stage esd protection circuit - Google Patents
Input stage esd protection circuit Download PDFInfo
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- CN103795026B CN103795026B CN201410071681.0A CN201410071681A CN103795026B CN 103795026 B CN103795026 B CN 103795026B CN 201410071681 A CN201410071681 A CN 201410071681A CN 103795026 B CN103795026 B CN 103795026B
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Abstract
The invention discloses a kind of input stage esd protection circuit, relate to the technical field of integrated circuit electro-static discharge protection design under deep submicron process.Input stage esd protection circuit disclosed by the invention includes diode string, power clamp ESD protective circuit, ESD amplitude Characteristics detecting module and transmission gate module.The input stage esd protection circuit that the present invention proposes can be under input pressure welding point forward ESD impact over the ground; effectively gate oxide and the electrical connection inputted between pressure welding point of input stage are disconnected; make the over-voltage breakdown that the gate oxide of input stage brings from esd event; simultaneously; when normal data transfer, it is ensured that signal is not the most decayed.
Description
Technical field
The present invention relates to static discharge technical field under deep submicron process, be more particularly to one
Input stage esd protection circuit.
Background technology
Along with the continuous progress of integrated circuit processing technique node, setting of chip electro-static discharge protection
Meter difficulty is increasing.The progress of technique makes the gate oxide of semi-conductor electronic device become more
Thin, PN junction becomes more shallow, raceway groove and becomes shorter, and these features the most largely weaken half
The ability of the anti-ESD impact of conducting electrons device.Therefore, under deep submicron process, integrated circuit
ESD protection be a problem that is thorny and that must solve.
On integrated circuit chip, esd protection circuit can be divided three classes, and they are: input stage ESD
Protection circuit, esd protection circuit between output stage esd protection circuit and power supply and ground.
For input stage esd protection circuit, when ESD impact occurs when inputting between pressure welding point and ground,
Release before path fully opens at ESD, input pressure welding point would generally occur a transient state mistake
The event of pressure, the persistent period of this transient overvoltage pulse is the most comparatively short, but amplitude is much larger than
Chip operates voltage normally.In traditional integrated circuit technique, owing to gate oxide is thicker,
The gate oxide of input stage phase inverter usually bears the transient overvoltage brought due to esd event
Impact, but it is as the most thinning of gate oxide, transient overvoltage pulse causes input stage anti-phase
The probability that grid oxide layer lost efficacy is increasing.Therefore, in deep submicron process, input
The esd protection circuit design of level to be not only devoted to improve the resistance ESD punching of protection device self
The ability hit, the most also to ensure to input the overvoltage pulse width that pressure welding point is formed under ESD impact
Value not can exceed that the gate oxide breakdown voltage of input stage phase inverter.
Fig. 1 show under traditional handicraft typical input stage esd protection circuit schematic diagram.In Fig. 1
ESD protection device include: diode string D1-D4, steady resistance RbAnd power clamp ESD
Protection circuit.Steady resistance RbEffect be to ensure that when esd event occurs, what ESD electric current was walked is
The data path of release path rather than the routine that design.In circuit shown in Fig. 1, ESD
The path of releasing of electric charge is by diode D1-D4Form with power clamp ESD protective circuit, in difference
ESD impact pattern under, different elements of releasing can enter opening, it is provided that letting out of low-resistance
Put path ESD current drain is fallen.Under pressure welding point forward impact over the ground, leading of ESD charge
Path is the diode D via forward conduction1And D2With the power clamp ESD protection triggered
Circuit is released to ground, due under this kind of conflicting model, the component that electric current flows through by pressure welding point
At most, the clamp voltage caused in pressure welding point is maximum, is easiest to cause input stage gate oxide
Puncture.In deep submicron process, protection element the clamp voltage formed and gate oxide
Design window between breakdown voltage becomes more and more less, traditional input stage esd protection circuit
Can not effectively prevent puncturing of input stage phase inverter gate oxide.
Summary of the invention
(1) to solve the technical problem that
The technical problem to be solved in the present invention is how to prevent input stage phase inverter gate oxide from being hit
Wear, ensure that the transmission of normal data is undamped simultaneously.
(2) technical scheme
In order to solve above-mentioned technical problem, the invention provides a kind of input stage esd protection circuit,
Described circuit includes that diode string, power clamp ESD protective circuit, ESD amplitude Characteristics detect
Module and transmission gate module；
Described diode string includes diode D1、D2、D3、D4；Described diode D1's
Anode is connected with the pressure welding point of described input stage esd protection circuit, described diode D1Negative electrode
With described diode D2Anode be connected, described diode D2Negative electrode and described input stage ESD
The power line V of protection circuitDDIt is connected；Described diode D3Anode and described diode D4
Negative electrode be connected, so diode D4The ground wire of anode and described input stage esd protection circuit
VSSIt is connected, described diode D3The pressure welding point of negative electrode and described input stage esd protection circuit
It is connected；
Described power clamp ESD protective circuit includes: PMOS transistor Mp1, NMOS brilliant
Body pipe Mn1, nmos pass transistor Mbig, nmos pass transistor Mfb, resistance R, electric capacity C；
Described Mp1Source electrode and described power line VDD, described MbigDrain electrode and described resistance R
One end connect, the other end of resistance R and described electric capacity C, Mp1Grid, Mn1Grid
And MfbDrain electrode connect；The other end of described electric capacity C and described MfbSource electrode, Mn1's
Source electrode, MbigSource electrode and described ground wire VSSConnect；MfbGrid and MbigGrid,
Mp1Drain electrode, Mn1Drain electrode connect；
Described ESD amplitude Characteristics detecting module includes resistance R1, nmos pass transistor Mnc, anti-phase
Device INV1、INV2、INV3And INV4；Described resistance R1One end and described input stage ESD
The pressure welding point of protection circuit connects；Described resistance R1The other end and MncDrain electrode, Mnc's
Grid, INV1Input connect；Described MncSource electrode and described ground wire VSSConnect；INV1
Outfan and INV2Input, INV3Input connect；Described INV2Outfan
It is connected with control signal ESDX；Described INV3Outfan and INV4Input connect；
Described INV4Outfan be connected with control signal ESD；INV1、INV3And INV4Electricity
Source all pressure welding point with described input stage esd protection circuit are connected, INV2Power end and institute
State the power line V of input stage esd protection circuitDDIt is connected；
Described transmission gate module includes: PMOS transistor Mpt, nmos pass transistor Mnt；Institute
State MptGrid be connected with control signal ESD；MptSource electrode and MntDrain electrode and described
The pressure welding point of input stage esd protection circuit is connected；Described MntGrid and control signal ESDX
Connect；MptDrain electrode and MntSource electrode, PMOS transistor MpGrid, NMOS brilliant
Body pipe MnGrid connect.
Preferably, the inverter drive chain of described control signal ESDX and ESD is the most solely
Stand.
(3) beneficial effect
The invention provides a kind of input stage esd protection circuit, this circuit can be at esd event
During generation, the effective electrical connection disconnected between pressure welding point and input inverter gate oxide,
Ensureing the over-voltage breakdown that input stage gate oxide brings from esd event, meanwhile, the present invention carries
The input stage esd protection circuit gone out is when normal data transfer, and signal is not the most decayed.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below
The accompanying drawing used required in embodiment or description of the prior art will be briefly described, aobvious and
Easily insight, the accompanying drawing in describing below is only some embodiments of the present invention, for this area
From the point of view of those of ordinary skill, on the premise of not paying creative work, it is also possible to according to these
Accompanying drawing obtains other accompanying drawing.
Fig. 1 is a kind of common input stage esd protection circuit structural representation under traditional handicraft；
Fig. 2 is the electrical block diagram of the input stage esd protection circuit of the present invention；
Fig. 3 is in order to prove gate oxide and input pressure welding point electrical connection under esd event
Disconnect and additionally add resistive element RfAfter circuit diagram；
Fig. 4 is simulated person's body Model ESD current source waveform figure, and under this esd event,
IN node in the input stage esd protection circuit of conventional input stage esd protection circuit and the present invention
The time dependent schematic diagram of voltage；
Fig. 5 be under simulated person's body Model esd event conventional input stage esd protection circuit and
IN in the input stage esd protection circuit of the present invention1The time dependent schematic diagram of node voltage；
Fig. 6 is the input stage ESD protection of the present invention under simulated person's body Model esd event
ESD node and the time dependent schematic diagram of MG node voltage in circuit；
Fig. 7 is when normal data are transmitted, and is applied to the input stage ESD protection electricity of the present invention
The voltage signal of IN node in road；
Fig. 8 is under the IN signal shown in Fig. 7 drives, the input stage ESD protection of the present invention
IN in circuit1Node voltage schematic diagram over time.
Detailed description of the invention
With embodiment, the present invention is described in further detail below in conjunction with the accompanying drawings.Following example
For the present invention is described, but can not be used for limiting the scope of the present invention.
The input stage esd protection circuit that the present invention proposes, existing input stage under traditional handicraft
On the basis of esd protection circuit, add between the gate oxide of pressure welding point and input inverter
Transmission gate, this transmission gate is controlled by ESD amplitude Characteristics detecting module, when ESD impact exists
When causing overvoltage in pressure welding point, transmission gate disconnects, it is to avoid overvoltage causes input inverter gate oxidation
Puncturing of layer, when normal data transfer, control signal ensures that transmission gate fully opens so that
Signal attenuation is minimum.
It is the input stage esd protection circuit structural representation of the present invention shown in Fig. 2, this circuit bag
Include: diode string, power clamp ESD protective circuit, ESD amplitude Characteristics detecting module and
Transmission gate module.
Described diode string includes diode D1、D2、D3、D4；Described diode D1's
Anode is connected with the pressure welding point of described input stage esd protection circuit, described diode D1Negative electrode
With described diode D2Anode be connected, described diode D2Negative electrode and described input stage ESD
The power line V of protection circuitDDIt is connected；Described diode D3Anode and described diode D4
Negative electrode be connected, so diode D4The ground wire of anode and described input stage esd protection circuit
VSSIt is connected, described diode D3The pressure welding point of negative electrode and described input stage esd protection circuit
It is connected；Described diode string is for occurring pressure welding point to power line or the ESD impact of ground wire
Time, the low impedance path of forward conduction is provided for ESD electric current, when signal normal transmission, plays
Signal buffer action between power line, ground wire and pressure welding point.
Described power clamp ESD protective circuit includes: PMOS transistor Mp1, NMOS brilliant
Body pipe Mn1, nmos pass transistor Mbig, nmos pass transistor Mfb, resistance R, electric capacity C；
Described Mp1Source electrode and described power line VDD, described MbigDrain electrode and described resistance R
One end connect, the other end of resistance R and described electric capacity C, Mp1Grid, Mn1Grid
And MfbDrain electrode connect；The other end of described electric capacity C and described MfbSource electrode, Mn1's
Source electrode, MbigSource electrode and described ground wire VSSConnect；MfbGrid and MbigGrid,
Mp1Drain electrode, Mn1Drain electrode connect；Described power clamp ESD protective circuit is at chip
When suffering ESD impact, low resistance conductive path is provided rapidly between power and ground, constitutes ESD
The important component part in current drain path.When chip normal operating, power clamp ESD is protected
Protection circuit is not turned on, it is ensured that less leakage current.
Described ESD amplitude Characteristics detecting module includes resistance R1, nmos pass transistor Mnc, anti-phase
Device INV1、INV2、INV3And INV4；Described resistance R1One end and described input stage ESD
The pressure welding point of protection circuit connects；Described resistance R1The other end and MncDrain electrode, Mnc's
Grid, INV1Input connect；Described MncSource electrode and described ground wire VSSConnect；INV1
Outfan and INV2Input, INV3Input connect；Described INV2Outfan
It is connected with control signal ESDX；Described INV3Outfan and INV4Input connect；
Described INV4Outfan be connected with control signal ESD；INV1、INV3And INV4Electricity
Source all pressure welding point with described input stage esd protection circuit are connected, INV2Power end and institute
State the power line V of input stage esd protection circuitDDIt is connected.Described ESD amplitude Characteristics detection mould
Block, for when pressure welding point generation ESD impact, sends effective control signal passing to transmission gate
Defeated door turns off, when normal data transfer, it is ensured that fully opening of transmission gate.
Described transmission gate module includes: PMOS transistor Mpt, nmos pass transistor Mnt；Institute
State MptGrid be connected with control signal ESD；MptSource electrode and MntDrain electrode and described
The pressure welding point of input stage esd protection circuit is connected；Described MntGrid and control signal ESDX
Connect；MptDrain electrode and MntSource electrode, PMOS transistor MpGrid, NMOS brilliant
Body pipe MnGrid connect.Described transmission gate module is used for when pressure welding point generation ESD impact,
The control signal sent according to ESD amplitude voltage detecting module, it is achieved pressure welding point and input inversion
Electric isolution between grid oxide layer, it is ensured that the gate oxide of input inverter is from over-voltage breakdown.
Meanwhile, when signal normal transmission, it is ensured that signal is not the most decayed.
In Fig. 2, data are when normal transmission, and the control signal ESD signal of transmission gate is logic
Low, ESDX signal is logic high.Now transmission gate fully opens, and data are by transmission gate and defeated
Entering grade phase inverter and send into internal circuit, wherein input pole phase inverter includes PMOS transistor Mp
And nmos pass transistor Mn.When pressure welding point forward esd event relatively occurs, ESD
Signal becomes logic high, ESDX signal becomes logic low, and now transmission gate complete switches off so that
The gate oxide of input stage phase inverter is from the damage of over-voltage breakdown, and ESD leakage current is from two
Release in the path of releasing of pole pipe D1, D2 and power clamp ESD protective circuit composition.Transmission gate
Control signal ESD and the inverter drive chain of ESDX be separate, this is in order to really
Protect transmission gate fully opening and complete switching off under esd event when normal data transfer
State.
The state complete switched off to prove transmission gate to be really under esd event, in emulation
In, extra resistance RfAdd IN to1Between node and ground wire, as it is shown on figure 3, with card
Bright IN1Node floating state under the overvoltage pulse that esd event causes.
In Fig. 4, an amplitude reaches the current impulse of 2A, in order to equivalence under anthropomorphic phantom's type
The esd event of 3kV, under this event, the IN joint of conventional input stage esd protection circuit
Point voltage peak value is up to about 15V, and the input stage esd protection circuit that the present invention proposes is then only
There is the peak value of about 6V, far below traditional structure.The protection circuit IN joint that the present invention proposes
The ESD amplitude Characteristics detecting element that the reason that some crest voltage reduces is extra has joined pressure welding
Between point and ground wire, constitute relation in parallel with original path of releasing so that whole path
Equivalent resistance reduce.From Fig. 4, conventional input stage esd protection circuit and the present invention propose
Input stage esd protection circuit IN node voltage after peaking, fall down the most rapidly this
One is true, can obtain the power clamp ESD protective circuit in Fig. 1 and Fig. 2 by this ESD
Electric current effectively triggers.
In Fig. 5, under the esd event of simulation, conventional protection circuit IN1The voltage base of node
This is consistent with IN node, IN1The voltage of node is exactly the voltage of input inverter gate oxide,
In the CMOS integrated circuit technology of 65nm, the breakdown voltage of gate oxide is usually 5V,
Conventional protection circuit is at IN1The overvoltage amplitude formed at node is much larger than 5V, it is easy to puncture defeated
Enter the gate oxide of phase inverter.The design concept proposed by the present invention, IN1Node saves at IN
The when that point voltage being more than 5V, electrical connection therebetween is just disconnected, IN1On node
Electric charge by the resistance R in Fig. 3fIt is released to ground so that input stage ESD that the present invention proposes
Protection circuit IN1Node voltage is pulled low rapidly；Along with releasing of electrostatic induced current, when IN node
On voltage magnitude again less than 5V when, transmission gate is again turned on, IN1Node is again by IN
Node drives, and is prevented effectively from the overvoltage damage to input stage phase inverter gate oxide with this.
In Fig. 6, under the esd event of simulation, the input stage ESD protection electricity that the present invention proposes
The ESD signal on road time voltage is more than 5V on IN, proceeds to logic high state, imply that ESD
Event occurs in pressure welding point, IN1Electrical connection between signal and IN signal disconnects.Simultaneously
MG signal illustrates that power clamp ESD protective circuit is effectively triggered over time,
And along with releasing of electrostatic charge, the clamp voltage that power line VDD sees is more and more less.
When Fig. 7 is analog data normal transmission, it is applied to the change in time of the signal on IN node
Change schematic diagram；Fig. 8 is under the IN node signal voltage of simulation drives, IN1Node signal with
The change schematic diagram of time；When data normal transmission, the DC voltage of a 2.5V is to power supply
Line VDDPower supply, the input stage esd protection circuit that as can be seen from the figure present invention proposes is basic
The not decay of band signals.
Embodiment of above is merely to illustrate the present invention, rather than limitation of the present invention.Although ginseng
According to embodiment, the present invention is described in detail, it will be understood by those within the art that,
Technical scheme is carried out various combination, amendment or equivalent, without departure from this
The spirit and scope of inventive technique scheme, all should contain in the middle of scope of the presently claimed invention.
Claims (2)
1. an input stage esd protection circuit, it is characterised in that described circuit includes two poles
Pipe string, power clamp ESD protective circuit, ESD amplitude Characteristics detecting module and transmission gate mould
Block；
Described diode string includes diode D1、D2、D3、D4；Described diode D1's
Anode is connected with the pressure welding point of described input stage esd protection circuit, described diode D1Negative electrode
With described diode D2Anode be connected, described diode D2Negative electrode and described input stage ESD
The power line V of protection circuitDDIt is connected；Described diode D3Anode and described diode D4
Negative electrode be connected, so diode D4The ground wire of anode and described input stage esd protection circuit
VSSIt is connected, described diode D3The pressure welding point of negative electrode and described input stage esd protection circuit
It is connected；
Described power clamp ESD protective circuit includes: PMOS transistor Mp1, NMOS brilliant
Body pipe Mn1, nmos pass transistor Mbig, nmos pass transistor Mfb, resistance R, electric capacity C；
Described Mp1Source electrode and described power line VDD, described MbigDrain electrode and described resistance R
One end connect, the other end of resistance R and described electric capacity C, Mp1Grid, Mn1Grid
And MfbDrain electrode connect；The other end of described electric capacity C and described MfbSource electrode, Mn1's
Source electrode, MbigSource electrode and described ground wire VSSConnect；MfbGrid and MbigGrid,
Mp1Drain electrode, Mn1Drain electrode connect；
Described ESD amplitude Characteristics detecting module includes resistance R1, nmos pass transistor Mnc, anti-phase
Device INV1、INV2、INV3And INV4；Described resistance R1One end and described input stage ESD
The pressure welding point of protection circuit connects；Described resistance R1The other end and MncDrain electrode, Mnc's
Grid, INV1Input connect；Described MncSource electrode and described ground wire VSSConnect；INV1
Outfan and INV2Input, INV3Input connect；Described INV2Outfan
It is connected with control signal ESDX；Described INV3Outfan and INV4Input connect；
Described INV4Outfan be connected with control signal ESD；INV1、INV3And INV4Electricity
Source all pressure welding point with described input stage esd protection circuit are connected, INV2Power end and institute
State the power line V of input stage esd protection circuitDDIt is connected；
Described transmission gate module includes: PMOS transistor Mpt, nmos pass transistor Mnt；Institute
State MptGrid be connected with control signal ESD；MptSource electrode and MntDrain electrode and described
The pressure welding point of input stage esd protection circuit is connected；Described MntGrid and control signal ESDX
Connect；MptDrain electrode and MntSource electrode, PMOS transistor MpGrid, NMOS brilliant
Body pipe MnGrid connect.
Circuit the most according to claim 1, it is characterised in that described control signal ESDX
And the inverter drive chain of ESD is separate.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410071681.0A CN103795026B (en) | 2014-02-28 | 2014-02-28 | Input stage esd protection circuit |
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|---|---|---|---|
| CN201410071681.0A CN103795026B (en) | 2014-02-28 | 2014-02-28 | Input stage esd protection circuit |
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| CN103795026A CN103795026A (en) | 2014-05-14 |
| CN103795026B true CN103795026B (en) | 2016-08-17 |
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| EP3627552A1 (en) * | 2018-09-19 | 2020-03-25 | Nxp B.V. | Rc-triggered bracing circuit |
| EP3817048A1 (en) * | 2019-11-01 | 2021-05-05 | Richwave Technology Corp. | Integrated circuit with electrostatic discharge protection |
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| CN104253410B (en) * | 2014-09-11 | 2017-04-19 | 北京大学 | Overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit |
| CN104283201B (en) * | 2014-09-11 | 2017-02-15 | 北京大学 | Input stage esd protection circuit |
| CN104851881B (en) * | 2015-05-05 | 2017-12-19 | 武汉新芯集成电路制造有限公司 | A kind of electrostatic discharge protective circuit |
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| Publication number | Publication date |
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| CN103795026A (en) | 2014-05-14 |
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