CN202917970U

CN202917970U - Power supply clamping ESD protection circuit

Info

Publication number: CN202917970U
Application number: CN 201220500361
Authority: CN
Inventors: 马和良
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd
Priority date: 2012-09-28
Filing date: 2012-09-28
Publication date: 2013-05-01
Anticipated expiration: 2022-09-28

Abstract

The utility model discloses a power supply clamping ESD protection circuit. The power supply clamping ESD protection circuit includes the following components of: a snubber circuit which is composed of a first PMOS transistor and a first NMOS transistor, wherein a source pole of the first PMOS transistor is connected with a power supply, a grid pole of the first PMOS transistor is connected with a grid pole of the first NMOS transistor, a drain pole of the first PMOS transistor is connected with a drain pole of the first NMOS transistor, and a source pole of the first NMOS transistor is grounded; a bleeder circuit which is composed of a second NMOS transistor, wherein a grid pole of the second NMOS transistor is connected with the drain pole of the first PMOS transistor in the snubber circuit, a drain pole of the second NMOS transistor is connected with the power supply, and a source pole of the second NMOS transistor is grounded; and a detection circuit which is composed of a third NMOS transistor and a capacitor, wherein a grid pole and a drain pole of the third NMOS transistor are connected with the power supply, a source pole of the third NMOS transistor and one end of the capacitor are connected with the gird pole of the first PMOS transistor and the gird pole of the first NMOS transistor in the snubber circuit, and the other end of the capacitor is grounded. The power supply clamp ESD protection circuit of the utility model can assist in significantly improving the ESD protection ability of a chip and saving the area of the chip.

Description

Power supply clamper esd protection circuit

Technical field

The utility model relates to the ESD(static discharge) field, particularly relate to a kind of power supply clamper esd protection circuit.

Background technology

Along with the fast development of integrated circuit technology, the live width of metal-oxide-semiconductor was more and more narrow in recent years, and junction depth is more and more shallow, and the thickness of grid oxide layer is also more and more thinner, and these have all accelerated the demand of circuit design to ESD.When live width was 1 μ m, esd event was very little on the impact of circuit, and when entering 0.18 μ m, 0.13 μ m epoch, especially the following epoch of 90 nanometers, ESD becomes the very urgent problem that needs solution.

General ESD is divided into HBM(Human body model Human Body Model) pattern, MM(machine model Machinery model) pattern and CDM(Charged device model band power mode) pattern.

HBM and MM pattern are outside chip to be discharged, and the esd protection that only relies on input/output port is far from being enough, also need to add esd protection circuit between VDD-to-VSS, thereby leakage current is more fast protected the ESD performance of whole chip.

Referring to shown in Figure 1, traditional power supply clamper esd protection circuit comprises: testing circuit, buffer circuit and leadage circuit.Wherein, testing circuit is made of resistance R 1 and capacitor C 1.Buffer circuit is made of PMOS pipe M1 and NMOS pipe M2.Leadage circuit is made of the 2nd NMOS pipe M3.

Testing circuit is esd pulse or normal power supply electrifying pulse for detection of differentiation.When power supply normally powered on, this moment, testing circuit will guarantee that esd protection circuit do not open, and when esd event occured, testing circuit was wanted to detect rapidly esd pulse, and the work of guiding esd protection circuit, thus leakage current protection chip internal circuit.

Buffer circuit is the output of amplification detection circuit, and this leadage circuit provides driving force, thereby drives leadage circuit work.

The leadage circuit ESD electric current of releasing falls the ESD current drain.When esd event occured, leadage circuit can normally be opened the ESD electric current of releasing; When circuit worked, leadage circuit cut out.Because when esd event occured, electric current all was order of amps, so the metal-oxide-semiconductor size of leadage circuit is all larger.

When esd event occured, testing circuit detected esd pulse, and the buffer circuit output HIGH voltage drives leadage circuit, thereby releases ESD current protection chip internal circuit.

In above-mentioned this traditional esd protection circuit, the described testing circuit that is made of resistance R 1 and capacitor C 1 is exactly the RC delay circuit, and its RC delay time determines the time of leakage current, and delay time is larger, and the leakage current time is also just more.In order to increase delay time, just must increase resistance value or increase capacitance, and purely increase resistance value or increase capacitance, all can increase the area of chip.

The utility model content

The technical problems to be solved in the utility model provides a kind of power supply clamper esd protection circuit, can improve more significantly the ESD protective capacities of chip, and can save the area of chip.

For solving the problems of the technologies described above, power supply clamper esd protection circuit of the present utility model comprises: a testing circuit, a buffer circuit, a leadage circuit;

Described buffer circuit is comprised of PMOS pipe M1 and NMOS pipe M2, the source electrode of the one PMOS pipe M1 is connected with power vd D, the grid of the one PMOS pipe M1 is connected with the grid of NMOS pipe M2, the drain electrode of the one PMOS pipe M1 is connected with the drain electrode of NMOS pipe M2, the source ground GND of NMOS pipe M2;

Described leadage circuit is made of the 2nd NMOS pipe M3, and its grid is connected with the drain electrode of PMOS pipe M1 and the drain electrode of NMOS pipe M2, and its drain electrode is connected its source ground GND with power vd D; Wherein:

Described testing circuit is made of the 3rd NMOS pipe M4 and capacitor C 1, the grid of the 3rd NMOS pipe M4 is connected with power vd D with drain electrode, the grid of PMOS pipe M1 and the grid of NMOS pipe M2 are connected the other end ground connection GND of capacitor C 1 in one end of its source electrode and capacitor C 1 and the described buffer circuit.

The NMOS pipe that the utility model adopts diode to connect replaces the resistance in the testing circuit; make testing circuit have longer time-delay; just guarantee that also esd protection circuit has the ESD electric current of releasing of more time, makes it have better ESD performance, and can save the area of chip.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail:

Fig. 1 is existing power supply clamper esd protection circuit schematic diagram;

Fig. 2 is improved power supply clamper esd protection circuit schematic diagram.

Embodiment

The time that normally powers on is generally about 1ms; and the time that esd event occurs is generally tens nanoseconds or hundreds of nanosecond; so the delay time of testing circuit wants correctly to distinguish that normal power source powers on or esd event in the clamped esd protection circuit of power supply, so delay time will be between the two time.After correct the differentiation, also to increase delay time as far as possible, thereby increase the time of the ESD electric current of releasing.The time of leakage current is determined by delay time.

In the embodiment shown in Figure 2, the NMOS pipe belt that improved power supply clamper esd protection circuit adopts diode to connect is replaced resistance, the same testing circuit that is made of delay circuit that forms.Only have the size of reasonable adjustment NMOS pipe, not only can effectively increase delay time, improve the performance of ESD, simultaneously can also saving chip area.

In conjunction with shown in Figure 2, in the present embodiment, the 3rd NMOS pipe M4 and capacitor C 1 have consisted of testing circuit, and PMOS pipe M1 and NMOS pipe M2 pipe have consisted of the first-level buffer circuit, and the 2nd NMOS pipe M3 has consisted of leadage circuit.Grid and the drain electrode of the 3rd NMOS pipe M4, the source electrode of PMOS pipe M1, the drain electrode of the 2nd NMOS pipe M3 is connected with power vd D respectively.One end of capacitor C 1, the source electrode of NMOS pipe M2, the source electrode of the 2nd NMOS pipe M3 is ground connection GND respectively.

Capacitor C 1 can be PIP(polycrystalline electric capacity) electric capacity, also can be the MIM(metal capacitance) electric capacity.Capacitance is decided according to chip area and delay time, and probable ranges 1～20pF also can be larger.The 2nd NMOS pipe M3 is the leakage current pipe, because the electric current of releasing all is order of amps, so size is generally all larger, concrete size also needs to decide according to the ESD barrier propterty, and the width probable ranges of leakage current pipe is 1000～4000 μ m.The one PMOS pipe M1 and NMOS pipe M2 consist of inverter, can guarantee that its actuating force is just passable.The 3rd NMOS pipe M4 is the NMOS pipe that diode connects, and in order to guarantee the delay effect of testing circuit, generally the 3rd NMOS pipe M4 is designed to down than pipe.

In conjunction with shown in Figure 2, during normal power supply electrifying, the output terminals A point of testing circuit can be with the supply voltage rising, and the output B point of buffer circuit remains low-voltage, therefore leadage circuit cuts out, esd protection circuit is not worked.When esd event occurs when, vdd voltage moment is high voltage, and the testing circuit that is consisted of by the 3rd NMOS pipe M4 and capacitor C 1, because its output terminals A point of time-delay rises slower, be equivalent to keep the low-voltage of a period of time, and buffer circuit drives bleeder pipe the 2nd NMOS pipe M3 conducting with regard to output HIGH voltage, thereby releases the ESD electric current.The time of leakage current is determined by delay time, and delay time is long, and the ESD current time of releasing is just long, and it is cleaner that the ESD electric current just can be released, thereby chip is just safer.

In order to verify the power supply clamper esd protection circuit after the improvement, to traditional power supply clamper esd protection circuit and the power supply clamper esd protection circuit after improving carry out simulating, verifying.

In traditional power supply clamper esd protection circuit, capacitor C 1 is got 10pF, resistance value 50k ohm; the length of its resistance is 15 μ m, and the width of resistance is 1 μ m, and its value is 5k ohm; the number of resistance series connection is 10, i.e. the resistance of 10 5k ohms series connection forms 50k ohm.In the power supply clamper esd protection circuit after improvement, capacitor C 1 remains 10pF, the width of the W(MOS pipe of the 3rd NMOS pipe M4) be 1 μ m, the length of L(MOS pipe) be 10 μ m.Then choosing a rise time is 100ns, and magnitude of voltage is simulated esd pulse from the pulse that 0V rises to 100V.Simulation result shows; in traditional power supply clamper ESD circuit; the time that the output B point of buffer circuit is continuously high level is 376ns; and the output B point of the buffer circuit in the power supply clamper esd protection circuit after improving to be continuously the time of high level be 1565ns; that is to say when equal esd event occurs; traditional power supply clamper esd protection circuit has the ESD electric current of releasing 376 nanoseconds; and the power supply clamper esd protection circuit after improving has the 1565 times nanosecond ESD electric current of releasing, and the power supply clamper esd protection circuit after obviously improving has stronger esd protection ability.Comparison resistance R1 and the 3rd metal-oxide-semiconductor M4 from the area, obviously metal-oxide-semiconductor is saved area more.So the power supply clamper esd protection circuit after improving can strengthen the ESD protective capacities, again can saving chip area.

Although the utility model utilizes specific embodiment to describe, the explanation of embodiment is not limited scope of the present utility model.The one skilled in the art is by reference explanation of the present utility model; in the situation that do not deviate from spirit and scope of the present utility model; easily carry out various modifications or can make up embodiment; for example described buffer circuit is not limited to 1 grade; can also be 3 grades or 5 grades, these also should be considered as protection range of the present utility model.

Claims

1. power supply clamper esd protection circuit comprises:

One buffer circuit, be comprised of PMOS pipe and a NMOS pipe, the source electrode of a described PMOS pipe is connected with power supply, and the grid of a PMOS pipe is connected with the grid of a NMOS pipe, the drain electrode of the one PMOS pipe is connected with the drain electrode of a NMOS pipe, the source ground of a NMOS pipe;

One leadage circuit is made of the 2nd NMOS pipe, and the drain electrode of the PMOS pipe in its grid and the described buffer circuit and the drain electrode of a NMOS pipe are connected, and its drain electrode is connected its source ground with power supply; It is characterized in that, also comprise:

One testing circuit, consisted of by the 3rd NMOS pipe and an electric capacity, the grid of described the 3rd NMOS pipe is connected with power supply with drain electrode, and the grid of a PMOS pipe and the grid of a NMOS pipe are connected the other end ground connection of described electric capacity in an end of its source electrode and described electric capacity and the described buffer circuit.

2. power supply clamper esd protection circuit as claimed in claim 1, it is characterized in that: described buffer circuit can be 1 grade, also can be 3 grades, can also be 5 grades.