CN112087219A - Low-power-consumption hysteresis reverse trigger - Google Patents
Low-power-consumption hysteresis reverse trigger Download PDFInfo
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- CN112087219A CN112087219A CN202010976599.8A CN202010976599A CN112087219A CN 112087219 A CN112087219 A CN 112087219A CN 202010976599 A CN202010976599 A CN 202010976599A CN 112087219 A CN112087219 A CN 112087219A
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- 150000004706 metal oxides Chemical class 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 230000000630 rising effect Effects 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 2
- 230000007306 turnover Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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Abstract
The invention discloses a low-power-consumption hysteresis reverse trigger, which comprises a PMOS (P-channel metal oxide semiconductor), namely P1; 5 NMOS, namely N1, N2, N3, N4, N5; and an inverter INV; the source electrode of the P1 is connected with a power supply signal; the drain of the P1 is respectively connected with the drain of the N1, the gate of the N3, the drain of the N5 and the input end of the INV; the gate of the P1 is connected with the gate of the N1; the source of N1 is respectively connected with the source of N3, the gate of N2 and the drain of N2; the source of N2 is connected to the gate of N4 and the drain of N4. In the scheme of the invention, P2 and P3 are removed from the structure of the Schmitt trigger, the connection mode of N2 is modified, N4 and N5 are added, and an inverter INV is also added; under the condition of ensuring that the width-to-length ratios of P1, N1 and N3 are not changed, N2, N4 and N5 are modified into inverse ratio tubes, the function of reducing the current consumption of the whole circuit can be realized, and the current-reducing circuit has a hysteresis function and lower current loss.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption hysteresis reverse trigger.
Background
The Schmitt trigger has two stable states, but is different from a common trigger in that the Schmitt trigger adopts a potential triggering mode, and the state of the Schmitt trigger is maintained by the potential of an input signal; the schmitt trigger has different threshold voltages for input signals with different changing directions of positive increasing and negative decreasing. Before the input signal triggers the turnover threshold, the output end always keeps low level or high level, and when the input signal reaches the turnover threshold, the output end signal is immediately turned over, so that a transition state in the middle of a common inverter is avoided, and the signal high-low characteristic of a circuit device connected behind the trigger is ensured. However, before the input signal reaches the inversion threshold, the schmitt trigger consumes a large current to maintain the high or low level of the output signal. The power consumption parameter is an important quality parameter of modern circuit design, and the lower the power consumption, the higher the system efficiency.
Therefore, how to reduce the overall power consumption of the schmitt trigger is an urgent problem to be solved in the design field, and a low-power consumption hysteresis reverse trigger is designed aiming at the above problems.
Disclosure of Invention
The invention aims to provide a low-power-consumption hysteresis reverse trigger which has the advantages of hysteresis function and low current loss and solves the problem that a Schmitt trigger needs to consume large current in order to maintain high potential or low potential of an output end signal.
In order to achieve the purpose, the invention adopts the following technical scheme: a low-power-consumption hysteresis inverting trigger comprises a PMOS (P-channel metal oxide semiconductor), namely P1; 5 NMOS, namely N1, N2, N3, N4, N5; and an inverter INV;
the source electrode of the P1 is connected with a power supply signal;
the drain of the P1 is respectively connected with the drain of the N1, the gate of the N3, the drain of the N5 and the input end of the INV;
the gate of the P1 is connected with the gate of the N1;
the source of N1 is respectively connected with the source of N3, the gate of N2 and the drain of N2;
the source of the N2 is connected with the gate of the N4 and the drain of the N4;
the drain electrode of the N3 is connected with a power supply signal;
the source ground signal of N4;
the gate of N5 is connected to the output terminal of the inverter INV, and the source of N5 is grounded.
Further, the device also comprises an OUT port which is connected with the drain of the P1, the drain of the N1, the gate of the N3, the drain of the N5 and the input end of the INV.
Further, the gates of the P1 and N1 are the input terminals IN of the whole circuit module.
Compared with the prior art, the invention has the beneficial effects that:
1. in the scheme, P2 and P3 are removed from the structure of the Schmitt trigger, the connection mode of N2 is modified, N4 and N5 are added, and an inverter INV is also added; under the condition of ensuring that the width-to-length ratios of P1, N1 and N3 are not changed, N2, N4 and N5 are modified into inverse ratio tubes, the function of reducing the current consumption of the whole circuit can be realized, and the current-reducing circuit has a hysteresis function and lower current loss.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a circuit diagram of a Schmitt trigger;
FIG. 2 is a waveform diagram of a transient current and an output waveform of the Schmitt trigger shown in FIG. 1 when the rising and falling times of the input signal are different;
fig. 3 is a circuit diagram of a low power consumption inverting flip-flop according to an embodiment of the present application;
FIG. 4 is a waveform diagram of transient current and an output waveform diagram of the inverting flip-flop according to the embodiment when the rising and falling times of the input signal are different;
fig. 5 is a schematic diagram comparing current consumption of the reverse flip-flop and the schmitt flip-flop according to the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-5, a low power consumption hysteretic inverting flip-flop includes a PMOS, P1; 5 NMOS, namely N1, N2, N3, N4, N5; and an inverter INV;
the source electrode of the P1 is connected with a power supply signal;
the drain of the P1 is respectively connected with the drain of the N1, the gate of the N3, the drain of the N5 and the input end of the INV;
the gate of the P1 is connected with the gate of the N1;
the source of N1 is respectively connected with the source of N3, the gate of N2 and the drain of N2;
the source of the N2 is connected with the gate of the N4 and the drain of the N4;
the drain electrode of the N3 is connected with a power supply signal;
the source ground signal of N4;
the gate of N5 is connected to the output terminal of the inverter INV, and the source of N5 is grounded.
Also included is an OUT port connected to the drain of P1, the drain of N1, the gate of N3, the drain of N5, and the input of INV.
The gates of the P1 and N1 are the input IN of the entire circuit module.
In use, fig. 1 is a circuit diagram of a schmitt trigger, comprising: PMOS P1, P2, and P3; NMOS N1, N2, and N3. The source of the PMOS P1 is connected with a power supply signal, the drain of the P1 is connected with the source of the P2 and the source of the P3, the gate of the P1 is connected with the gate of the P2, the gate of the N1 and the gate of the N2, and the input end IN of the circuit module is formed.
The drain of P3 is connected to a ground signal.
The drain of the P2 is connected with the drain of the N1 and the gates of the P3 and the N3 to be used as the output end OUT of the circuit module.
The source of N1 is connected to the drain of N2 and the source of N3.
The source of N2 is connected to a ground signal.
The drain of N3 is connected to the power supply signal.
When the input signal IN is low, P1, P2, and N3 are on, N1, N2, and P3 are off, and the output signal OUT is high. When the input signal IN is at a high level, P1, P2, and N3 are turned off, N1, N2, and P3 are turned on, and the output signal OUT is at a low level.
The power consumption of the flip-flop determines the noise performance of the flip-flop, and in order to reduce the noise and power consumption of the flip-flop, the power consumption of the flip-flop needs to be reduced. Mainly the power consumption before and after flipping.
Fig. 2 is a waveform diagram of a transient state of the schmitt trigger shown in fig. 1 when the rising and falling times of the input signal are different.
Referring to fig. 2, during the rising of the input IN, the output signal OUT is kept high until the flip threshold is triggered, and the overall circuit power consumption is 66.7 μ a. After the output signal OUT goes high after the flip threshold is triggered during the fall of the input signal IN, the overall circuit power consumption is still 66.7 μ a.
Fig. 3 is a circuit structure diagram of the present invention. On the basis of the reference to fig. 1, P2 and P3 are removed, the connection mode of N2 is modified, N4 and N5 are added, and an inverter INV is also added. Under the condition of ensuring that the width-length ratios of P1, N1 and N3 are not changed, N2, N4 and N5 are modified into inverse ratio tubes, and the function of reducing the current consumption of the whole circuit can be realized.
Referring to fig. 4, the power consumption of the circuit designed by the present invention is only 6 μ a before and after signal inversion, which is only about one eleventh of the power consumption of the original schmitt trigger.
Referring to fig. 5, the power consumption of the circuit designed by the present invention is compared with the power consumption of the circuit of the conventional schmitt trigger.
The invention is not described in detail, but is well known to those skilled in the art.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (3)
1. A low-power-consumption hysteresis inverting trigger comprises a PMOS (P-channel metal oxide semiconductor), namely P1; 5 NMOS, namely N1, N2, N3, N4, N5; and an inverter INV;
the source electrode of the P1 is connected with a power supply signal;
the drain of the P1 is respectively connected with the drain of the N1, the gate of the N3, the drain of the N5 and the input end of the INV;
the gate of the P1 is connected with the gate of the N1;
the source of N1 is respectively connected with the source of N3, the gate of N2 and the drain of N2;
the source of the N2 is connected with the gate of the N4 and the drain of the N4;
the drain electrode of the N3 is connected with a power supply signal;
the source ground signal of N4;
the gate of N5 is connected to the output terminal of the inverter INV, and the source of N5 is grounded.
2. The low-power-consumption hysteresis inverting flip-flop of claim 1, wherein: also included is an OUT port connected to the drain of P1, the drain of N1, the gate of N3, the drain of N5, and the input of INV.
3. The low-power-consumption hysteresis inverting flip-flop of claim 1, wherein: the gates of the P1 and N1 are the input IN of the entire circuit module.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010976599.8A CN112087219B (en) | 2020-09-16 | 2020-09-16 | Low-power consumption hysteresis inverting trigger |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010976599.8A CN112087219B (en) | 2020-09-16 | 2020-09-16 | Low-power consumption hysteresis inverting trigger |
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| CN112087219A true CN112087219A (en) | 2020-12-15 |
| CN112087219B CN112087219B (en) | 2024-07-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381738A (en) * | 2021-06-25 | 2021-09-10 | 上海威固信息技术股份有限公司 | Schmitt trigger with adjustable negative threshold voltage |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403988A (en) * | 2011-12-22 | 2012-04-04 | 中国科学院上海微系统与信息技术研究所 | Power on reset circuit |
| CN202917970U (en) * | 2012-09-28 | 2013-05-01 | 上海华虹集成电路有限责任公司 | Power supply clamping ESD protection circuit |
| CN105337593A (en) * | 2014-06-30 | 2016-02-17 | 无锡华润矽科微电子有限公司 | Hysteresis circuit structure capable of realizing enhanced anti-interference capability |
| CN106325449A (en) * | 2016-08-31 | 2017-01-11 | 中国科学院上海高等研究院 | Power on reset circuit with low power consumption |
| CN206820728U (en) * | 2017-04-11 | 2017-12-29 | 西安电子科技大学 | A kind of Schmidt trigger with unidirectional hysteresis |
-
2020
- 2020-09-16 CN CN202010976599.8A patent/CN112087219B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403988A (en) * | 2011-12-22 | 2012-04-04 | 中国科学院上海微系统与信息技术研究所 | Power on reset circuit |
| CN202917970U (en) * | 2012-09-28 | 2013-05-01 | 上海华虹集成电路有限责任公司 | Power supply clamping ESD protection circuit |
| CN105337593A (en) * | 2014-06-30 | 2016-02-17 | 无锡华润矽科微电子有限公司 | Hysteresis circuit structure capable of realizing enhanced anti-interference capability |
| CN106325449A (en) * | 2016-08-31 | 2017-01-11 | 中国科学院上海高等研究院 | Power on reset circuit with low power consumption |
| CN206820728U (en) * | 2017-04-11 | 2017-12-29 | 西安电子科技大学 | A kind of Schmidt trigger with unidirectional hysteresis |
Non-Patent Citations (2)
| Title |
|---|
| SAMEER KUMAR JHA ET AL: "Design of Low Power CMOS Based Schmitt Trigger in 180nm Technology", 《2019 4TH INTERNATIONAL CONFERENCE ON INTERNET OF THINGS: SMART INNOVATION AND USAGES (IOT-SIU)》 * |
| 陈星弼 等: "提高功率器件整体性能的研究", 《中国优秀博硕士学位论文全文数据库 (博士) 信息科技辑》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381738A (en) * | 2021-06-25 | 2021-09-10 | 上海威固信息技术股份有限公司 | Schmitt trigger with adjustable negative threshold voltage |
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