CN212034096U - Power consumption-free analog switch with voltage processing function - Google Patents

Abstract

The utility model discloses a no consumption analog switch with voltage processing function, include: two switch tubes, trombone slide, dip tube, pmos substrate selection circuit, nmos substrate selection circuit, drive circuit, level shift circuit, mains voltage detection circuit, high-low voltage selection circuit, the utility model provides a no consumption analog switch with voltage processing function, switch input and output are complete symmetrical, can two-way switch on, and the switch tube feels has the characteristic of transmission positive and negative voltage signal, and the switch tube can turn-off rapidly after the power failure, blocks the transmission of input terminal positive and negative voltage signal, has improved the isolation of switch tube under mains voltage power failure state greatly to this analog switch does not have static consumption.

Description

Power consumption-free analog switch with voltage processing function

Technical Field

The utility model relates to an analog switch's technical field, more specifically the no consumption analog switch field that says so involves a have voltage processing ability.

Background

The analog switch mainly completes the signal switching function in a signal link, and adopts a MOS tube switching mode to realize the turn-off or turn-on of the signal link.

At present, for an analog switch used for transmitting audio signals, the isolation of the switch in a power-down state is an important index, the audio analog switch usually adopts a pair of correlated pmos tube and nmos tube, the switch can only meet the requirements of transmitting positive voltage and negative voltage, if the switch is not processed, the switch tube can not be ensured to be in a turn-off state after power supply voltage is powered down, in the prior art, a pull-up resistor is usually connected to the grid electrode of a first switch tube, and a pull-down resistor is usually connected to the grid electrode of a second switch tube.

However, the mode cannot ensure that the switching tube can be quickly turned off after the power supply is powered down, and meanwhile, the mode also introduces larger static power consumption, so that the requirement of ultra-low power consumption in application occasions cannot be met.

Therefore, a power consumption free analog switch with voltage processing capability is a problem that needs to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a no consumption analog switch with voltage processing function has solved the problem that the switch tube can turn off rapidly and keep apart positive and negative voltage after the power failure, has positive and negative voltage processing function simultaneously.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a power-consumption-free analog switch having a voltage processing function, comprising:

a first switch tube;

the first driving circuit is connected with the grid electrode of the first switching tube;

the drain electrode of the pull-up tube is connected with the first drive circuit and the grid electrode of the first switch tube;

the drain of the second switch tube is connected with the source of the first switch tube, and the source of the second switch tube is connected with the drain of the first switch tube;

the second driving circuit is connected with the grid electrode of the second switching tube;

a drain of the pull-down tube is connected with the second drive circuit and the grid electrode of the second switch tube;

the first level shift circuit is respectively connected with the grid electrode of the pull-up tube and the grid electrode of the pull-down tube;

the second level shift circuit is connected with the first drive circuit and the first level shift circuit;

a third level shift circuit connected to the second driving circuit, the first level shift circuit, and the second level shift circuit;

the logic control circuit is respectively connected with the second level shift circuit and the third level shift circuit;

and the power supply voltage detection circuit is respectively connected with the first level shift circuit, the second level shift circuit and the third level shift circuit.

Preferably, the source of the pull-up tube is a high-voltage output end, and the high-voltage output end is connected to the first driving circuit, the second driving circuit, the first level shift circuit, the second level shift circuit, and the third level shift circuit.

Preferably, the source of the pull-down tube is a low-voltage output end, and the low-voltage output end is connected to the first driving circuit, the second driving circuit, the first level shift circuit, the second level shift circuit, and the third level shift circuit.

Preferably, the power voltage detection circuit comprises a first pmos transistor, a second pmos transistor, a first nmos transistor, a second nmos transistor, a first resistor, a second resistor and a first capacitor, wherein a drain of the first pmos transistor is connected to one end of the first resistor, a gate and a source of the first pmos transistor are connected to a source of the second pmos transistor and one end of the first capacitor, a gate of the second pmos transistor is connected to a gate of the first nmos transistor and one end of the second resistor, a drain of the second pmos transistor is connected to a drain of the first nmos transistor and a gate of the second nmos transistor, a source of the first nmos transistor is grounded, a source of the second nmos transistor is grounded, the other ends of the first resistor and the second resistor are respectively connected to a source voltage, and the other end of the first capacitor is connected to the first level shift circuit, the second level shift circuit, the third level shift circuit, and the third level shift circuit, The first driving circuit, the second driving circuit and the source electrode of the pull-down tube are connected.

The power supply voltage detection circuit has the beneficial effects that: the voltage state of the detection circuit reflects the initial state when an audio signal is input and the state when the power supply voltage is 0, and the uncertain level state caused by factors such as insufficient voltage level or noise interference of other core circuits is avoided.

Preferably, the first level shift circuit, the second level shift circuit and the third level shift circuit are the same level shift circuit, and the level shift circuit includes a seventh pmos transistor, an eighth pmos transistor, a ninth pmos transistor, a tenth pmos transistor, a seventh nmos transistor, an eighth nmos transistor, a ninth nmos transistor, a tenth nmos transistor, a fourth resistor and an inverter;

a source of the seventh pmos transistor, a source of the eighth pmos transistor, a source of the ninth pmos transistor, and a source of the tenth pmos transistor are connected, a gate of the seventh pmos transistor is connected to a drain of the eighth pmos transistor, a drain of the eighth nmos transistor is connected to a gate of the ninth pmos transistor, a drain of the seventh nmos transistor, and a gate of the eighth pmos transistor are connected to a gate of the tenth pmos transistor, a drain of the ninth pmos transistor and a drain of the ninth nmos transistor are connected to a gate of the tenth nmos transistor, a drain of the tenth pmos transistor, and a drain of the tenth nmos transistor are connected to a gate of the ninth nmos transistor, a gate of the seventh nmos transistor is connected to an input terminal of the fourth resistor, an input terminal of the inverter, a source of the eighth pmos transistor is connected to a source of the ninth pmos transistor, and a source of the tenth pmos transistor are connected to a gate of the ninth pmos transistor, a gate of the seventh nmos transistor is connected to a gate of the fourth resistor, an input terminal of the inverter, and a source of the eighth nmos transistor are connected to ground, and the source electrode of the ninth nmos tube is connected with the source electrode of the tenth nmos tube, and the other end of the fourth resistor is connected with a power supply voltage.

The level shift circuit has the advantages that: a transition between higher and lower voltages in the overall circuit is achieved.

According to the above technical solution, compared with the prior art, the utility model provides a pair of no consumption analog switch with voltage processing function has following effect:

the input and output of the analog switch circuit are completely symmetrical and can be conducted in two directions, the switch tube has the characteristic of transmitting positive and negative voltage signals, the switch tube can be rapidly turned off after the power supply fails, the switch tube blocks the transmission of the positive and negative voltage signals of the input end, the isolation of the switch under the power supply voltage power-down state is greatly improved, and the analog switch has no static power consumption.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic diagram of an analog switch provided by the present invention;

fig. 2 is a circuit diagram of the power supply voltage detection provided by the present invention;

fig. 3 is a first level shift circuit diagram provided by the present invention;

FIG. 4 is a diagram of a high voltage selection circuit according to the present invention;

FIG. 5 is a diagram of a low voltage selection circuit according to the present invention;

FIG. 6 is a schematic diagram of a pmos substrate select circuit provided by the present invention;

fig. 7 is a drawing of an nmos substrate selection circuit provided by the present invention;

FIG. 8 is a schematic diagram of a voltage port for power-up and power-down of a circuit according to the present invention;

fig. 9 is a schematic diagram of the present invention when an audio signal is input;

FIG. 10 is a schematic diagram illustrating the circuit according to the present invention when the power supply voltage is 0;

in fig. 1: 11-a first switch tube, 12-a second switch tube, 13-a pull-up tube, 14-a pull-down tube 109-a pmos substrate selection circuit, 110-an mos substrate selection circuit, 111-a logic control circuit, 114-a first drive circuit, 115-a second drive circuit, 102-a first level shift circuit, 112-a second level shift circuit, 113-a third level shift circuit, 101-a power supply voltage detection circuit, 107-a high voltage selection circuit, 108-a low voltage selection circuit, 103-a first voltage port, 104-a second voltage port, 105-a high voltage selection output port and 106-a low voltage selection output port.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, an embodiment of the present invention discloses a non-power consumption analog switch with voltage processing function, including:

a first switching tube 11;

a first driving circuit 114, wherein the driving circuit 114 is connected with the gate of the first switching tube 11;

a pull-up tube 13, wherein a drain of the pull-up tube 13 is connected with the first driving circuit 114 and a grid electrode of the first switch tube 11;

a drain of the second switching tube 12 is connected with a source of the first switching tube 11, and a source of the second switching tube 12 is connected with a drain of the first switching tube 11;

the second driving circuit 115, the second driving circuit 115 is connected with the grid of the second switching tube 12;

a pull-down tube 14, wherein the drain of the pull-down tube 14 is connected with the second driving circuit 115 and the gate of the second switch tube 12;

the first level shift circuit 102, the first level shift circuit 102 is respectively connected with the grid of the pull-up tube 13 and the grid of the pull-down tube 14;

a second level shift circuit 112, wherein the second level shift circuit 112 is connected to the first driving circuit 114 and the first level shift circuit 102;

a third level shift circuit 113, the third level shift circuit 113 being connected to the second driver circuit 115, the first level shift circuit 102, and the second level shift circuit 112;

a logic control circuit 111, wherein the logic control circuit 111 is connected to the second level shift circuit 112 and the third level shift circuit 113 respectively;

the power supply voltage detection circuit 101, and the power supply voltage detection circuit 101 are connected to the first level shift circuit 102, the second level shift circuit 112, and the third level shift circuit 113, respectively.

In a specific embodiment, the source of the pull-up transistor 13 is a high voltage output terminal, and the high voltage output terminal is connected to the first driving circuit 114, the second driving circuit 115, the first level shifting circuit 102, the second level shifting circuit 112, and the third level shifting circuit 113.

In one embodiment, the source of the pull-down transistor 14 is a low voltage output terminal, and the low voltage output terminal is connected to the first driving circuit 114, the second driving circuit 115, the first level shifting circuit 102, the second level shifting circuit 112, and the third level shifting circuit 113.

Specifically, in a specific embodiment, referring to fig. 2, the power voltage detection circuit 101 includes a first pmos transistor 21, a second pmos transistor 22, a first nmos transistor 23, a second nmos transistor 24, a first resistor 25, a second resistor 26, and a first capacitor 27, wherein a drain of the first pmos transistor 21 is connected to one end of the first resistor 25, a gate and a source of the first pmos transistor 21 are connected to one end of a source capacitor 27 of the second pmos transistor 22, a gate of the second pmos transistor 22 is connected to a gate of the first nmos transistor 23 and one end of the second resistor 26, a drain of the second pmos transistor 22 is connected to a drain of the first nmos transistor 23 and a gate of the second nmos transistor 24, a source of the first nmos transistor 23 is grounded, a source of the second nmos transistor 24 is grounded, another ends of the first resistor 25 and the second resistor 26 are connected to a power voltage, and another ends of the capacitor 27 are connected to a first level shift circuit, a second level shift circuit, and a third level shift circuit, The first driving circuit, the second driving circuit, and the source of the pull-down tube are connected to form a low voltage selection output port 106.

In a specific embodiment, the first level shift circuit 102, the second level shift circuit 112, and the third level shift circuit 113 are the same level shift circuit, and referring to fig. 3, the level shift circuit includes a seventh pmos transistor 31, an eighth pmos transistor 32, a ninth pmos transistor 33, a tenth pmos transistor 34, a seventh nmos transistor 35, an eighth nmos transistor 36, a ninth nmos transistor 37, a tenth nmos transistor 38, a fourth resistor 39, and an inverter 310;

specifically, the source of the seventh pmos transistor 31, the source of the eighth pmos transistor 32, the source of the ninth pmos transistor 33 and the source of the tenth pmos transistor 34 are connected, the gate of the seventh pmos transistor 31 is connected to the drain of the eighth pmos transistor 32, the drain of the eighth nmos transistor 36 is connected to the gate of the ninth pmos transistor 33, the drain of the seventh pmos transistor 31, the drain of the seventh nmos transistor 35, the gate of the eighth pmos transistor 32 is connected to the gate of the tenth pmos transistor 34, the drain of the ninth pmos transistor 33 and the drain of the ninth nmos transistor 37 are connected to the gate of the tenth nmos transistor 38, the drain of the tenth pmos transistor 34 and the drain of the tenth nmos transistor 38 are connected to the gate of the ninth nmos transistor 37, the gate of the seventh nmos transistor 35 is connected to one end of the fourth resistor 39, the input terminal of the inverter 310, the source of the eighth pmos transistor 36 is connected to the source of the eighth pmos transistor 35, the source of the ninth pmos transistor 36, the ninth nmos transistor 36 is connected to the source of the ninth pmos transistor 37, the ninth nmos transistor 37, the other end of the fourth resistor 39 is connected to the supply voltage.

In a specific embodiment, referring to fig. 4, the high voltage selection circuit 107 further includes a high voltage selection circuit 107, where the high voltage selection circuit 107 includes a first voltage port 103, a second voltage port 104, and a high voltage selection output port 105, the first voltage port 103 is connected to the source of the first switch tube 11 and the drain of the second switch tube 12, the second voltage port 104 is connected to the drain of the first switch tube 11 and the gate of the second switch tube 12, and the high voltage selection output port 105 is connected to the first level shift circuit 102, the second level shift circuit 112, the third level shift circuit 113, the first driving circuit 114, the second driving circuit 115, and the source of the pull-up tube 13;

specifically, the high voltage selection circuit 107 comprises a third pmos transistor 41, a fourth pmos transistor 42, a fifth pmos transistor 43, a sixth pmos transistor 44, a third resistor 45, a first voltage port 103, a second voltage port 104, and a high voltage selection output port 105; the drain of the third pmos transistor 41 is connected to the first voltage port 103 and the gate of the fourth pmos transistor 42, the gate of the third pmos transistor 41 is connected to the drain of the fourth pmos transistor 42 and the second voltage port 104, the source of the third pmos transistor 41 is connected to the source of the fourth pmos transistor 42, the drain of the fifth pmos transistor 43 and the gate of the sixth pmos transistor 44, the gate of the fifth pmos transistor 43 is connected to the drain of the sixth pmos transistor 44 and one end of the third resistor 45, the source of the fifth pmos transistor 43 is connected to the source of the sixth pmos transistor 44, the substrate of the sixth pmos transistor 44 and the high voltage selection output port 105, and the other end of the third resistor 45 is connected to the source voltage.

Specifically, the voltage selected by the high voltage selection circuit 107 is the highest voltage between the power supply voltage and the first switching tube and the second switching tube.

In a specific embodiment, referring to fig. 5, the low voltage selection circuit 108 is further included, the low voltage selection circuit 108 includes a first output port 103, a second output port 104, and a low voltage selection output port 106, the first voltage port 103 is connected to the high voltage selection circuit 107, the source of the first switch tube 11, and the drain of the second switch tube 12, the second voltage port 104 is connected to the high voltage selection circuit 107, the drain of the first switch tube 11, and the gate of the second switch tube 12, and the low voltage selection output port 106 is connected to the first level shift circuit 102, the second level shift circuit 112, the third level shift circuit 113, the first driving circuit 114, the second driving circuit 115, and the source of the pull-up tube 13;

specifically, the low-voltage selection circuit 108 comprises a third nmos tube 51, a fourth nmos tube 52, a fifth nmos tube 53, a sixth nmos tube 54, a first voltage port 103, a second voltage port 104 and a low-voltage selection output port 106; the drain of the third nmos tube 51 is connected to the first voltage port 103 and the gate of the fourth nmos tube 52, the gate of the third nmos tube 51 is connected to the drain of the fourth nmos tube 52 and the second voltage port 104, the source of the third nmos tube 50 is connected to the source of the fourth nmos tube 52, the drain of the fifth nmos tube 53 and the gate of the sixth nmos tube 54, the gate of the fifth nmos tube 53 is connected to the drain of the sixth nmos tube 54, and the source of the fifth nmos tube 53 is connected to the source of the sixth nmos tube 54 and the low voltage selection output port 106.

Specifically, the voltage selected by the low voltage selection circuit is the grounding voltage and the lowest voltage between the first switching tube and the second switching tube.

In one embodiment, referring to fig. 6, a pmos substrate selection circuit 109 is further included, the pmos substrate selection circuit 109 is connected to the drain, gate and first voltage port 103 of the first switch tube 11, the drain, gate and second voltage port 104 of the second switch tube;

specifically, the pmos substrate selection circuit 109 includes: an eleventh pmos tube 61, a twelfth pmos tube 62, a first voltage port 103, a second voltage port 104; the gate of the eleventh pmos transistor 61 is connected to the second input port and the drain of the twelfth pmos transistor, and the source of the eleventh pmos transistor is connected to the source of the twelfth pmos transistor.

In a specific embodiment, referring to fig. 7, the nmos substrate selection circuit 110 is further included, where the nmos substrate selection circuit 110 is connected to the drain, gate and first voltage port 103 of the first switch tube 11, and the drain, gate and second voltage port 104 of the second switch tube;

specifically, nmos substrate selection circuit 110 includes: a thirteenth nmos tube 71, a fourteenth nmos tube 72, a first voltage port 103, a second voltage port 104; the gate of the thirteenth nmos tube 71 is connected to the first voltage port 103 and the drain of the fourteenth nmos tube 72, and the source of the thirteenth nmos tube 71 is connected to the source of the fourteenth nmos tube 72.

The utility model discloses specific theory of operation as follows:

when the first switch tube 11 and the second switch tube 12 transmit positive voltage, the voltage at the end of the first voltage port 103 is greater than the voltage at the end of the second voltage port 104, so the twelfth pmos tube 62 in the pmos substrate selection circuit 109 is closed, the eleventh pmos tube 61 is opened, the first voltage port 103 with higher voltage is selected as the substrate voltage of the first switch tube 11, the voltage at the end of the output port 601 in the pmos substrate selection circuit 109 is equal to the voltage at the end of the first voltage port 103, the thirteenth nmos tube 71 in the nmos substrate selection circuit 110 is closed, the fourteenth nmos tube 72 is opened, the second voltage port 104 with lower voltage is selected as the substrate of the second switch tube 12, and the voltage at the end of the output port 701 in the nmos substrate selection circuit 110 is equal to the voltage at the end of the second voltage port 104;

when the first switch tube 11 and the second switch tube 12 transmit positive and negative voltages, the voltage at the terminal of the first voltage port 103 is less than that at the terminal of the second voltage port 104, so the eleventh pmos tube 61 in the pmos-tube substrate selection circuit 109 is turned off, the twelfth pmos tube 62 is turned on, the terminal of the second voltage port 104 with higher voltage is selected as the substrate voltage of the first switch tube 11, the voltage at the output port 601 in the pmos-tube substrate selection circuit 109 is equal to that at the terminal of the second voltage port 104, the fourteenth nmos tube 72 in the nmos-tube substrate selection circuit 110 is turned off, the thirteenth nmos tube 71 is turned on, the terminal of the first voltage port 103 with lower voltage is selected as the substrate of the second switch tube 12, and the voltage at the output port 701 in the nmos-tube substrate selection circuit 110 is equal to that at the terminal 103 of the first voltage port 103.

The high voltage selection circuit 107 is configured as a two-stage cascade of pmos substrate selection circuits 109 that ultimately select the highest of the supply voltage, the voltage at the first voltage port 103, and the voltage at the second voltage port 104.

The high voltage selection circuit 108 is configured as a two-stage cascade of pmos substrate selection circuits 110, the final selected voltage being the lowest of GND, the voltage at the first voltage port 103, and the voltage at the second voltage port 104.

When the power supply voltage is powered on, the logic control circuit 111 controls the first switch tube and the second switch tube to be turned on and off; when the power supply voltage is turned off, the power supply voltage drops to 0, the first voltage port 103 is used as an input terminal to input an audio signal, the second voltage port 104 is used as an output terminal, the input/output terminal 103/104, and the voltages of the output ports 105 and 106 are shown in fig. 3, the maximum input voltage of the audio signal is VMAX, the minimum input voltage is VMIN, the maximum output voltage of the high-voltage selection output port 105 is VMAX, the minimum output voltage is 0, the maximum output voltage of the high-voltage selection output port 106 is 0V, and the minimum output voltage is VMIN.

When an audio signal is input, in an initial state, the voltage across the first capacitor 27 is 0, when the voltage across the low-voltage selection output port 106 decreases to a value below the threshold voltage VTHP of the first pmos transistor 21 and the second pmos transistor 22, due to the parasitic diodes of the first pmos transistor 21 and the second pmos transistor 22, the voltage at the a point can only decrease to VTHP, after one period of the audio signal, the voltage difference across the capacitor 27 is raised to VMAX | -VTHP |, and when the voltage across the low-voltage selection output port 106 is 0, the voltage at the a point of the upper plate a of the first capacitor 27 is VMAX | -VTHP |, as shown in fig. 9, when the voltage at the a point of the upper plate a of the capacitor 27 is VMAX | -VTHP |, since the power voltage is 0, the gate voltage of the second nmos transistor 24 is also VMAX | -VTHP |, when VMAX- | VTHP | is greater than the gate voltage VTHN of the second nmos tube 24, the second nmos tube 24 will turn on, and the voltage at the power voltage detection output port 201 is forced to GND.

When the power voltage is 0, the voltages at the output port 105 and the output port 106 in the first level shift circuit 102 are shown in fig. 8, the voltage at the output port 201 in the first level shift circuit 102 is forced to 0 due to the action of the second nmos transistor 24 in the power voltage detection circuit, and the voltages at the output port 304 and the output port 305 in the level shift circuit 201 are shown in fig. 10 according to the operating principle of the level shift circuit, wherein the output port 305 in the level shift circuit 201 is connected with the gate of the pull-up transistor 13, the output port 304 is connected with the gate of the pull-down transistor 14, and due to the actions of the pull-up transistor 13 and the pull-down transistor 14, the voltage at the gate of the first switching transistor 11 is always consistent with the voltage at the output port 105, and the gate voltage of the switching transistor 12 is always consistent with the voltage at the output. Because the voltage of the grid electrode of the switch tube 11 is always not lower than the input voltage of the 103 terminal, the voltage of the grid electrode of the second switch tube 12 is always not higher than the input voltage of the 103 terminal, and the first switch tube 11 and the second switch tube 12 are always kept in an off state.

The output terminal 201 of the power supply voltage detection circuit 101 is connected to the input terminals of the second level shift circuit 112 and the third level shift circuit 113, when the power supply voltage is turned off, the second level shift circuit 112 outputs a voltage not lower than the voltage at the first voltage port 103, and the third level shift circuit 113 outputs a voltage not higher than the voltage at the first voltage port 103.

When the whole circuit normally works, the second nmos tube 24 in the power supply voltage detection circuit 101 is in an off state, the 201 end in the first level shift circuit 102 has no pull-down action, the 304 end voltage output is a low level, namely, the lowest voltage in the first voltage port 103, the second voltage port 104 and the GND, the pull-down tube 14 is in an off state, the 305 end output is a high level, namely, the highest voltage in the first voltage port 103, the second voltage port 104 and the power supply voltage, the pull-up tube 13 is in an off state, the states of the first switch tube 11 and the second switch tube 12 are controlled by the logic control circuit 111, and the whole circuit does not have static power consumption during working.

Can draw the conclusion, the utility model provides a no consumption analog switch with voltage processing function, the switch tube can turn off rapidly after the power down, blocks the transmission of input terminal positive and negative voltage signal, has improved the isolation of switch tube under the power down state of mains voltage greatly to this analog switch does not have static consumption.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (5)

1. A power consumption free analog switch with voltage handling capability, comprising:

a first switching tube (11);

the first driving circuit (114), the first driving circuit (114) is connected with the grid electrode of the first switching tube (11);

the drain electrode of the pull-up tube (13) is connected with the first driving circuit (114) and the grid electrode of the first switch tube (11);

the drain of the second switching tube (12) is connected with the source of the first switching tube (11), and the source of the second switching tube (12) is connected with the drain of the first switching tube (11);

a second driving circuit (115), wherein the second driving circuit (115) is connected with the grid electrode of the second switching tube (12);

a pull-down tube (14), wherein a drain of the pull-down tube (14) is connected with the second drive circuit (115) and a grid electrode of the second switch tube (12);

the first level shift circuit (102), the first level shift circuit (102) is respectively connected with the grid of the pull-up tube (13) and the grid of the pull-down tube (14);

a second level shift circuit (112), the second level shift circuit (112) being connected to the first drive circuit (114) and the first level shift circuit (102);

a third level shift circuit (113), the third level shift circuit (113) being connected to the second drive circuit (115), the first level shift circuit (102), and the second level shift circuit (112);

a logic control circuit (111), wherein the logic control circuit (111) is respectively connected with the second level shift circuit (112) and the third level shift circuit (113);

and a power supply voltage detection circuit (101), wherein the power supply voltage detection circuit (101) is respectively connected with the first level shift circuit (102), the second level shift circuit (112) and the third level shift circuit (113).

2. The power consumption free analog switch with voltage processing function according to claim 1, wherein the source of the pull-up transistor (13) is a high voltage output terminal, and the high voltage output terminal is connected to the first driving circuit (114), the second driving circuit (115), the first level shifting circuit (102), the second level shifting circuit (112) and the third level shifting circuit (113).

3. The power consumption free analog switch with voltage processing function of claim 1, wherein the source of the pull-down tube (14) is a low voltage output terminal, and the low voltage output terminal is connected to the first driving circuit (114), the second driving circuit (115), the first level shifting circuit (102), the second level shifting circuit (112) and the third level shifting circuit (113).

4. The power consumption-free analog switch with the voltage processing function according to claim 1, wherein the power supply voltage detection circuit (101) comprises a first pmos transistor, a second pmos transistor, a first nmos transistor, a second nmos transistor, a first resistor, a second resistor and a first capacitor, wherein a drain of the first pmos transistor is connected to one end of the first resistor, a gate and a source of the first pmos transistor are connected to a source of the second pmos transistor and one end of the first capacitor, a gate of the second pmos transistor is connected to a gate of the first nmos transistor and one end of the second resistor, a drain of the second pmos transistor is connected to a drain of the first nmos transistor and a gate of the second nmos transistor, a source of the first nmos transistor is grounded, a source of the second nmos transistor is grounded, and the other end of the first resistor and the other end of the second resistor are connected to a source voltage, the other end of the first capacitor is connected with the first level shift circuit (102), the second level shift circuit (112), the third level shift circuit (113), the first drive circuit (114), the second drive circuit (115) and the source electrode of the pull-down tube (14).

5. The power consumption-free analog switch with the voltage processing function is characterized in that the first level shift circuit (102), the second level shift circuit (112) and the third level shift circuit (113) are the same level shift circuit, and the level shift circuit comprises a seventh pmos transistor, an eighth pmos transistor, a ninth pmos transistor, a tenth pmos transistor, a seventh nmos transistor, an eighth nmos transistor, a ninth nmos transistor, a tenth nmos transistor, a fourth resistor and an inverter;

a source of the seventh pmos transistor, a source of the eighth pmos transistor, a source of the ninth pmos transistor, and a source of the tenth pmos transistor are connected, a gate of the seventh pmos transistor is connected to a drain of the eighth pmos transistor, a drain of the eighth nmos transistor is connected to a gate of the ninth pmos transistor, a drain of the seventh nmos transistor, and a gate of the eighth pmos transistor are connected to a gate of the tenth pmos transistor, a drain of the ninth pmos transistor and a drain of the ninth nmos transistor are connected to a gate of the tenth nmos transistor, a drain of the tenth pmos transistor, and a drain of the tenth nmos transistor are connected to a gate of the ninth nmos transistor, a gate of the seventh nmos transistor is connected to an input terminal of the fourth resistor, an input terminal of the inverter, a source of the eighth pmos transistor is connected to a source of the ninth pmos transistor, and a source of the tenth pmos transistor are connected to a gate of the ninth pmos transistor, a gate of the seventh nmos transistor is connected to a gate of the fourth resistor, an input terminal of the inverter, and a source of the eighth nmos transistor are connected to ground, and the source electrode of the ninth nmos tube is connected with the source electrode of the tenth nmos tube, and the other end of the fourth resistor is connected with a power supply voltage.

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