CN110247651B - Positive-voltage-to-negative-voltage logic circuit based on GaAs HEMT technology - Google Patents
Positive-voltage-to-negative-voltage logic circuit based on GaAs HEMT technology Download PDFInfo
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 37
- 238000005516 engineering process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000006243 chemical reaction Methods 0.000 claims abstract description 13
- 230000003139 buffering effect Effects 0.000 claims description 4
- 238000007493 shaping process Methods 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
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Abstract
The invention provides a positive-voltage-to-negative-voltage logic circuit based on a GaAs HEMT (high Electron mobility transistor) process, which can convert an input positive-voltage logic signal into two negative-voltage logic signals with complementary outputs (one in phase and one in phase) through the structural design of an input level shift circuit unit, a buffer circuit unit, an in-phase logic output circuit unit and an opposite-phase logic output circuit unit, and has the advantages of simple conversion structure and high conversion efficiency; and each circuit unit is designed based on the GaAs HEMT technology, so that the positive-voltage-to-negative-voltage logic circuit can be integrated with a single-chip microwave integrated circuit direct unit chip such as a radio frequency switch, a numerical control attenuator, a numerical control phase shifter and the like, the simplification and miniaturization of the application of the single-chip microwave integrated circuit system are promoted, and the power consumption of the single-chip microwave integrated circuit system is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit design, in particular to a positive-voltage-to-negative-voltage logic circuit based on a GaAs HEMT process.
Background
In control type monolithic microwave integrated circuits such as a radio frequency switch, a numerical control attenuator, a numerical control phase shifter and the like, a control logic circuit is an indispensable unit circuit and is used for realizing digital logic control functions such as switch on-off, attenuation/phase shift switching and the like. Because the GaAs-based HEMT transistor has the remarkable characteristics of high characteristic frequency, high switching speed, good noise performance, high output power and the like, the single-chip microwave integrated circuit currently mainstream adopts the GaAs HEMT technology.
As shown in FIG. 1, the turn-on threshold of the enhanced GaAs-based HEMT transistor is positive, and Vgs is more than or equal to 1V and is enough to turn on the drain and source, and Vgs is less than or equal to 0V and turns off the drain and source; the starting threshold of the depletion type GaAs-based HEMT transistor is negative voltage, and Vgs=0V is enough to enable the drain source to be started and enable the drain source to be turned off only when the Vgs is less than or equal to-1V. The current control type monolithic microwave integrated circuit basically adopts a depletion type GaAs-based HEMT transistor, so that the digital control signal of the current control type monolithic microwave integrated circuit can only adopt negative pressure logic signals (such as 0V/On, -3V/Off). In practical applications, the control signal provided by the system is typically a positive pressure logic signal (e.g., 3V/On, 0V/Off), and if negative pressure logic control is to be implemented, only a logic conversion device based On CMOS technology can be additionally added in the system, the positive pressure logic signal is converted into a negative pressure logic signal, and then the negative pressure logic signal is input to the control end of the monolithic microwave integrated circuit. However, because the GaAs HEMT process is incompatible with the CMOS process, single chip integration cannot be realized, and only secondary integration is realized, so that the complexity and the volume of the system are increased, the cost is increased, and meanwhile, the power consumption of the system is increased due to the newly added device.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention aims to provide a technical solution for converting a positive voltage logic signal into a negative voltage logic signal based on GaAs HEMT technology, so that a positive voltage to negative voltage logic conversion circuit can be integrated with a monolithic microwave integrated circuit unit chip directly while effectively converting.
To achieve the above and other related objects, the present invention provides a positive-to-negative-voltage logic circuit based on GaAs HEMT process, comprising:
the input level shift circuit unit performs level shift on the input positive-pressure logic signal to obtain a first negative-pressure logic signal;
the buffer circuit unit is used for buffering and shaping the first negative pressure logic signal to obtain a second negative pressure logic signal;
the in-phase logic output circuit unit is used for carrying out phase adjustment on the second negative pressure logic signal to obtain a third negative pressure logic signal, wherein the third negative pressure logic signal is in phase with the positive pressure logic signal;
The inverting logic output circuit unit is used for carrying out phase adjustment on the second negative pressure logic signal to obtain a fourth negative pressure logic signal, and the fourth negative pressure logic signal is inverted with the positive pressure logic signal;
Optionally, the input level shift circuit unit, the buffer circuit unit, the in-phase logic output circuit unit and the anti-phase logic output circuit unit are all circuit units based on GaAs HEMT process.
Optionally, the input level shift circuit unit includes:
The positive voltage logic signal is connected with the positive electrode of a first diode, the first diode and the rest diodes are sequentially connected in series in the same direction, and the negative electrode of the last diode is connected with a first node;
one end of the first resistor is connected with the first node, and the other end of the first resistor is connected with a negative power supply end;
the first node is used as an output end of the input level shift circuit unit, and the signal at the first node is the first negative voltage logic signal.
Optionally, a plurality of the diodes are GaAs based diodes.
Optionally, the buffer circuit unit includes a second resistor, a third resistor and a first HEMT transistor; one end of the second resistor is connected with the first node, and the other end of the second resistor is connected with the grid electrode of the first HEMT transistor; the source electrode of the first HEMT transistor is connected with the negative power supply end, and the drain electrode of the first HEMT transistor is connected with the second node; one end of the third resistor is connected with the second node, and the other end of the third resistor is connected with the ground;
The second node is used as an output end of the buffer circuit unit, and a signal at the second node is the second negative pressure logic signal.
Optionally, the in-phase logic output circuit unit includes a fourth resistor and a second HEMT transistor; the grid electrode of the second HEMT transistor is connected with the second node, the source electrode of the second HEMT transistor is connected with the negative power supply end, and the drain electrode of the second HEMT transistor is connected with the third node; one end of the fourth resistor is connected with the third node, and the other end of the fourth resistor is connected with the ground;
The third node is used as the output end of the in-phase logic output circuit unit, and the signal at the third node is the third negative-voltage logic signal.
Optionally, the inverting logic output circuit unit includes a fifth resistor, a sixth resistor, a third HEMT transistor, and a fourth HEMT transistor; the grid electrode of the third HEMT transistor is connected with the second node, the source electrode of the third HEMT transistor is connected with the negative power supply end, and the drain electrode of the third HEMT transistor is connected with the fourth node; one end of the fifth resistor is connected with the fourth node, and the other end of the fifth resistor is connected with the ground; the grid electrode of the fourth HEMT transistor is connected with the fourth node, the source electrode of the fourth HEMT transistor is connected with the negative power supply end, and the drain electrode of the fourth HEMT transistor is connected with the fifth node; one end of the sixth resistor is connected with the fifth node, and the other end of the sixth resistor is connected with the ground;
The fifth node is used as the output end of the inverting logic output circuit unit, and the signal at the fifth node is the fourth negative voltage logic signal.
Optionally, the negative power supply terminal provides a negative voltage level, and an absolute value of the negative voltage level is equal to a high level of the positive voltage logic signal.
Optionally, the first HEMT transistor, the second HEMT transistor, the third HEMT transistor, and the fourth HEMT transistor are all enhancement HEMT transistors.
Optionally, the resistance values of the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are all greater than or equal to a first threshold.
As described above, the positive-to-negative-pressure logic circuit has the following beneficial effects:
1) Through the structural design of the input level shift circuit unit, the buffer circuit unit, the in-phase logic output circuit unit and the anti-phase logic output circuit unit, the input positive-pressure logic signals can be converted into two negative-pressure logic signals (one is in phase with the positive-pressure logic signals and the other is in anti-phase with the positive-pressure logic signals) with complementary outputs, the conversion structure is simple, and the conversion efficiency is high;
2) The positive-voltage-to-negative-voltage logic circuit is based on the GaAs HEMT technology and compatible with the GaAs HEMT technology, so that the positive-voltage-to-negative-voltage logic circuit can be directly integrated with a unit chip of the monolithic microwave integrated circuit, the simplification and miniaturization of the application of the monolithic microwave integrated circuit system are promoted, and the power consumption is reduced.
Drawings
Fig. 1 shows a schematic diagram of the drain-source current Ids of two HEMT tubes as a function of the gate-source voltage Vgs.
Fig. 2 is a schematic diagram of a logic circuit for converting positive voltage to negative voltage according to a first embodiment of the invention.
Fig. 3 is a schematic diagram of a logic circuit for converting positive voltage to negative voltage in a second embodiment of the invention.
Description of the reference numerals
1. Input level shift circuit unit
2. Buffer circuit unit
3. In-phase logic output circuit unit
4. Inverting logic output circuit unit
D1 First diode
D2 Second diode
D3 Third diode
D4 Fourth diode
D5 Fifth diode
D6 Sixth diode
D7 Seventh diode
D8 Eighth diode
R1 first resistor
R2 second resistor
R3 third resistor
R4 fourth resistor
R5 fifth resistor
R6 sixth resistor
T1 first HEMT tube
T2 second HEMT tube
T3 third HEMT tube
T4 fourth HEMT tube
Vin positive pressure logic signal
V1 first negative voltage logic signal
V2 second negative pressure logic signal
Vout+third negative voltage logic signal
Vout-fourth negative voltage logic signal
V d fourth node signal
V EE negative power supply terminal
GND ground
A first node
B second node
C third node
D fourth node
E fifth node
Detailed Description
As mentioned in the foregoing background, the existing control type monolithic microwave integrated circuits basically use depletion mode HEMT transistors as switches, and their corresponding digital control signals can only generally use negative pressure logic signals (e.g. 0V/On, -3V/Off), while in practical product applications, the control signals provided by the system are generally positive pressure logic signals (e.g. 3V/On, 0V/Off), if negative pressure logic signal control is to be implemented, only logic conversion devices based On CMOS technology can be additionally added in the system, and the positive pressure logic signals are converted into negative pressure logic signals before being input to the corresponding control terminals.
The GaAs HEMT process is incompatible with the CMOS process, single chip integration cannot be realized, and the integration can be realized only twice, so that the complexity and the volume of the system are increased, the cost is increased, and in addition, the power consumption of the system is increased due to the fact that a new device is added.
Based on the above, the invention provides a positive-voltage-to-negative-voltage logic circuit based on a GaAs HEMT process, which comprises an input level shift circuit unit, a buffer circuit unit, an in-phase logic output circuit unit and an opposite-phase logic output circuit unit which are sequentially connected, wherein the input level shift circuit unit preliminarily converts an input positive-voltage logic signal into a negative-voltage signal through level shift, the negative-voltage signal firstly increases driving capability through the buffer circuit unit, then carries out phase adjustment through the in-phase logic output circuit unit and the opposite-phase logic output circuit unit, and finally outputs the negative-voltage logic signal to obtain complementation.
Therefore, the process of the logic circuit is compatible with the GaAs HEMT process of the monolithic microwave integrated circuit system while the positive-pressure logic signal is converted into the negative-pressure logic signal, so that the logic circuit can be directly integrated with a unit chip of the monolithic radio frequency microwave integrated circuit, the simplification and miniaturization of the application of the monolithic microwave integrated circuit system are promoted, and the power consumption is reduced.
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The structures, proportions, sizes, etc. shown in the drawings attached hereto are for illustration purposes only and are not intended to limit the scope of the invention, which is defined by the claims, but rather by the claims.
Example 1
In detail, as shown in fig. 2, the positive-to-negative-voltage logic circuit based on GaAs HEMT process includes:
the input positive-pressure logic signal Vin is subjected to level shift by the input level shift circuit unit 1 to obtain a first negative-pressure logic signal V1;
The buffer circuit unit 2 is used for buffering and shaping the first negative pressure logic signal V1 to obtain a second negative pressure logic signal V2;
The in-phase logic output circuit unit 3 performs phase adjustment on the second negative pressure logic signal V2 to obtain a third negative pressure logic signal Vout+ which is in-phase with the positive pressure logic signal Vin;
The inverting logic output circuit unit 4 performs phase adjustment on the second negative pressure logic signal V2 to obtain a fourth negative pressure logic signal Vout-, and the fourth negative pressure logic signal Vout-is inverted with the positive pressure logic signal Vin;
The input level shift circuit unit 1, the buffer circuit unit 2, the in-phase logic output circuit unit 3 and the anti-phase logic output circuit unit 4 are all circuit units based on the GaAs HEMT process.
The embodiment of the invention converts a positive-pressure logic signal Vin of 3V/On and 0V/Off (namely, the high level is 3V and the low level is 0V) into a negative-pressure logic signal of 0V/On and 3V/Off (namely, the high level is 0V and the low level is-3V).
In more detail, as shown in fig. 2, the input level shift circuit unit 1 includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, and a first resistor R1, wherein the positive voltage logic signal Vin is connected to the positive electrode of the first diode D1, the first diode D1 and the remaining diodes are sequentially connected in parallel, that is, the negative electrode of the first diode D1 is connected to the positive electrode of the second diode D2, the negative electrode of the second diode D2 is connected to the positive electrode of the third diode D3, the negative electrode of the third diode D3 is connected to the positive electrode of the fourth diode D4, the negative electrode of the fourth diode D4 is connected to the positive electrode of the fifth diode D5, and the negative electrode of the fifth diode D5 is connected to the first node a; one end of the first resistor R1 is connected with the first node a, and the other end is connected with the negative power supply end V EE.
The positive electrode of the first diode D1 is used as an input end (also an input end of the whole circuit) of the input level shift circuit unit 1, the first node a is used as an output end of the input level shift circuit unit 1, and the signal at the first node a is the first negative pressure logic signal V1.
Further, the negative power supply terminal V EE provides a negative voltage level, the absolute value of the negative voltage level is equal to the high level of the positive voltage logic signal Vin, and in the embodiment of the present invention, the high level of the positive voltage logic signal Vin is 3V, and the negative voltage level provided by the negative power supply terminal VEE is-3V.
Optionally, the first diode D1, the second diode D2, the third diode D3, the fourth diode D4 and the fifth diode D5 are GaAs-based diodes, and the corresponding forward conduction voltage drop V T is 0.7V. It can be understood that the first diode D1, the second diode D2, the third diode D3, the fourth diode D4 and the fifth diode D5 may be GaAs-based diodes of different types, the forward conduction voltage drop V T may be different, the number of diodes may be correspondingly changed, and the number of diodes may be appropriately selected according to circumstances, which is not described herein.
In more detail, as shown in fig. 2, the buffer circuit unit 2 includes a second resistor R2, a third resistor R3, and a first HEMT transistor T1; one end of the second resistor R2 is connected with the first node a, and the other end of the second resistor R2 is connected with the grid electrode of the first HEMT transistor T1; the source electrode of the first HEMT transistor T1 is connected with the negative power supply end VEE, and the drain electrode of the first HEMT transistor T1 is connected with the second node b; one end of the third resistor R3 is connected to the second node b, and the other end of the third resistor R3 is grounded GND.
The first node a is used as an input end of the buffer circuit unit 2, the second node b is used as an output end of the buffer circuit unit 2, and the signal at the second node b is a second negative pressure logic signal V2.
In more detail, the in-phase logic output circuit unit 3 includes a fourth resistor R4 and a second HEMT transistor T2; the grid electrode of the second HEMT transistor T2 is connected with the second node b, the source electrode of the second HEMT transistor T2 is connected with the negative power supply end VEE, and the drain electrode of the second HEMT transistor T2 is connected with the third node c; one end of the fourth resistor R4 is connected to the third node c, and the other end of the fourth resistor R4 is grounded GND.
The second node b is used as an input end of the in-phase logic output circuit unit 3, the third node c is used as an output end of the in-phase logic output circuit unit 3, and a signal at the third node c is a third negative voltage logic signal Vout+.
In more detail, the inverting logic output circuit unit 4 includes a fifth resistor R5, a sixth resistor R6, a third HEMT transistor T3, and a fourth HEMT transistor T4; the grid electrode of the third HEMT transistor T3 is connected with the second node b, the source electrode of the third HEMT transistor T3 is connected with the negative power supply end V EE, and the drain electrode of the third HEMT transistor T3 is connected with the fourth node d; one end of the fifth resistor R5 is connected with the fourth node d, and the other end of the fifth resistor R5 is grounded GND; the grid electrode of the fourth HEMT transistor T4 is connected with a fourth node d, the source electrode of the fourth HEMT transistor T4 is connected with a negative power supply end VEE, and the drain electrode of the fourth HEMT transistor T4 is connected with a fifth node e; one end of the sixth resistor R6 is connected to the fifth node e, and the other end of the sixth resistor R6 is grounded GND.
The second node b is used as an input end of the inverting logic output circuit unit 4, the fifth node e is used as an output end of the inverting logic output circuit unit 4, and a signal at the fifth node e is a fourth negative voltage logic signal Vout-.
Further, the first HEMT transistor T1, the second HEMT transistor T2, the third HEMT transistor T3 and the fourth HEMT transistor T4 are all enhancement HEMT transistors; optionally, the first HEMT transistor T1, the second HEMT transistor T2, the third HEMT transistor T3 and the fourth HEMT transistor T4 are GaAs-based HEMT transistors. As shown in FIG. 1, for GaAs-based enhanced HEMT transistors, the drain-source is turned off when Vgs is less than or equal to 0, and the drain-source is turned on when Vgs is less than or equal to 1.
Further, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 are all greater than or equal to the first threshold value 10kΩ, that is, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 are all large resistors with the magnitude of 10kΩ or more.
In detail, the working principle of the positive-voltage-to-negative-voltage logic circuit is as follows:
(1) When the input positive voltage logic signal Vin is at a high level of 3V, the voltage difference between two ends of the first diode D1, the second diode D2, the third diode D3, the fourth diode D4 and the fifth diode D5 connected in series is sufficient, the first diode D1, the second diode D2, the third diode D3, the fourth diode D4 and the fifth diode D5 are all conducted, and the first negative voltage logic signal v1=3-V T ×5= -0.5V at the first node a; correspondingly, the gate-source voltage vgs=v1-V EE =2.5v of the first HEMT transistor T1, the drain-source of the first HEMT transistor T1 is turned on, the second negative-pressure logic signal v2=v EE = -3V at the second node b; the gate-source voltage vgs=v2-V EE =0v of the second HEMT transistor T2, the drain-source of the second HEMT transistor T2 is turned off, the third negative voltage logic signal vout+=gnd=0v at the third node c; the gate-source voltage vgs=v2-V EE =0v of the third HEMT transistor T3, the drain-source of the third HEMT transistor T3 is turned off, the signal at the fourth node d is vd=gnd=0v; the gate-source voltage vgs=vd-V EE =3v of the fourth HEMT transistor T4, the drain-source of the fourth HEMT transistor T4 is turned on, and the fourth negative voltage logic signal at the fifth node e is Vout- =v EE = -3V.
(2) When the input positive voltage logic signal Vin is at a low level of 0V, the voltage difference between two ends of the first diode D1, the second diode D2, the third diode D3, the fourth diode D4 and the fifth diode D5 connected in series is insufficient, and the first negative voltage logic signal v1=v EE = -3V at the first node a is cut off; correspondingly, the gate-source voltage vgs=v1-V EE =0v of the first HEMT transistor T1, the drain-source of the first HEMT transistor T1 is turned off, the second negative-pressure logic signal v2=gnd=0v at the second node b; the gate-source voltage vgs=v2-V EE =3v of the second HEMT transistor T2, the drain-source of the second HEMT transistor T2 is turned on, the third negative voltage logic signal vout+=v EE = -3V at the third node c; the gate-source voltage vgs=v2-V EE =3v of the third HEMT transistor T3, the drain-source of the third HEMT transistor T3 is turned on, the signal at the fourth node d is vd=v EE = -3V; the gate-source voltage vgs=vd-V EE =0v of the fourth HEMT transistor T4, the drain-source of the fourth HEMT transistor T4 is turned off, and the fourth negative voltage logic signal at the fifth node e is Vout- =gnd=0v.
Based on the above analysis, the positive pressure logic signal Vin of "3V/0V" is simultaneously converted into the third negative pressure logic signal vout+ of "0V/-3V" in phase and the fourth negative pressure logic signal Vout-of "-3V/0V" in phase by the positive pressure-to-negative pressure logic circuit. The positive-pressure-to-negative-pressure logic circuit is simple in structure and high in conversion efficiency, and can convert positive-pressure logic signals into two negative-pressure logic signals with the same phase and the opposite phase. The positive-voltage-to-negative-voltage logic circuit only adopts a HEMT transistor, a diode and a resistor based on a GaAs HEMT process, and does not adopt silicon-based devices such as a CMOS transistor, and the process of the positive-voltage-to-negative-voltage logic circuit is compatible with the GaAs HEMT process of the monolithic microwave integrated circuit, so that the positive-voltage-to-negative-voltage logic circuit can be directly integrated with a unit chip of the monolithic microwave integrated circuit, the simplification and miniaturization of the application of the monolithic microwave integrated circuit system are promoted, and the power consumption is reduced.
Example two
The first embodiment is directed to the conversion of the positive voltage logic signal Vin of "3V/On, 0V/Off" (i.e. the high level is 3V, the low level is 0V), while the conversion of the positive voltage logic signal Vin of other specifications is similar to the first embodiment, and the second embodiment of the invention converts the positive voltage logic signal Vin of "5V/On, 0V/Off" (i.e. the high level is 5V, the low level is 0V) into the negative voltage logic signal of "0V/On, -5V/Off" (i.e. the high level is 0V, the low level is-5V).
In detail, as shown in fig. 3, the positive-to-negative-voltage logic circuit based on GaAs HEMT process in the embodiment of the present invention also includes:
the input positive-pressure logic signal Vin is subjected to level shift by the input level shift circuit unit 1 to obtain a first negative-pressure logic signal V1;
The buffer circuit unit 2 is used for buffering and shaping the first negative pressure logic signal V1 to obtain a second negative pressure logic signal V2;
The in-phase logic output circuit unit 3 performs phase adjustment on the second negative pressure logic signal V2 to obtain a third negative pressure logic signal Vout+ which is in-phase with the positive pressure logic signal Vin;
The inverting logic output circuit unit 4 performs phase adjustment on the second negative pressure logic signal V2 to obtain a fourth negative pressure logic signal Vout-, and the fourth negative pressure logic signal Vout-is inverted with the positive pressure logic signal Vin;
The input level shift circuit unit 1, the buffer circuit unit 2, the in-phase logic output circuit unit 3 and the anti-phase logic output circuit unit 4 are all circuit units based on the GaAs HEMT process.
In more detail, as shown in fig. 3, the input level shift circuit unit 1 includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8, and a first resistor R1, wherein the positive voltage logic signal Vin is connected to the positive electrode of the first diode D1, the first diode D1 and the remaining diodes are sequentially connected in series in the same direction, that is, the negative electrode of the first diode D1 is connected to the positive electrode of the second diode D2, the negative electrode of the second diode D2 is connected to the positive electrode of the third diode D3, the negative electrode of the third diode D3 is connected to the positive electrode of the fourth diode D4, the negative electrode of the fourth diode D4 is connected to the positive electrode of the fifth diode D5, the negative electrode of the fifth diode D5 is connected to the positive electrode of the sixth diode D6, the negative electrode of the sixth diode D6 is connected to the positive electrode of the seventh diode D7, and the negative electrode of the eighth diode D7 is connected to the positive electrode of the eighth diode D8; one end of the first resistor R1 is connected with the first node a, and the other end is connected with the negative power supply end V EE.
In detail, as shown in fig. 3, the specific structures of the buffer circuit unit 2, the in-phase logic output circuit unit 3 and the inverting logic output circuit unit 4 in the embodiment of the present invention are the same as those in the first embodiment, and are not described herein again.
It should be noted that, in the embodiment of the present invention, the positive voltage logic signal Vin has a high level of 5V, and the negative voltage level provided by the negative power supply terminal VEE is correspondingly-5V.
Likewise, the working principle of the positive-voltage-to-negative-voltage logic circuit in the embodiment of the invention is as follows:
(1) When the input positive voltage logic signal Vin is at a high level of 5V, the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5, the sixth diode D6, the seventh diode D7 and the eighth diode D80 are connected in series, the voltage difference across the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5, the sixth diode D6, the seventh diode D7 and the eighth diode D8 is sufficient, and the first negative voltage logic signal v1=5-V T ×8= -0.6V at the first node a; correspondingly, the gate-source voltage vgs=v1-V EE =4.4v of the first HEMT transistor T1, the drain-source of the first HEMT transistor T1 is turned on, the second negative-pressure logic signal v2=v EE = -5V at the second node b; the gate-source voltage vgs=v2-V EE =0v of the second HEMT transistor T2, the drain-source of the second HEMT transistor T2 is turned off, the third negative voltage logic signal vout+=gnd=0v at the third node c; the gate-source voltage vgs=v2-V EE =0v of the third HEMT transistor T3, the drain-source of the third HEMT transistor T3 is turned off, the signal at the fourth node d is vd=gnd=0v; the gate-source voltage vgs=vd-V EE =5v of the fourth HEMT transistor T4, the drain-source of the fourth HEMT transistor T4 is turned on, and the fourth negative voltage logic signal at the fifth node e is Vout- =v EE = -5V.
(2) When the input positive voltage logic signal Vin is at the low level of 0V, the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5, the sixth diode D6, the seventh diode D7 and the eighth diode D8 are connected in series, the voltage difference across the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5, the sixth diode D6, the seventh diode D7 and the eighth diode D8 is not enough, and the first negative voltage logic signal v1=v EE = -5V of the first node a is cut off; correspondingly, the gate-source voltage vgs=v1-V EE =0v of the first HEMT transistor T1, the drain-source of the first HEMT transistor T1 is turned off, the second negative-pressure logic signal v2=gnd=0v at the second node b; the gate-source voltage vgs=v2-V EE =5v of the second HEMT transistor T2, the drain-source of the second HEMT transistor T2 is turned on, the third negative voltage logic signal vout+=v EE = -5V at the third node c; the gate-source voltage vgs=v2-V EE =5v of the third HEMT transistor T3, the drain-source of the third HEMT transistor T3 is turned on, the signal at the fourth node d is vd=v EE = -5V; the gate-source voltage vgs=vd-V EE =0v of the fourth HEMT transistor T4, the drain-source of the fourth HEMT transistor T4 is turned off, and the fourth negative voltage logic signal at the fifth node e is Vout- =gnd=0v.
Based on the above analysis, the positive voltage logic signal Vin of "5V/0V" is simultaneously converted into the third negative voltage logic signal vout+ of "0V/-5V" in phase and the fourth negative voltage logic signal Vout-of "-5V/0V" in phase by the positive voltage-to-negative voltage logic circuit.
It can be understood that the input level shift circuit unit 1 in the embodiment of the present invention may also include six, nine, and other numbers of diodes, which can be flexibly selected according to the forward conduction voltage drop V T of each diode and the high level of the positive voltage logic signal Vin.
In summary, the positive-to-negative-pressure logic circuit of the invention can convert an input positive-pressure logic signal into two negative-pressure logic signals with complementary outputs (one in-phase and one out-of-phase) through the structural design of the input level shift circuit unit, the buffer circuit unit, the in-phase logic output circuit unit and the anti-phase logic output circuit unit, and has simple conversion structure and high conversion efficiency; and each circuit unit is designed based on the GaAs HEMT technology, so that the positive-voltage-to-negative-voltage logic circuit can be integrated with a single-chip microwave integrated circuit direct unit chip such as a radio frequency switch, a numerical control attenuator, a numerical control phase shifter and the like, the simplification and miniaturization of the application of the single-chip microwave integrated circuit system are promoted, and the power consumption of the single-chip microwave integrated circuit system is reduced.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (5)
1. The positive-voltage-to-negative-voltage logic circuit based on the GaAs HEMT technology is characterized by comprising:
the input level shift circuit unit performs logic conversion on the input positive-voltage logic signal to obtain a first negative-voltage logic signal;
the buffer circuit unit is used for buffering and shaping the first negative pressure logic signal to obtain a second negative pressure logic signal;
the in-phase logic output circuit unit is used for carrying out phase adjustment on the second negative pressure logic signal to obtain a third negative pressure logic signal, wherein the third negative pressure logic signal is in phase with the positive pressure logic signal;
The inverting logic output circuit unit is used for carrying out phase adjustment on the second negative pressure logic signal to obtain a fourth negative pressure logic signal, and the fourth negative pressure logic signal is inverted with the positive pressure logic signal;
wherein the input level shift circuit unit includes:
The positive voltage logic signal is connected with the positive electrode of the first diode, the first diode and the rest diodes are sequentially connected in series in the same direction, and the negative electrode of the last diode is connected with the first node; one end of the first resistor is connected with the first node, the other end of the first resistor is connected with a negative power supply end, the negative power supply end provides a negative voltage level, and the absolute value of the negative voltage level is equal to the high level of the positive voltage logic signal; the first node is used as the output end of the input level shift circuit unit, and the signal at the first node is the first negative voltage logic signal;
The input level shift circuit unit, the buffer circuit unit, the in-phase logic output circuit unit and the anti-phase logic output circuit unit are all circuit units based on a GaAs HEMT process, and the plurality of diodes are all GaAs-based diodes;
The buffer circuit unit comprises a second resistor, a third resistor and a first HEMT transistor, wherein one end of the second resistor is connected with the first node, the other end of the second resistor is connected with the grid electrode of the first HEMT transistor, the source electrode of the first HEMT transistor is connected with the negative power supply end, the drain electrode of the first HEMT transistor is connected with the second node, one end of the third resistor is connected with the second node, the other end of the third resistor is grounded, the second node is used as the output end of the buffer circuit unit, and signals at the second node are the second negative pressure logic signals.
2. The positive-to-negative voltage logic circuit based on GaAs HEMT process of claim 1, wherein said in-phase logic output circuit unit includes a fourth resistor and a second HEMT transistor; the grid electrode of the second HEMT transistor is connected with the second node, the source electrode of the second HEMT transistor is connected with the negative power supply end, and the drain electrode of the second HEMT transistor is connected with the third node; one end of the fourth resistor is connected with the third node, and the other end of the fourth resistor is connected with the ground;
The third node is used as the output end of the in-phase logic output circuit unit, and the signal at the third node is the third negative-voltage logic signal.
3. The positive-to-negative voltage logic circuit based on GaAs HEMT process of claim 2, wherein the inverting logic output circuit unit includes a fifth resistor, a sixth resistor, a third HEMT transistor, and a fourth HEMT transistor; the grid electrode of the third HEMT transistor is connected with the second node, the source electrode of the third HEMT transistor is connected with the negative power supply end, and the drain electrode of the third HEMT transistor is connected with the fourth node; one end of the fifth resistor is connected with the fourth node, and the other end of the fifth resistor is connected with the ground; the grid electrode of the fourth HEMT transistor is connected with the fourth node, the source electrode of the fourth HEMT transistor is connected with the negative power supply end, and the drain electrode of the fourth HEMT transistor is connected with the fifth node; one end of the sixth resistor is connected with the fifth node, and the other end of the sixth resistor is connected with the ground;
The fifth node is used as the output end of the inverting logic output circuit unit, and the signal at the fifth node is the fourth negative voltage logic signal.
4. The positive-to-negative voltage logic circuit of claim 3, wherein the first, second, third, and fourth HEMT transistors are enhancement HEMT transistors.
5. The positive-to-negative voltage logic circuit based on GaAs HEMT process of claim 4, wherein the first, second, third, fourth, fifth and sixth resistors each have a resistance value equal to or greater than a first threshold.
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| CN111682866B (en) * | 2020-06-24 | 2024-02-09 | 天津中科海高微波技术有限公司 | GaAs switch driving circuit with adjustable output current |
| CN112865783A (en) * | 2021-01-24 | 2021-05-28 | 合肥芯谷微电子有限公司 | GaAs E/D technology low-power consumption inverter circuit |
| CN114567151B (en) * | 2022-02-25 | 2023-09-29 | 中国电子科技集团公司第二十九研究所 | GaAs process driving circuit improving method, circuit, switch and chip |
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