CN116248093A

CN116248093A - High-voltage level shift module and gate driving circuit

Info

Publication number: CN116248093A
Application number: CN202111494764.7A
Authority: CN
Inventors: 沈超; 陈冠峰; 陈继辉; 卜慧琴; 单志清
Original assignee: CRM ICBG Wuxi Co Ltd
Current assignee: CRM ICBG Wuxi Co Ltd
Priority date: 2021-12-08
Filing date: 2021-12-08
Publication date: 2023-06-09

Abstract

The invention relates to a high-voltage translation module, which comprises a junction field effect transistor, a third PNP tube, a fourth NPN tube, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a second PNP tube. The invention also relates to a grid driving circuit comprising the high-voltage level shifting module. The high-voltage level shift module and the corresponding gate driving circuit thereof fully utilize the characteristics and advantages of bipolarization preparation process devices, realize the high-voltage level shift function more succinctly in the function realization of the circuit, particularly in the structure realization of a high-voltage level shift part, and can realize the high-voltage level shift function without a complicated narrow pulse time sequence conversion process, and the number of devices required by the whole circuit is obviously reduced, so that the whole circuit has better reliability, shock resistance and interference resistance, and meanwhile, the bipolarization preparation process is adopted, the chip preparation cost of the circuit is lower, and the circuit has good market competitiveness and broad market prospect.

Description

High-voltage level shift module and gate driving circuit

Technical Field

The invention relates to the technical field of electronic circuits, in particular to the technical field of grid driving circuits in electric vehicle controllers and electric tools, and specifically relates to a high-voltage translation module and a corresponding grid driving circuit thereof.

Background

At present, a mainstream alternative scheme of a driving half-bridge power MOSFET or IGBT tube is represented by an IR2103 circuit of an international rectifying company (IR), a logic block diagram of the half-bridge driving IC prepared by a special high-voltage well technology based on CMOS is shown in figure 1, and the characteristic of the preparation of the special high-voltage well technology based on CMOS is that in order to realize the driving of a high-voltage side half-bridge, the core of the function realization is a high-voltage translation bit structure 102 in a dashed line frame in figure 1, the high-voltage withstand voltage is designed to bear high voltage to realize the conversion of high and low levels by two high-voltage MOS tubes, and the device characteristic of the high-voltage MOS determines the limitation of the sustainable power consumption born by the two high-voltage MOS tubes at the moment of high-voltage level conversion, so the function is realized by matching pulse generation 101, the high-voltage translation bit structure 102, pulse filtering 103 and an RS trigger filter shaping module 104.

The change time sequence of the overall function of the part is illustrated in the following fig. 2, wherein the change time sequence is specifically:

the first step, the input signal needs to be changed into a narrow pulse signal with short duration by pulse generation 101, and the duration of the narrow pulse is generally within hundreds of ns; secondly, the high-voltage translation structure 102 works, and the converted narrow pulse signals realize the change of the control signal level from VCC/COM to (VB-DeltaV)/VS by driving the on and off of the two high-voltage MOS transistors; third, the pulse filtering 103 converts the narrow pulse level signal between VB/(VB-DeltaV) to the narrow pulse level signal between VB/VS; fourth, the RS flip-flop filter shaping module 104 restores the input narrow pulse signal, and finally converts the input narrow pulse signal into a square wave signal with the same frequency as the input square wave signal, so as to drive the output stage driving tube to work, and finally drives the upper half-arm bridge power MOSFET or IGBT tube.

Due to the limitation requirement of the continuous power consumption of the high-voltage MOS transistor, the duration of the narrow pulse signal generated by conversion is short enough, and the duration of the short pulse is too short, so that the anti-interference characteristic of the circuit is poor when the circuit works. And because of the characteristics of the CMOS preparation process device, once the power consumption on the MOS tube bearing high voltage exceeds the limit, the device is easy to burn out instantly and the like.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide a high-voltage translation module with better overall reliability, shock resistance and anti-interference characteristics and a corresponding grid driving circuit thereof.

In order to achieve the above object, the high voltage translation module and the corresponding gate driving circuit thereof according to the present invention are as follows:

the high-voltage electric potential shift module is mainly characterized by comprising:

a junction field effect transistor, a third PNP tube, a fourth NPN tube, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor, wherein,

the first end of the second resistor is connected with the first end of the third resistor; the second end of the third resistor is connected with the emitter of the third PNP tube; the source electrode of the junction field effect tube is connected with the collector electrode of the fourth NPN tube; the emitter of the fourth NPN tube is connected with the first end of the fourth resistor; the second end of the fourth resistor is connected with the grid electrode of the junction field effect transistor; the collector of the third PNP tube is connected with the first end of the fifth resistor, and the second end of the fifth resistor is connected with the first end of the seventh resistor and the first end of the sixth resistor.

Preferably, the high voltage translation module further comprises a second PNP transistor, wherein,

the emitter of the second PNP tube is connected with the second end of the second resistor, the base of the second PNP tube is connected with the base of the third PNP tube, and the base and the collector of the second PNP tube are connected with the drain of the junction field effect tube.

The gate driving circuit comprising the high-voltage level shift module is mainly characterized by comprising:

the input logic control module is used for transmitting the input logic level signals to the logic processing module of the rear stage after logic processing;

and the interlocking logic and dead time generation module is connected with the input logic control module and is used for judging the consistency of the signal states of the logic signals processed by the input logic control module so as to prevent the power tube from being burnt out due to inaccurate input signal states.

Preferably, the gate driving circuit further comprises:

and the bias module is used for generating bias current required by the operation of each main module in the circuit.

Preferably, the gate driving circuit further comprises:

The VCC under-voltage protection module is connected with the interlocking logic and dead time generation module and is used for monitoring the power supply voltage VCC input by the circuit, and the VCC under-voltage protection module is also provided with a VCC under-voltage protection value;

when the VCC under-voltage protection value is lower than a circuit design threshold value, the VCC under-voltage protection module executes under-voltage protection function actions;

when the VCC under-voltage protection value is higher than the circuit design threshold value, the VCC under-voltage protection module executes the action of separating from the under-voltage protection function.

Preferably, the gate driving circuit further comprises:

the high-side output driving module is connected with the high-voltage translation module and is used for receiving the signals processed by the high-voltage translation module and realizing high-side high-current output driving of the grid driving circuit by amplifying the signal driving capability step by step; and

the low-side output driving module is connected with the interlocking logic and dead time generating module and is used for receiving the output signals processed by the interlocking logic and dead time generating module and realizing low-side high-current output driving of the grid driving circuit through step-by-step amplification of the signal driving capability.

Preferably, the input logic control module specifically includes:

the output end of the input schmitt trigger group is connected with the input end of the interlocking logic and dead time generation module and is used for carrying out logic control processing on a first input logic level signal HIN and a second input logic level signal L-I-N of the input end.

More preferably, the high-side output driving module is provided with a first high-side darlington driving structure and a second high-side darlington driving structure, wherein the first high-side darlington driving structure comprises a seventh NPN tube and an eighth NPN tube,

the collector of the seventh NPN tube is connected with the collector of the eighth NPN tube; the emitter of the seventh NPN tube is connected with the base electrode of the eighth NPN tube; the emitter of the eighth NPN tube is connected with the high-side output end of the high-side output driving module;

the second high-side Darlington driving structure comprises a fourth NPN tube and a fifth NPN tube,

the collector of the fourth NPN tube is connected with the base electrode of the seventh NPN tube; the emitter of the fourth NPN tube is connected with the base electrode of the fifth NPN tube; and the collector electrode of the fifth NPN tube is connected with the high-side output end of the high-side output driving module.

More preferably, the low-side output driving module is provided with a first low-side darlington driving structure and a second low-side darlington driving structure, wherein the first low-side darlington driving structure comprises a sixth NPN tube and a seventh NPN tube,

the collector of the sixth NPN tube is connected with the collector of the seventh NPN tube; the emitter of the sixth NPN tube is connected with the base electrode of the seventh NPN tube; the emitter of the seventh NPN tube is connected with the low-side output end of the low-side output driving module;

the second low-side darlington driving structure comprises a ninth NPN tube and a tenth NPN tube,

the collector electrode of the ninth NPN tube is connected with the base electrode of the sixth NPN tube; the base electrode of the ninth NPN transistor is connected with the first input logic level signal HIN or the second input logic level signal L-I-N; the emitter of the ninth NPN tube is connected with the base electrode of the tenth NPN tube; and the collector electrode of the tenth NPN tube is connected with the low-side output end of the low-side output driving module.

Preferably, the gate driving circuit further comprises a filtering module, wherein the filtering module is arranged between the output end of the high-voltage level shifting module and the input end of the high-side output driving module, and is used for reducing the instability of the voltage value of the circuit in the charging and discharging process so as to input stable voltage to the high-side output driving module for outputting high voltage level.

By adopting the high-voltage level shift module and the corresponding gate driving circuit thereof, the characteristics and advantages of bipolarization preparation process devices are fully utilized, the function realization of the circuit is more concise, particularly the structure realization of a high-voltage level shift part can realize the high-voltage level shift function without a complicated narrow pulse time sequence conversion process, the number of devices required by the whole circuit is obviously reduced, and the reliability, impact resistance and anti-interference characteristics of the whole circuit are better. Meanwhile, the bipolarr preparation technology is adopted, so that the chip preparation cost of the circuit is lower. Optionally, the integrated bootstrap diode can be further designed in the circuit, the design of the driving power supply can be greatly simplified by adopting the bootstrap suspension driving power supply structure, and the driving of the two power switch devices at the high side and the low side can be completed by only using one power supply voltage VCC, so that the selection range of the circuit in practical application is wider, the application periphery is simpler under the condition that an external bootstrap diode is not needed, the design area of a PCB (printed circuit board) can be further reduced, meanwhile, the preparation price of a bipolar process chip is relatively low, and the use cost can be effectively reduced. The method is more suitable for application scenes of electric vehicle controllers and related electric tools, and has good market competitiveness and broad market prospect.

Drawings

Fig. 1 is a logic block diagram of a half-bridge driver IC fabricated by a special high-voltage well process based on CMOS in the prior art.

Fig. 2 is a timing diagram of a variation in implementing a high-side half-bridge driving function in the prior art.

Fig. 3 is a schematic diagram of a gate driving circuit according to the present invention.

Fig. 4 is a schematic logic structure diagram of the high voltage translation module according to the present invention.

Fig. 5 is a schematic diagram of a logic structure of a high-side output driving module according to the present invention.

Fig. 6 is a schematic diagram of a logic structure of a low-side output driving module according to the present invention.

FIG. 7 is a schematic diagram of a logic structure of an embodiment of a bias module of the present invention.

Fig. 8 is a schematic logic structure diagram of a VCC under-voltage protection module according to an embodiment of the present invention.

Fig. 9 is a schematic diagram of a logic structure of an embodiment of the interlock logic & dead time generation module of the present invention.

Fig. 10 is an equivalent logic diagram of the interlock logic & dead time generation module according to the present invention involving the not gate INV.

Fig. 11a is a first schematic diagram of equivalent logic involving NOR gates NOR in the interlock logic & dead time generation module of the present invention.

Fig. 11b is a second schematic diagram of equivalent logic involving NOR gates NOR in the interlock logic & dead time generation module of the present invention.

Fig. 12 is a schematic logic structure diagram of another embodiment of the high voltage translation module of the present invention.

FIG. 13 is a schematic diagram of an exemplary application structure of the present invention.

Reference numerals

301. Bias module

302. Input logic control module

303 VCC under-voltage protection module

304. Interlock logic & dead time generation module

305. High-voltage translation module

306. High-side output driving module

307. Low-side output driving module

J0 Junction field effect transistor

Q402 second PNP tube

Q403 third PNP pipe

Q404 fourth NPN tube

R402 second resistor

R403 third resistor

R404 fourth resistor

R405 fifth resistor

R406 sixth resistor

R407 seventh resistor

Q1202 second NPN tube

Q1203 third PNP tube

R1202 second resistor

R1203 third resistor

R1204 fourth resistor

R1205 fifth resistor

R1206 sixth resistor

R1207 seventh resistor

Q701 first NPN tube

Q702 second PNP tube

Q703 third NPN tube

Q704 fourth PNP tube

R701 first resistor

R702 second resistor

R703 third resistor

D _z Voltage stabilizing diode

Q802 second PNP tube

Q803 third PNP tube

Q805 fifth PNP tube

Q806 sixth PNP tube

Q807 seventh NPN tube

Q808 eighth NPN tube

INV1 first inverting amplifier

INV2 second inverting amplifier

INV3 third inverting amplifier

INV4 fourth inverting amplifier

INV5 fifth inverting amplifier

NOR1 first logic NOR gate

NOR2 second logic NOR gate

Q501 first PNP tube

Q502 second PNP tube

Q503 third NPN tube

Q504 fourth NPN tube

Q505 fifth NPN tube

Q506 sixth NPN tube

Q507 seventh NPN tube

Q508 eighth NPN tube

R501 first resistor

R502 second resistor

R503 third resistor

Q601 first PNP pipe

Q602 second NPN tube

Q603 third NPN tube

Q604 fourth PNP tube

Q605 fifth PNP tube

Q606 sixth NPN tube

Q607 seventh NPN tube

Q608 eighth NPN tube

Q609 ninth NPN tube

Q610 tenth NPN tube

R601 first resistor

R602 second resistor

HIN first input logic level signal

A second input logic level signal

Detailed Description

In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.

Before describing in detail embodiments that are in accordance with the present invention, it should be observed that relational terms, such as first and second, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Referring to fig. 4, the high voltage translation module includes:

junction field effect transistor J0, third PNP transistor Q403, fourth NPN transistor Q404, second resistor R402, third resistor R403, fourth resistor R404, fifth resistor R405, sixth resistor R406, and seventh resistor R407, wherein,

the first end of the second resistor R402 is connected with the first end of the third resistor R403; the second end of the third resistor R403 is connected with the emitter of the third PNP tube Q403; the source electrode of the junction field effect tube J0 is connected with the collector electrode of the fourth NPN tube Q404; the emitter of the fourth NPN tube Q404 is connected with the first end of the fourth resistor R404; the second end of the fourth resistor R404 is connected with the grid electrode of the junction field effect transistor J0; the collector of the third PNP transistor Q403 is connected to the first end of the fifth resistor R405, and the second end of the fifth resistor R405 is connected to the first end of the seventh resistor R407 and the first end of the sixth resistor R406.

Referring to fig. 12, as a preferred embodiment of the present invention, a second PNP transistor Q402 is further included, wherein,

The emitter of the second PNP transistor Q402 is connected to the second end of the second resistor R402, the base of the second PNP transistor Q402 is connected to the base of the third PNP transistor Q403, and the base and collector of the second PNP transistor Q402 are connected to the drain of the junction field effect transistor J0.

In practical applications, the high voltage level shift module 305 is a core implementation module of the present invention, and the structure fully utilizes the characteristics and advantages of the bipolartechnology platform device, and implements the prior art through a simpler and reliable logic structure, that is, the above-mentioned fig. 1 needs four modules of pulse generation 101, high voltage level shift structure 102, pulse filtering 103 and RS trigger filtering shaping 104 to cooperate to implement the high voltage level shift function.

Referring to fig. 3, the gate driving circuit including the high voltage level shift module described above includes:

the input logic control module 302 is configured to logically process an input logic level signal and then transmit the processed signal to a logic processing module at a later stage;

the interlock logic & dead time generation module 304 is connected to the input logic control module 302, and is configured to perform signal state consistency judgment processing on the logic signal processed by the input logic control module 302, so as to prevent the power tube from being burned due to inaccurate input signal state.

As a preferred embodiment of the present invention, the input logic control module 302 specifically includes:

the output end of the input schmitt trigger group is connected with the input end of the interlocking logic and dead time generation module 304 and is used for carrying out logic control processing on a first input logic level signal HIN and a second input logic level signal L-I-N of the input end.

Referring to fig. 9, in an embodiment of the present invention, the interlock logic & dead time generation module 304 specifically includes:

a first capacitor C1, a first inverse amplifier INV1, a second inverse amplifier INV2, a third inverse amplifier INV3, a fourth inverse amplifier INV4, a fifth inverse amplifier INV5, a first NOR gate NOR1, and a second NOR gate NOR2, wherein,

the output end of the first reverse amplifier INV1 is connected with the input end of the second reverse amplifier INV 2; the output end of the second inverting amplifier INV2 is connected with the first end of the first capacitor C1 and the input end of the fourth inverting amplifier INV4, and the output end of the fourth inverting amplifier INV4 is connected with the second input end of the second logic NOR gate NOR 2; the first input end of the second logical NOR gate NOR2 is connected with the input end of the third inverting amplifier INV 3; the output end of the third inverting amplifier INV3 is connected with the first input end of the first logic NOR gate NOR 1; the second input end of the first logical NOR gate NOR1 is connected with the input end of the first inverting amplifier INV 1; the output end of the second logical NOR gate NOR2 is connected with the input end of the fifth inverting amplifier INV 5; the fifth inverting amplifier INV5 and the output end of the first NOR gate NOR1 both output signals.

In practical application, the interlock logic & dead time generation module 304 further processes the logic signal processed by the input logic control module 302, so as to prevent the situation that the high side output HO/LO is high at the same time when the input signal state is inaccurate, so that the power MOSFET or IGBT tube driven by the output has abnormal situation that the upper arm bridge and the lower arm bridge pass through, and the abnormal situation easily has short circuit and large current, so that the power tube is burnt.

As a preferred embodiment of the present invention, the gate driving circuit further includes:

the bias module 301 is used for generating bias current required by each main module in the circuit to work.

Referring to fig. 7, in an embodiment of the present invention, the bias module 301 specifically includes:

a first NPN tube Q701, a second PNP tube Q702, a third NPN tube Q703, a fourth PNP tube Q704, a first resistor R701, a second resistor R702 and a third resistor R703, wherein,

the collector of the first NPN tube Q701 is connected to the second end of the first resistor R701 and the base of the third NPN tube Q703, the emitter of the first NPN tube Q701 is connected to the second end of the second resistor R702, the first end of the first resistor R701 is connected to the emitter of the second PNP tube Q702 and the first end of the third resistor R703, the second PNP tube Q702 is connected to the third NPN tube Q703, the emitter of the third NPN tube Q703 is connected to the first end of the second resistor R702 and the base of the first NPN tube Q701, the base of the fourth PNP tube Q704 is connected to the second PNP tube Q702 and the second end of the third resistor R703, and the collector of the fourth PNP tube Q704 is connected to the second end of the third resistor R703.

the VCC under-voltage protection module 303 is connected with the interlocking logic & dead time generation module 304, and is configured to monitor the power supply voltage VCC input by the circuit, and the VCC under-voltage protection module 303 is further provided with a VCC under-voltage protection value;

when the VCC under-voltage protection value is lower than the circuit design threshold, the VCC under-voltage protection module 303 performs an under-voltage protection function;

when the VCC under-voltage protection value is higher than the circuit design threshold, the VCC under-voltage protection module 303 performs the action of disengaging from the under-voltage protection function.

Referring to fig. 8, in an embodiment of the present invention, the VCC under-voltage protection module 303 specifically includes:

voltage stabilizing diode D _z A first NPN tube Q801, a second PNP tube Q802, a third PNP tube Q803, a fourth PNP tube Q804, a fifth PNP tube Q805, a sixth PNP tube Q806, a seventh NPN tube Q807, an eighth NPN tube Q808 and a ninth NPN tube Q809, wherein a first resistor R801, a second resistor R802, a third resistor R803, a fourth resistor R804, a fifth resistor R805, a sixth resistor R806, a seventh resistor R807, an eighth resistor R808 and a ninth resistor R809,

The collector of the first NPN tube Q801 is connected with the first end of the third resistor R803 and the second end of the second resistor R802, and the base of the first NPN tube Q801 is connected with the first end of the fourth resistor R804; the second PNP transistor Q802, the third PNP transistor Q803 and the fourth PNP transistor Q804 all share a base, and the emitters of the second PNP transistor Q802, the third PNP transistor Q803 and the fourth PNP transistor Q804 are connected and then all connected to the first end of the first resistor R801; the collector of the fourth PNP transistor Q804 is connected to the first end of the seventh resistor R807 and the first end of the eighth resistor R808; the base electrode of the fifth PNP tube Q805 is connected with the second end of the first resistor R801 and the first end of the second resistor R802, the fifth PNP tube Q805 and the sixth PNP tube Q806 share an emitter electrode, and the emitters of the fifth PNP tube Q805 and the sixth PNP tube Q806 are connected with the collector electrode of the second PNP tube Q802; the fifth PNP transistor Q805 is commonly connected to the seventh PNP transistor Q807, the collector of the fifth PNP transistor Q805 is connected to the base of the seventh NPN transistor Q807, the sixth PNP transistor Q806 is commonly connected to the eighth NPN transistor Q808, the base of the ninth NPN transistor Q809 is connected to the sixth PNP transistor Q806 and the collector of the eighth NPN transistor Q808, and the seventh NPN transistor Q807 is commonly connected to the base of the eighth NPN transistor Q808; the emitter of the seventh NPN tube Q807 and the eighth NPN tube The emitter of Q808 is connected; the voltage stabilizing diode D _z The negative pole of the third PNP transistor Q803 is connected with the base electrode of the sixth PNP transistor Q806 and the collector electrode of the third PNP transistor Q803, the zener diode D _z Is connected to the first end of the sixth resistor R806; the collector of the ninth NPN transistor Q809 is connected to the second terminal of the fourth resistor R804, the second terminal of the seventh resistor R807, and the first terminal of the ninth resistor R807.

In practical applications, the VCC under-voltage protection module 303 monitors the power supply voltage VCC, and when detecting that the VCC voltage is lower than the design threshold, the under-voltage protection function acts to output control signals to control and turn off the outputs of the high and low sides HO and LO, so as to protect the power MOSFET or the IGBT power tube driven by the output. The VCC under-voltage protection point is generally designed with hysteresis voltage, when the VCC voltage is detected to be lower than the design threshold V _CCUVD When the VCC voltage is detected to be higher than the design threshold V _CCUVR When the voltage is out of the under-voltage protection state, the hysteresis voltage V _CCUVH ＝V _CCUVR －V _CCUVD 。

the high-side output driving module 306 is connected with the high-voltage translation module 305 and is used for receiving the signals processed by the high-voltage translation module 305, and the high-side high-current output driving of the gate driving circuit is realized by amplifying the signal driving capability step by step; and

The low-side output driving module 307 is connected to the interlock logic & dead time generating module 304, and is configured to receive the output signal processed by the interlock logic & dead time generating module 304, and amplify the signal driving capability step by step, so as to implement low-side high-current output driving of the gate driving circuit.

As a preferred embodiment of the present invention, the high-side output driving module 306 is provided with a first high-side darlington driving structure and a second high-side darlington driving structure, where the first high-side darlington driving structure includes a seventh NPN transistor Q507 and an eighth NPN transistor Q508,

the collector of the seventh NPN tube Q507 is connected with the collector of the eighth NPN tube Q508; the emitter of the seventh NPN tube Q507 is connected with the base of the eighth NPN tube Q508; the emitter of the eighth NPN transistor Q508 is connected to the high-side output terminal HO of the high-side output driving module 306;

the second high-side darlington driving structure includes a fourth NPN tube Q504 and a fifth NPN tube Q505,

the collector of the fourth NPN tube Q504 is connected with the base of the seventh NPN tube Q507; the emitter of the fourth NPN tube Q504 is connected with the base of the fifth NPN tube Q505; the collector of the fifth NPN transistor Q505 is connected to the high-side output terminal HO of the high-side output driving module 306.

Referring to fig. 5, in an embodiment of the present invention, the high-side output driving module 306 specifically includes:

a first PNP pipe Q501, a second PNP pipe Q502, a third NPN pipe Q503, a fourth NPN pipe Q504, a fifth NPN pipe Q505, a sixth NPN pipe Q506, a seventh NPN pipe Q507, an eighth NPN pipe Q508, a first resistor R501, a second resistor R502 and a third resistor R503, wherein,

the first PNP pipe Q501 and the second PNP pipe Q502 share an emitter; the first PNP tube Q501 and the second PNP tube Q502 share a base electrode; the collector of the first PNP tube Q501 is connected with the base thereof and the first end of the first resistor R501; the second end of the first resistor R501 is connected with the collector of the third NPN tube Q503; the base electrode of the third NPN tube Q503 is connected to the output logic level signal processed by the high voltage level shift module 305; the second PNP tube Q502 and the fourth NPN tube Q504 share a collector; the base electrode of the fourth NPN tube Q504 is connected with the second end of the first resistor R501 and the collector electrode of the third NPN tube Q503; the emitter of the fourth NPN tube Q504 is connected with the first end of the second resistor R502; the second end of the second resistor R502 is connected with the emitter of the third NPN tube Q503; the base electrode of the seventh NPN tube Q507 is connected with the collector electrode of the second PNP tube Q502; the emitter of the seventh NPN tube Q507 is connected with the first end of the third resistor R503; the second end of the third resistor R503 is connected with the collector of the sixth NPN tube Q506; the emitter of the sixth NPN tube Q506 is connected with the collector of the fourth NPN tube Q504; the base electrode of the sixth NPN tube Q506 is connected with the emitter electrode of the eighth NPN tube Q508 and the collector electrode of the fifth NPN tube Q505; the eighth NPN tube Q508 and the seventh NPN tube Q507 share a collector; the base electrode of the eighth NPN transistor Q508 is connected between the emitter electrode of the seventh NPN transistor Q507 and the first end of the third resistor R503; the base electrode of the fifth NPN tube Q505 is connected between the emitter electrode of the fourth NPN tube Q504 and the first end of the second resistor R502; an emitter of the fifth NPN tube Q505 is connected to the second end of the second resistor R502.

In practical applications, the high-side output driving module 306 receives the signal processed by the high-voltage level shifting module 305, and obtains a large current driving capability to drive the power MOSFET or the IGBT power tube through step-by-step amplification of the signal driving capability.

As a preferred embodiment of the present invention, the low-side output driving module 307 is provided with a first low-side darlington driving structure and a second low-side darlington driving structure, where the first low-side darlington driving structure includes a sixth NPN tube Q606 and a seventh NPN tube Q607,

the collector of the sixth NPN tube Q606 is connected with the collector of the seventh NPN tube Q607; the emitter of the sixth NPN tube Q606 is connected with the base of the seventh NPN tube Q607; the emitter of the seventh NPN transistor Q607 is connected to the low-side output terminal LO of the low-side output driving module 307;

the second low-side darlington driving structure includes a ninth NPN tube Q609 and a tenth NPN tube Q610,

the collector of the ninth NPN tube Q609 is connected with the base of the sixth NPN tube Q606; the base of the ninth NPN transistor Q609 is connected with the first input logic level signal HIN or the second input logic level signal L-I-N; an emitter of the ninth NPN tube Q609 is connected with a base of the tenth NPN tube Q610; the collector of the tenth NPN transistor Q610 is connected to the low side output terminal LO of the low side output driving module 307.

Referring to fig. 6, in an embodiment of the present invention, the low-side output driving module 307 specifically includes:

a first PNP pipe Q601, a second NPN pipe Q602, a third NPN pipe Q603, a fourth PNP pipe Q604, a fifth PNP pipe Q605, a sixth NPN pipe Q606, a seventh NPN pipe Q607, an eighth NPN pipe Q608, a ninth NPN pipe Q609, a tenth NPN pipe Q610, a first resistor R601 and a second resistor R602, wherein,

the first PNP pipe Q601 and the fourth PNP pipe Q604 share an emitter; the first PNP pipe Q601 and the second NPN pipe Q602 share a collector, and the collector of the second NPN pipe Q602 is connected with a base electrode thereof; the second NPN tube Q602 and the third NPN tube Q603 share a base electrode; the third NPN tube Q603 is connected with the common collector of the fourth PNP tube Q604, and the collector of the fourth PNP tube Q604 is connected with the base thereof; the fourth PNP transistor Q604 and the fifth PNP transistor Q605 share a base, and the fourth PNP transistor Q604 and the fifth PNP transistor Q605 share an emitter; the fifth PNP tube Q605 and the ninth NPN tube Q609 share a collector; the base electrode of the ninth NPN transistor Q609 is connected to the output logic level signal processed by the interlock logic & dead time generating module 304; an emitter of the ninth NPN tube Q609 is connected with a first end of the first resistor R601; the second end of the first resistor R601 is connected with the emitter of the tenth NPN tube Q610; the base electrode of the tenth NPN tube Q610 is connected between the emitter electrode of the ninth NPN tube Q609 and the first end of the first resistor R601; the collector of the tenth NPN tube Q610 is connected with the base of the eighth NPN tube Q608; the emitter of the eighth NPN tube Q608 is connected between the collector of the fifth PNP tube Q605 and the collector of the ninth NPN tube Q609; the collector of the eighth NPN tube Q608 is connected to the emitter of the sixth NPN tube Q606 through the second resistor R602; the base of the sixth NPN tube Q606 is connected between the collector of the fifth PNP tube Q605 and the collector of the ninth NPN tube Q609; the base electrode of the seventh NPN tube Q607 is connected between the emitter electrode of the sixth NPN tube Q606 and the first end of the second resistor R602; the emitter of the seventh NPN tube Q607 is connected with the collector of the tenth NPN tube Q610; the collector of the seventh PNP transistor Q607 is connected to the emitter of the first PNP transistor Q601, the emitter of the fourth PNP transistor Q604, the emitter of the fifth PNP transistor Q605, and the collector of the sixth NPN transistor Q606.

In practical applications, the low-side output driving module 307 receives the output signal processed by the interlock logic & dead time generating module, and obtains a large current driving capability to drive the power MOSFET or the IGBT power tube through step-by-step amplification of the signal driving capability.

As a preferred embodiment of the present invention, the gate driving circuit further includes a filtering module, which is disposed between the output end of the high-voltage level shifting module 305 and the input end of the high-side output driving module 306, and is configured to reduce the instability of the voltage value of the circuit during the charging and discharging process, so as to input a stable voltage to the high-side output driving module 306 for outputting the high voltage level.

In a specific embodiment of the present invention, fig. 4 is a specific logic structure of an exemplary embodiment of the high voltage level shift module.

When the Y1 output state is low, the Q404 tube is in the off state:

at this time, the J0 tube (i.e. the njfet tube) is designed to bear most of the high voltage between VB and COM. In the process of gradually raising the voltage between VB and COM, when the voltage between VB and COM is relatively low (less than ten or more V), the J0 tube is not in a complete pinch-off state, and the equivalent resistance of the J0 tube is relatively small, and then the voltage between VB and COM is mainly formed by the Q404 tube BVcbo. When the voltage between VB and COM is further increased to more than ten or more V, the voltage is V of J0 tube (njfet tube) _GS To some extent the voltage is negative and the J0 tube will enter a fully pinched off state. Then the high voltage between VB and COM will be mostly taken up by the J0 tube and Q404 will only take up a small part of the high voltage. At this time, the withstand voltage of the J0 tube can be made high in the withstand voltage process, and the withstand voltage of the Q404 tube can be made at least 100V or more.

When the Y1 output state goes high, the drive Q404 tube is in an on state:

in this state, V of J0 tube (njfet tube) _GS The voltage is about a negative Q404 conduction voltage drop. At this time, the current flowing through the paths Q402 to Q404 is limited under high voltage by using the resistance characteristics of the J0 tube (njfet tube) (the higher the voltage received between the source and drain, the larger the equivalent resistance value thereof), thereby achieving the purpose of limiting the power of the whole module during operation. The high voltage between VB and COM will now be essentially borne by the J0 tube.

In the realization of the integral high-voltage level shifting function of the structure, when the output state of Y1 is low, the Q404 pipe is in a cut-off state, the Q402 pipe and the Q403 pipe are also in cut-off states, at the moment, the output of Y3 is low under the pull-down action of the R406 resistor, and the Q405 pipe is cut-off; when the output state of Y1 becomes high, the Q404 pipe is driven to be in an on state, at this moment, the current flowing through the Q402 pipe is mainly determined by the equivalent resistance of the J0 pipe (njfet pipe), and by reasonably designing the working current and selecting proper resistance values of R402 and R403 resistors and the proportional relation of the Q402 and Q403 pipes, the bias current on the path of the Q402 pipe is mirrored to the path of the Q403 pipe, so that the current has proper driving capability after flowing through the resistors R405, R406 and R407 and then reaching the output of Y3, and the Q405 pipe is driven to be conducted.

Through the description of the change of the working state of the whole module, the conversion from the signals from VCC to COM to the signals from VB to VS is realized, namely the high voltage level shifting function from VCC low voltage to VB high voltage is realized.

In a specific embodiment of the present invention, fig. 5 and 6 show schematic diagrams of specific logic structures of an embodiment of the high-low side HO and LO output stages of the present invention.

The functions of fig. 5 and 6 are basically consistent, and only slightly different in bias current supply, namely, output driving stage structures of a high side HO and a low side LO are respectively adopted, and a typical darlington driving structure is adopted.

In a specific embodiment of the present invention, fig. 7 shows a schematic diagram of a specific logic structure of an embodiment of the bias module of the present invention.

Fig. 7 shows a typical bias structure, through which appropriate bias currents are generated in Q701, R702, and Q703, and Q702, R703, Q704, and a post-stage LPNP tube form a current mirror structure, so as to provide stable bias currents for the post-stage modules of the circuit.

In a specific embodiment of the present invention, fig. 8 shows a schematic diagram of a specific logic structure of an embodiment of the VCC under-voltage protection structure of the present invention.

Fig. 8 shows an undervoltage protection function implementation module, in the above logic structure, the positive input of the comparator structure is connected to a reference voltage generated by the zener diode, and the negative input is connected to a voltage dividing proportional resistor between VCC and COM to sample to obtain a voltage variation value of VCC. Normally, the voltage detected by the negative end input of the comparator is higher than the reference voltage generated by the voltage stabilizing diode, and the UVLO-EN output is low; when VCC under-voltage is detected, the detected voltage input by the negative end of the comparator is lower than the reference voltage generated by the voltage stabilizing diode, and at the moment, the output of UVLO-EN is high, and the high-low side transmission channel of the turn-off circuit is controlled, so that the under-voltage protection function for the power supply VCC is realized. And the hysteresis voltage value of the undervoltage protection function is realized through the resistor resistance value of R803 connected in series or in short circuit.

In a specific embodiment of the present invention, fig. 9 shows a schematic diagram of a specific logic structure of an embodiment of the interlock logic & dead time generation module of the present invention.

Fig. 9 is an interlock logic & dead time generation module, the implementation of which can be described as follows.

The input and output signal logic truth tables are as follows:

as can be seen from the truth table, under the condition that the input logic signals HIN and L-I-N are not simultaneously '0' and are not simultaneously '1', the circuit controls the outputs HO and LO to be simultaneously '0', and the upper power tube and the lower power tube are in a state of being simultaneously turned off; when inputting logic signal HIN,

Meanwhile, when the power tube is 0, an upper tube power tube with the circuit control output HO of 0 is turned off, and a lower tube power tube with the LO of 1 is turned on; when the logic signal HIN is inputted>

And when the power supply is at 1, the upper tube power tube with the circuit control output HO of 1 is turned on, and the lower tube power tube with the LO of 0 is turned off.

The circuit eliminates the condition that the upper power tube and the lower power tube are simultaneously conducted when the output of the control circuit is through the internal interlocking logic design and the dead time increasing design.

In a specific embodiment of the present invention, fig. 10, 11a and 11b show an equivalent logic schematic diagram of the present invention involving the not gate INV and the NOR gate NOR. The logic gate circuit in the general bipolar process is realized through the structure, the upper tube LPNP tube passes through the bias current of the mirror image bias part, and when the lower tube NPN tube is cut off, the high-level driving output is realized; and when the lower NPN tube is conducted, low-level driving output is realized.

In a specific embodiment of the present invention, fig. 12 shows a schematic diagram of a specific logic structure of the high voltage level shift module 305 according to the present invention, which is different from the specific logic structure of the other embodiment of fig. 4. The basic implementation principle is basically consistent with that of the figure 4, and the driving of the Q1203 tube path is different by utilizing Q1202 paths of bias current, so that the structure of the figure 12 is simpler.

In the practical application process, referring to fig. 13, in a typical working state of the circuit, the voltage between the circuit high-voltage sides VB and VS is bootstrapped by a "bootstrapped floating driving power supply structure", that is, the voltage between the circuits VB and VS is bootstrapped mainly by the aid of D1 (bootstrap diode) and C1 (bootstrap capacitor) in the following diagram. The capacitance of the mu F level is generally provided, the voltage stabilizing effect on the voltage between the power supply VB and the voltage supply VS after bootstrapping is mainly achieved, the capacitance of the mu F level cannot be inherited in the chip, but the opposite D1 (bootstrap diode) can be conveniently integrated in the chip through a process scheme, so that the bootstrap diode design can be further integrated in an optional circuit, and D1 tubes in typical peripheral application can be reduced after the integration in the chip, and the peripheral application cost is reduced.

Meanwhile, voltage between VB and VS is realized by bootstrap depending on D1 (bootstrap diode) and C1 (bootstrap capacitor), the voltage between VB and VS is different from direct power supply through an external power supply, and the voltage is relatively unstable in the process of bootstrap when the voltage is charged and discharged, so that the high-voltage level shift module can be optionally connected with a filtering module at the later stage, and the anti-interference characteristic of the work of the module is further improved.

It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A high voltage translation module, comprising:

a junction field effect transistor (J0), a third PNP tube (Q403), a fourth NPN tube (Q404), a second resistor (R402), a third resistor (R403), a fourth resistor (R404), a fifth resistor (R405), a sixth resistor (R406) and a seventh resistor (R407), wherein,

the first end of the second resistor (R402) is connected with the first end of the third resistor (R403); the second end of the third resistor (R403) is connected with the emitter of the third PNP tube (Q403); the source electrode of the junction field effect tube (J0) is connected with the collector electrode of the fourth NPN tube (Q404); the emitter of the fourth NPN tube (Q404) is connected with the first end of the fourth resistor (R404); the second end of the fourth resistor (R404) is connected with the grid electrode of the junction field effect transistor (J0); the collector of the third PNP tube (Q403) is connected with the first end of the fifth resistor (R405), and the second end of the fifth resistor (R405) is connected with the first end of the seventh resistor (R407) and the first end of the sixth resistor (R406).

2. The high voltage translation module according to claim 1, further comprising a second PNP transistor (Q402), wherein,

the emitter of the second PNP tube (Q402) is connected with the second end of the second resistor (R402), the base of the second PNP tube (Q402) is connected with the base of the third PNP tube (Q403), and the base and collector of the second PNP tube (Q402) are connected with the drain of the junction field effect tube (J0).

3. A gate drive circuit comprising the high voltage translation module of any one of claims 1 to 2, the gate drive circuit comprising:

an input logic control module (302) for logically processing the input logic level signal and transmitting the processed signal to a logic processing module at a later stage;

and the interlocking logic and dead time generation module (304) is connected with the input logic control module (302) and is used for judging the consistency of the signal states of the logic signals processed by the input logic control module (302) so as to prevent the power tube from being burnt due to inaccurate input signal states.

4. A gate drive circuit according to claim 3, wherein said gate drive circuit further comprises:

A bias module (301) for generating bias currents required for operation of the respective main modules within the circuit.

5. A gate drive circuit according to claim 3, wherein said gate drive circuit further comprises:

the VCC under-voltage protection module (303) is connected with the interlocking logic and dead time generation module (304) and is used for monitoring the power supply voltage VCC input by the circuit, and the VCC under-voltage protection module (303) is also provided with a VCC under-voltage protection value;

when the VCC under-voltage protection value is lower than a circuit design threshold value, the VCC under-voltage protection module (303) executes under-voltage protection function action;

when the VCC under-voltage protection value is higher than the circuit design threshold value, the VCC under-voltage protection module (303) executes the action of separating from the under-voltage protection function.

6. A gate driving circuit according to claim 3, wherein said input logic control module (302) comprises:

an input schmitt trigger group, a port pull-down resistor, a port pull-up resistor or a pull-up current source, wherein the output end of the input schmitt trigger group is connected with the interlocking logic&The dead time generation module (304) has an input terminal connected to the first input logic level signal HIN and the second input logic level signal of the input terminal

Logic control processing is performed.

7. A gate drive circuit according to claim 3, wherein said gate drive circuit further comprises:

the high-side output driving module (306) is connected with the high-voltage translation module (305) and is used for receiving the signals processed by the high-voltage translation module (305) and realizing high-side high-current output driving of the grid driving circuit through step-by-step amplification of the signal driving capability; and

the low-side output driving module (307) is connected with the interlocking logic and dead time generating module (304) and is used for receiving the output signals processed by the interlocking logic and dead time generating module (304) and realizing low-side high-current output driving of the grid driving circuit through step-by-step amplification of the signal driving capability.

8. The gate driving circuit according to claim 7, wherein a first high-side darlington driving structure and a second high-side darlington driving structure are disposed in the high-side output driving module (306), and wherein the first high-side darlington driving structure includes a seventh NPN transistor (Q507) and an eighth NPN transistor (Q508),

the collector of the seventh NPN tube (Q507) is connected with the collector of the eighth NPN tube (Q508); the emitter of the seventh NPN tube (Q507) is connected with the base electrode of the eighth NPN tube (Q508); the emitter of the eighth NPN tube (Q508) is connected with a high-side output end (HO) of the high-side output driving module (306);

The second high-side Darlington driving structure comprises a fourth NPN tube (Q504) and a fifth NPN tube (Q505),

the collector of the fourth NPN tube (Q504) is connected with the base of the seventh NPN tube (Q507); the emitter of the fourth NPN tube (Q504) is connected with the base electrode of the fifth NPN tube (Q505); the collector of the fifth NPN tube (Q505) is connected with the high-side output end (HO) of the high-side output driving module (306).

9. The gate drive circuit of claim 7, wherein a first low-side darlington driving structure and a second low-side darlington driving structure are disposed in the low-side output driving module (307), and wherein the first low-side darlington driving structure includes a sixth NPN transistor (Q606) and a seventh NPN transistor (Q607),

the collector of the sixth NPN tube (Q606) is connected with the collector of the seventh NPN tube (Q607); the emitter of the sixth NPN tube (Q606) is connected with the base electrode of the seventh NPN tube (Q607); the emitter of the seventh NPN tube (Q607) is connected with the low-side output end (LO) of the low-side output driving module (307);

the second low-side darlington driving structure includes a ninth NPN tube (Q609) and a tenth NPN tube (Q610),

The collector of the ninth NPN tube (Q609) is connected with the base of the sixth NPN tube (Q606); the base of the ninth NPN transistor (Q609) is connected with the first input logic level signal HIN or the second input logic level signal

The emitter of the ninth NPN tube (Q609) is connected with the base electrode of the tenth NPN tube (Q610); the collector of the tenth NPN tube (Q610) is connected with the low-side output end (LO) of the low-side output driving module (307).

10. The gate driving circuit according to claim 7, further comprising a filtering module, wherein the filtering module is disposed between the output terminal of the high-voltage level shifting module (305) and the input terminal of the high-side output driving module (306), and is configured to reduce the instability of the voltage value of the circuit during the charging and discharging process, so as to input a stable voltage to the high-side output driving module (306) for outputting the high voltage level.