CN103117739A - GaN-based enhancement-depletion type level switch circuit - Google Patents
GaN-based enhancement-depletion type level switch circuit Download PDFInfo
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- CN103117739A CN103117739A CN2013100552619A CN201310055261A CN103117739A CN 103117739 A CN103117739 A CN 103117739A CN 2013100552619 A CN2013100552619 A CN 2013100552619A CN 201310055261 A CN201310055261 A CN 201310055261A CN 103117739 A CN103117739 A CN 103117739A
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Abstract
The invention discloses a GaN-based enhancement-depletion type level switch circuit and mainly overcomes the shortcoming that the prior art cannot integrate a level switch circuit and a GaN-based circuit on one substrate. The switch circuit comprises a first inverter circuit, a first output circuit, a second inverter circuit and a second inverter circuit, wherein the first inverter circuit inverts an input level, the first output circuit pulls down the level inverted by the first inverter circuit, the second inverter circuit inverts an output level, and the second output circuit pulls down the level inverted by the second inverter circuit. The GaN-based enhancement-depletion type level switch circuit is simple in process realization, and can integrate the level switch circuit and the GaN-based circuit on one substrate, thereby increasing the reliability and reducing the crosstalk.
Description
Technical field
The present invention relates to electronic technology field, further relate to the gallium nitrate based enhancing depletion type level shifting circuit in the semiconductor integrated circuit technical field.The present invention can be used for controlling the switch in gallium nitrate based microwave radio field, makes by the radiofrequency signal of switch to turn-off and conducting.
Background technology
At present, along with the maturation of semiconductor technology, the microwave radio monolithic system is more and more ripe, generally by digital logic unit and microwave radio the electric circuit constitute.Gallium nitrate based microwave radio circuit adopts comparatively ripe depletion device, and depletion device is due to the raceway groove that exhausts of the natural formation of aluminum-gallium-nitrogen/gallium nitride heterojunction, and causing its cut-in voltage is negative value, and general many at-2V--2.5V.And gallium nitrate based radio circuit coordinates with the rear end silicon-based electronic circuits to be absolutely necessary as system front end.But most of si-substrate integrated circuit interface is standard TTL output, its high-low level is respectively＞2.4V and＜0.4V, therefore need a special interface-level shifting circuit, realize the conversion of level, be connected gallium nitrate based front end and silica-based rear end, and then guarantee the normal operation of the switch that in gallium nitrate based circuit, depletion device consists of.Generally, can think if after changing voltage less than or equal to-3.5V switch turn-off, more than or equal to-1V switch open.In order to address the above problem, there have been a lot of silicon-based electronic circuits to realize the conversion of level at present.
The patented technology that Chengdu Hi-tech Zone Nima Electronic Product Design Studio has " level shifting circuit of dual control model processed " (application number 201120421799.3, Granted publication CN 202334487 U) discloses a kind of level shifting circuit that is applicable to control switch.This circuit comprises binary channels NPN transistor and the output signal circuit and the control signal input circuit that are connected with binary channels NPN transistor T2 simultaneously.This circuit has minimum cost.But, the deficiency that this patented technology still exists is: due to gallium nitride material p-type doping difficulty, so NPN transistor used in this circuit structure still can not realize on gallium nitride, therefore still can not be gallium nitrate based circuit and level shifting circuit with the substrate single-chip integrated.
The patented technology that Chinese Academy of Sciences Microelectronics Institute has " digital-to-analogue hybrid multi-path independent control switch circuit " (application number 200810238937.7, application publication number CN 101753121A) discloses a kind of level shifting circuit that is applicable to control switch.This circuit comprises that PWM controller, enter drive, level shifting circuit, current mode switch circuit and output volt are at circuit etc.This circuit can significantly improve the switching speed of field effect transistor.But, the deficiency that this patented technology still exists is: although now technical can this patented technology be connected circuit and first connect by gold thread and then be encapsulated in a housing, but gold thread can bring signal cross-talk, may affect the normal realization of circuit function.
Summary of the invention
The object of the invention is to overcome the deficiency that above-mentioned prior art exists, propose a kind of gallium nitrate based enhancing depletion type level shifting circuit.The present invention has designed a kind of attainable gallium nitrate based enhancing depletion type level shifting circuit in order to improve the performance of gallium nitrate based circuit, has realized the integrated of SOC (system on a chip), has reduced between line and has crosstalked, and can be connected with the TTL circuit use.
For achieving the above object, the present invention includes the first negative circuit, the first output circuit, the second negative circuit, the second output circuit.The input of the output of the first negative circuit and the first output circuit joins, and the input of the output of the first output circuit and the second negative circuit joins, and the input of the output of the second negative circuit and the second output circuit joins.
The drain electrode of depletion high electron mobility transistors T1 in the first negative circuit unit connects the positive bias line, after the source electrode of T1 and its grid short circuit, join with the drain electrode of enhancement type high electron mobility transistor T2 and the grid of the enhancement type high electron mobility transistor T3 in the first output circuit unit respectively; The grid of T2 connects input VIN, the source ground line of T2.
The drain electrode of T3 in the first output circuit unit connects the positive bias line, and the grid of T3 connects the drain electrode of T2, and the source electrode of T3 connects the positive pole of Schottky diode D1; The negative pole of D1 connects the positive pole of Schottky diode D2, and the negative pole of D2 connects the positive pole of Schottky diode D3, and the negative pole of D3 connects the positive pole of Schottky diode D4; The negative pole of D4 connects the drain electrode of depletion high electron mobility transistors T4, and the grid of T4 and source electrode connect the negative bias line, and the drain electrode of T4 meets grid and the second output VOUT1 of depletion high electron mobility transistors T6.
The drain electrode of enhancement type high electron mobility transistor T5 in the second negative circuit unit connects the positive bias line, after the source electrode of T5 and its grid short circuit, respectively with the drain electrode of T6 and the second output circuit unit in the grid of depletion high electron mobility transistors T7 join; The grid of T6 connects the first output VOUT1, the source ground line of T6.
The drain electrode of T7 in the second output circuit unit connects the positive bias line, the grid of T7 connect T6 drain electrode, the source electrode of T7 connects the positive pole of Schottky diode D5; The negative pole of D5 connects the positive pole of Schottky diode D6, and the negative pole of D6 connects the positive pole of Schottky diode D7, and the negative pole of D7 connects the positive pole of Schottky diode D8; The negative pole of D8 connects the drain electrode of enhancement type high electron mobility transistor T8, and the grid of T8 and source electrode connect the negative bias line, and the drain electrode of T8 meets the second output VOUT2.
Compared with prior art, the present invention has the following advantages:
First, because the present invention has designed a kind of circuit structure, overcome in prior art due to gallium nitride material p-type doping difficulty, cause in the structure of prior art NPN transistor used irrealizable deficiency still on gallium nitride, solved gallium nitrate based Circuits System monolithic and there is no the problem of appropriate circuitry topological structure in integrated process, circuit structure of the present invention is simple, semiconductor device technology used is realized simple, make the present invention can be on gallium nitrate based, realize that the monolithic integrated circuit that the output with the standard silicon-based electronic circuits is complementary is integrated.
Second, because the present invention can realize that gallium nitrate based Circuits System monolithic is integrated, having overcome in the prior art uses gold thread may bring the deficiency of signal cross-talk between silicon-based electronic circuits and gallium nitrate based circuit, solved the problem of the circuit function normal expression that in silicon-based electronic circuits and gallium nitrate based circuit wafer, interconnection causes, make the present invention have gallium nitrate based system error rate and reduce, the advantage that performance is more stable.
The 3rd, because the present invention can realize that gallium nitrate based radio frequency circuit system monolithic is integrated, overcome the relatively poor deficiency of silicon-based electronic circuits Radiation hardness in the prior art, solved Circuits System in the problem of particular surroundings as descending at outer space performance, make the present invention have a Circuits System Radiation hardness stronger, the advantage that reliability is higher.
Description of drawings
Fig. 1 is circuit theory diagrams of the present invention;
Fig. 2 is the analogous diagram that output end voltage VOUT1 of the present invention and VOUT2 respond input terminal voltage VIN.
Embodiment:
With reference to the accompanying drawings the present invention is described in further detail.
With reference to Fig. 1, circuit structure of the present invention is described below:
The present invention includes the first output circuit, the second negative circuit, the second output circuit.The input of the output of the first negative circuit and the first output circuit joins, and the input of the output of the first output circuit and the second negative circuit joins, and the input of the output of the second negative circuit and the second output circuit joins.
The drain electrode of depletion high electron mobility transistors T1 in the first negative circuit meets positive bias line VDD, after the source electrode of T1 and its grid short circuit, join with the drain electrode of enhancement type high electron mobility transistor T2 and the grid of the enhancement type high electron mobility transistor T3 in the first output circuit unit respectively; The grid of T2 meets input VIN, the source ground line GND of T2.
The drain electrode of T3 in the first output circuit meets positive bias line VDD, and the grid of T3 connects the drain electrode of T2, and the source electrode of T3 connects the positive pole of Schottky diode D1; The negative pole of D1 connects the positive pole of Schottky diode D2, and the negative pole of D2 connects the positive pole of Schottky diode D3, and the negative pole of D3 connects the positive pole of Schottky diode D4; The negative pole of D4 connects the drain electrode of depletion high electron mobility transistors T4, and the grid of T4 and source electrode meet negative bias line VSS, and the drain electrode of T4 meets grid and the second output VOUT1 of depletion high electron mobility transistors T6.
The breadth length ratio of enhancement type high electron mobility transistor T2, T3, T5, T8 is identical, the breadth length ratio of depletion high electron mobility transistors T1, T4, T6, T7 is identical, and the physical size of Schottky diode D1, D2, D3, D4, D5, D6, D7, D8 is identical.
The first negative circuit in the present invention and the first output circuit operation principle are:
If input VIN is low level, enhancement type high electron mobility transistor T2 turn-offs, thereby the T2 channel resistance is larger, but the upper grid voltage of depletion high electron mobility transistors T1 is 0, therefore the channel resistance of the relative T2 of channel resistance is much smaller, so the output of the first negative circuit obtains the voltage near VDD in the dividing potential drop of raceway groove.Because enhancement type high electron mobility transistor T3 grid voltage is near VDD, T3 opens.And then the channel resistance of T3 is less than the channel resistance of T4.Through four Schottky diode step-downs such as Schottky diode D1, D2, D3, D4, the output VOUT1 of the first output circuit can be adjusted into the 0V left and right.
In embodiments of the invention, by the technique adjusted, making the breadth length ratio of T3 and the breadth length ratio of depletion high electron mobility transistors T4 is 5～8.So selecting is in order to make T3 compare T4, a larger mutual conductance to be arranged, and can satisfy T3 and be slightly less than the channel resistance of T4 at the situation lower channel resistance of opening in this scope, can satisfy again T3 at the channel resistance of the situation lower channel resistance that turn-offs much larger than T4.Less than 5 the time, the mutual conductance of T3 is too little when this breadth length ratio, in the situation that it is too little to open dividing potential drop, the high level that makes output VOUT1 is much smaller than 0V and function can not normally realize; Greater than 8 the time, the T3 mutual conductance is too large when this breadth length ratio, in the situation that it is too large to turn-off dividing potential drop, the low level that makes output VOUT1 is far above-4V and function can not normally realize.
If input VIN is low-voltage, T2 opens, and because the breadth length ratio of T2 and T1 is 5～8, so the channel resistance of T1 wants several times in the channel resistance of T2, thereby first negative circuit be output as near 0V, make T3 turn-off, thereby the channel resistance of T3 will be much larger than the channel resistance of T4, thereby the output VOUT1 of the first output circuit is near VSS.
The drain electrode of enhancement type high electron mobility transistor T5 in the second negative circuit unit connects the positive bias line, after the source electrode of T5 and its grid short circuit, respectively with the drain electrode of T6 and the second output circuit unit in the grid of depletion high electron mobility transistors T7 join; The grid of T6 meets the first output VOUT1, the source ground line of T6.
The drain electrode of T7 in the second output circuit unit connects the positive bias line, the grid of T7 connect T6 drain electrode, the source electrode of T7 connects the positive pole of Schottky diode D5; The negative pole of D5 connects the positive pole of Schottky diode D6, and the negative pole of D6 connects the positive pole of Schottky diode D7, and the negative pole of D7 connects the positive pole of Schottky diode D8; The negative pole of D8 connects the drain electrode of enhancement type high electron mobility transistor T8, and the grid of T8 and source electrode connect the negative bias line, and the drain electrode of T8 meets the second output VOUT2.
The second negative circuit in the present invention and the second output circuit operation principle are:
The output VOUT1 that is input as the first output circuit of this module in conjunction with above-mentioned principle, learns that concerning the output VOUT1 of the first output circuit, VIN is low level, and VOUT1 is high level and near 0V, VIN is high level, and VOUT1 is low level and near VSS.
If input VIN is high level, VOUT1 is low level, depletion high electron mobility transistors T6 turn-offs, thereby the T6 channel resistance is larger, but the upper grid voltage of enhancement type high electron mobility transistor T5 is 0V, therefore the channel resistance of the relative T5 of channel resistance of T6 is much bigger, and therefore the output of the first negative circuit obtains near VSS in the dividing potential drop of raceway groove.Because depletion high electron mobility transistors T7 grid voltage is near VSS, thus the T7 unlatching, and then the channel resistance of T7 is less than the channel resistance of T8.By the technique adjusted, making the breadth length ratio of T7 and the breadth length ratio of depletion high electron mobility transistors T8 is 5～8, and through Schottky diode D1, D2, D3, four diode step-downs of D4, the output VOUT2 of the second output circuit can be adjusted into the VDD left and right and be high level.
If input VIN is low-voltage, the VOUT1 end is high level, and T6 opens, and because the breadth length ratio of T6 and T5 is 5～8, so the channel resistance of T5 wants several times in the channel resistance of T6, thereby the first negative circuit is output as near 0V, make T7 turn-off, thereby T7 have larger channel resistance.And T8 is owing to being 0 for enhance device and grid voltage, thus larger channel resistance is also arranged, but be 5～8 times of T7 due to the breadth length ratio of T8, so the channel resistance of T8 is less than the channel resistance of T7.Through the step-down of Schottky diode D5, D6, D7, D8, the output VOUT2 that makes the second output circuit is low level.
Below in conjunction with Fig. 2 analogous diagram, effect of the present invention is further described.
With reference to Fig. 2, the output of the present invention's the second negative circuit and the output VOUT2 of the second output circuit are described below with the analogous diagram of input voltage VIN response respectively:
The input VIN input range of emulation of the present invention is that 0-5V is direct current scanning, and thinks that VIN is input low level when VIN＜0.4V, and during VIN＞2.4V, VIN is input high level; VDD=5V, VSS=-5V; Think when output＞-be the output high level during 2V, output＜-be output low level during 3V.
The present invention is carried out emulation in as above simulated conditions, obtain simulation result as shown in Figure 2.In Fig. 2, transverse axis represents input terminal voltage VIN, and the longitudinal axis represents output end voltage, and the dotted line in Fig. 2 represents to export VOUT1, and solid line represents to export VOUT2.
When input terminal voltage VIN was low level, the second negative circuit was output as low level, and was about 0V, and output VOUT2 is low level, and be-4V about; When input terminal voltage VIN was high level, the second negative circuit was output as high level, and was the 0V left and right, and output VOUT2 is high level, and was the 0V left and right.Therefore, during at low level and high level Transforms, VOUT1 and VOUT2 can both be with level at high level and low level Transforms as VIN.Therefore the present invention can realize the function of level conversion.
Claims (8)
1. a gallium nitrate based enhancing depletion type level shifting circuit, comprise the first negative circuit, the first output circuit, the second negative circuit, the second output circuit; The input of the output of described the first negative circuit and the first output circuit joins, and the input of the output of the first output circuit and the second negative circuit joins, and the input of the output of the second negative circuit and the second output circuit joins; Wherein:
The drain electrode of depletion high electron mobility transistors T1 in described the first negative circuit unit connects the positive bias line, after the source electrode of T1 and its grid short circuit, be connected with the grid of enhancement type high electron mobility transistor T3 in the drain electrode of enhancement type high electron mobility transistor T2 and the first output circuit unit respectively; The grid of T2 connects input VIN, the source ground line of T2;
The drain electrode of T3 in described the first output circuit unit connects the positive bias line, and the grid of T3 connects the drain electrode of T2, and the source electrode of T3 connects the positive pole of Schottky diode D1; The negative pole of D1 connects the positive pole of Schottky diode D2, and the negative pole of D2 connects the positive pole of Schottky diode D3, and the negative pole of D3 connects the positive pole of Schottky diode D4; The negative pole of D4 connects the drain electrode of depletion high electron mobility transistors T4, and the grid of T4 and source electrode connect the negative bias line, and the drain electrode of T4 meets grid and the second output VOUT1 of depletion high electron mobility transistors T6;
The drain electrode of enhancement type high electron mobility transistor T5 in described the second negative circuit unit connects the positive bias line, after the source electrode of T5 and its grid short circuit, respectively with the drain electrode of T6 and the second output circuit unit in the grid of depletion high electron mobility transistors T7 join; The grid of T6 connects the first output VOUT1, the source ground line of T6;
The drain electrode of T7 in described the second output circuit unit connects the positive bias line, the grid of T7 connect T6 drain electrode, the source electrode of T7 connects the positive pole of Schottky diode D5; The negative pole of D5 connects the positive pole of Schottky diode D6, and the negative pole of D6 connects the positive pole of Schottky diode D7, and the negative pole of D7 connects the positive pole of Schottky diode D8; The negative pole of D8 connects the drain electrode of enhancement type high electron mobility transistor T8, and the grid of T8 and source electrode connect the negative bias line, and the drain electrode of T8 meets the second output VOUT2.
2. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, the breadth length ratio of described enhancement type high electron mobility transistor T2, T3, T5, T8 is identical.
3. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, described enhancement type high electron mobility transistor T2, T3, T5, T8 threshold voltage are greater than zero.
4. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, the breadth length ratio of described depletion high electron mobility transistors T1, T4, T6, T7 is identical.
5. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, the threshold voltage of described depletion high electron mobility transistors T1, T4, T6, T7 is less than zero.
6. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, the physical size of described Schottky diode D1, D2, D3, D4, D5, D6, D7, D8 is identical.
7. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, described enhancement type high electron mobility transistor breadth length ratio is 5～8 times of depletion high electron mobility transistors breadth length ratio.
8. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, described positive bias line voltage equates with negative bias line voltage value, opposite in sign.
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| CN201310055261.9A CN103117739B (en) | 2013-01-31 | 2013-01-31 | GaN-based enhancement-depletion type level switch circuit |
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| CN201310055261.9A CN103117739B (en) | 2013-01-31 | 2013-01-31 | GaN-based enhancement-depletion type level switch circuit |
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| CN103117739B CN103117739B (en) | 2015-06-17 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106992776A (en) * | 2017-03-28 | 2017-07-28 | 西安电子科技大学 | Gallium nitride base strengthens depletion type level conversion performance improvement circuit |
| CN110247651A (en) * | 2019-07-05 | 2019-09-17 | 中国电子科技集团公司第二十四研究所 | A kind of positive-pressure rotary negative pressure logic circuit based on GaAs HEMT technique |
| CN116054810A (en) * | 2022-07-11 | 2023-05-02 | 荣耀终端有限公司 | Level conversion circuit and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4661725A (en) * | 1984-02-08 | 1987-04-28 | U.S. Philips Corporation | Elementary logic circuit obtained by means of field effect transistors of gallium arsenide and compatible with the ECL 100 K technology |
| JPH05243972A (en) * | 1992-02-28 | 1993-09-21 | Sony Corp | Compound semiconductor integrated circuit device |
| CN1734941A (en) * | 2005-08-30 | 2006-02-15 | 上海复旦微电子股份有限公司 | Level switching circuit |
-
2013
- 2013-01-31 CN CN201310055261.9A patent/CN103117739B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4661725A (en) * | 1984-02-08 | 1987-04-28 | U.S. Philips Corporation | Elementary logic circuit obtained by means of field effect transistors of gallium arsenide and compatible with the ECL 100 K technology |
| JPH05243972A (en) * | 1992-02-28 | 1993-09-21 | Sony Corp | Compound semiconductor integrated circuit device |
| CN1734941A (en) * | 2005-08-30 | 2006-02-15 | 上海复旦微电子股份有限公司 | Level switching circuit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106992776A (en) * | 2017-03-28 | 2017-07-28 | 西安电子科技大学 | Gallium nitride base strengthens depletion type level conversion performance improvement circuit |
| CN106992776B (en) * | 2017-03-28 | 2020-02-21 | 西安电子科技大学 | Gallium nitride-based enhanced depletion type level switching circuit |
| CN110247651A (en) * | 2019-07-05 | 2019-09-17 | 中国电子科技集团公司第二十四研究所 | A kind of positive-pressure rotary negative pressure logic circuit based on GaAs HEMT technique |
| CN110247651B (en) * | 2019-07-05 | 2024-04-30 | 中国电子科技集团公司第二十四研究所 | Positive-voltage-to-negative-voltage logic circuit based on GaAs HEMT technology |
| CN116054810A (en) * | 2022-07-11 | 2023-05-02 | 荣耀终端有限公司 | Level conversion circuit and electronic device |
| CN116054810B (en) * | 2022-07-11 | 2023-11-14 | 荣耀终端有限公司 | Level conversion circuit and electronic device |
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| CN103117739B (en) | 2015-06-17 |
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Effective date of registration: 20170614 Address after: 650221 Yunnan city of Kunming province Dabanqiao Street office office building No. 7 room 7-114 Patentee after: Yunnan Hui Hui Electronic Technology Co., Ltd. Address before: Xi'an City, Shaanxi province Taibai Road 710071 No. 2 Patentee before: Xidian University |