CN116054810B

CN116054810B - Level conversion circuit and electronic device

Info

Publication number: CN116054810B
Application number: CN202210809036.9A
Authority: CN
Inventors: 宁林琼; 赵楠; 赵礼列; 郑盼攀
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-07-11
Filing date: 2022-07-11
Publication date: 2023-11-14
Anticipated expiration: 2042-07-11
Also published as: CN116054810A

Abstract

The application discloses a level conversion circuit and electronic equipment, relates to the technical field of electronics, and is used for realizing level conversion on an MDC signal line through the circuit. The level shift circuit includes: the input end, the output end and the high-level conduction branch circuit; an input for coupling to a master device powered by a first voltage and an output for coupling to a slave device powered by a second voltage; the high-level conduction branch comprises a first reversing circuit and a second reversing circuit which are coupled in series between the input end and the output end; the second reverse circuit inputs a second voltage; the first reverse circuit is used for outputting a low level to the second reverse circuit when the input end inputs the high level of the first voltage; the second inverting circuit is configured to output a high level of the second voltage to the output terminal when the low level is input from the first inverting circuit.

Description

Level conversion circuit and electronic device

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a level shifter circuit and an electronic device.

Background

The serial management interface (serial management interface, SMI) is a serial interface for communication between a master device and a slave device, and includes a management data clock (management data clock, MDC) signal line and a management data input output (management data input output, MDIO) signal line.

Because the input voltages of the master device and the slave device may be different, the voltages corresponding to the high levels are different, and the signal edge jump time of the MDC signal line is required to be very short, a special high-speed level conversion chip is usually connected to the MDC signal line to convert the different voltages of the high levels (simply referred to as level conversion), but the special chip is expensive, and the product cost is increased.

Disclosure of Invention

The embodiment of the application provides a level conversion circuit and electronic equipment, which are used for realizing conversion of high level between different voltages through the circuit.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

in a first aspect, there is provided a level shift circuit comprising: the input end, the output end and the high-level conduction branch circuit; an input for coupling to a master device powered by a first voltage and an output for coupling to a slave device powered by a second voltage; the high-level conduction branch comprises a first reversing circuit and a second reversing circuit which are coupled in series between the input end and the output end; the second reverse circuit inputs a second voltage; the first reverse circuit is used for outputting a low level to the second reverse circuit when the input end inputs the high level of the first voltage; the second inverting circuit is configured to output a high level of the second voltage to the output terminal when the low level is input from the first inverting circuit.

The low level of the level conversion circuit disclosed by the application is defined as 0V under different voltage classes, but the voltages corresponding to the high level are different, so that for the high level of the input first voltage, the high level is converted into the low level through the first reversing circuit, and then the low level is converted into the high level of the second voltage through the second reversing circuit powered by the second voltage. The conversion of the high level between different voltages is realized through the circuit.

In one possible implementation, the first inverting circuit includes a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor are coupled to the input, the first terminal of the first transistor is for inputting the second voltage, the second terminal of the first transistor and the first terminal of the second transistor are coupled to the second inverting circuit, and the second terminal of the second transistor is grounded. The inverter formed by the first transistor and the second transistor inverts the signal and increases the driving current, the on-resistance of these transistors is small, and a large driving current is provided, and when a high level is input, the level output from the level conversion circuit can be quickly pulled up to the high level of the second voltage, thereby reducing the rising time of the rising edge.

In one possible implementation, the first transistor is a P-type metal oxide semiconductor field effect transistor, the first end of the first transistor is a source, the second end of the first transistor is a drain, the second transistor is an N-type metal oxide semiconductor field effect transistor, the first end of the second transistor is a drain, and the second end of the second transistor is a source.

In one possible implementation, the second inverting circuit includes a third transistor having a gate coupled to the first inverting circuit, a first terminal of the third transistor inputting the second voltage, and a second terminal of the third transistor coupled to the output terminal. The third transistor further increases the driving current, the on-resistance of the transistor is small, and a large driving current is provided, and when a high level is input, the level output from the level shift circuit can be quickly pulled up to the high level of the second voltage, thereby reducing the rising time of the rising edge.

In one possible implementation, the third transistor is a P-type metal oxide semiconductor field effect transistor, the first end of the third transistor is a source, and the second end of the third transistor is a drain.

In one possible embodiment, the circuit further comprises a low-level conduction branch, the low-level conduction branch and the high-level conduction branch being coupled in parallel between the input terminal and the output terminal; the low level conduction branch is used for outputting low level to the output terminal when the input terminal inputs low level. The low level conduction branch circuit is disconnected when the input end inputs high level, and is conducted when the input end inputs low level, and the low level is defined as 0V under different voltage levels, so that the low level does not need to be subjected to level conversion.

In one possible implementation, the low-level turn-on branch includes a fourth transistor having a gate input the first voltage, a first terminal coupled to the input terminal, and a second terminal coupled to the output terminal. When the input end inputs high level, the fourth transistor is cut off, and current is prevented from flowing through the low level conduction branch.

In one possible implementation, the fourth transistor is an N-type metal oxide semiconductor field effect transistor, the first end of the fourth transistor is a source, and the second end of the fourth transistor is a drain.

In one possible implementation, the level shift circuit further includes a resistor, and the output terminal is grounded through the resistor. The resistor is used as a pull-down resistor and is used for shunting the current output by the output end, so that the excessive current is prevented from being input to a coupled device, and the device is damaged.

In a second aspect, there is provided an electronic device comprising a master device, a slave device and a level shifting circuit as described in any of the first aspect and any of its embodiments, the master device being coupled to the slave device via a management data clock signal line of a serial management interface and the level shifting circuit.

The technical effects of the second aspect refer to the technical effects of the first aspect and any of its embodiments and are not repeated here.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of another electronic device according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of still another electronic device according to an embodiment of the present application;

fig. 4 is a schematic diagram of simulation waveforms of an MDIO signal output by a master device and an MDIO signal received by a slave device according to an embodiment of the present application;

FIG. 5 is a schematic diagram of simulation waveforms of an MDIO signal output by a slave device and an MDIO signal received by a master device according to an embodiment of the present application;

fig. 6 is a schematic diagram of simulation waveforms of an MDC signal output by a master device and an MDC signal received from a slave device according to an embodiment of the application.

Detailed Description

Some concepts to which the present application relates will be described first.

The terms "first," "second," and the like, in accordance with embodiments of the present application, are used solely for the purpose of distinguishing between similar features and not necessarily for the purpose of indicating a relative importance, number, sequence, or the like.

The terms "exemplary" or "such as" and the like, as used in relation to embodiments of the present application, are used to denote examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

The terms "coupled" and "connected" in accordance with embodiments of the application are to be construed broadly, and may refer, for example, to a physical direct connection, or to an indirect connection via electronic devices, such as, for example, electrical resistance, inductance, capacitance, or other electrical devices.

In an electronic device such as a router or a switch, communication between a master device (e.g., a processor) and a slave device (e.g., a slave device) can be performed through an SMI interface. Since the master and slave devices may use different input voltages, for example, the input voltage of the master device is 3.3V, the input voltage of the slave device is 5V, the low level is defined as 0V at different voltage levels, but the corresponding voltages of the high level are different. The signal edge jump time of the MDC signal line in the SMI interface is required to be very short, so that a special high-speed level conversion chip is usually coupled to the MDC signal line to convert different voltages with high level (simply called level conversion), but the special chip is expensive, and the product cost is increased.

The embodiment of the application provides electronic equipment which can be a router, a switch, a mobile phone, a computer, a tablet and the like, and is not particularly limited. As shown in fig. 1, the electronic device 10 includes a master device 101, a slave device 102, a first level shift circuit 103, and a second level shift circuit 104. The master device 101 may be a control chip such as a processor, a controller, etc., and the slave device 102 may be a controlled chip such as a network interface controller (network interface controller, NIC), a register, etc. The master device 101 and the slave device 102 communicate with each other through an SMI interface.

The MDC interface of the master device 101 is coupled to the MDC interface of the slave device 102 through an MDC signal line, which is a unidirectional transmission line from the master device 101 to the slave device 102, for transmitting an MDC signal (clock) to the slave device 102 by the master device 101, and a first level shift circuit 103 for level shifting the MDC signal. The MDIO interface of the master device 101 is coupled to the MDIO interface of the slave device 102 through an MDIO signal line and a second level shifter circuit 104. The MDIO signal line is a bidirectional transmission line between the master device 101 and the slave device 102, and is used for transmitting MDIO signals (data) between the master device 101 and the slave device 102, and the second level conversion circuit 104 is used for level converting the MDIO signals.

Test verification shows that when the frequency of the MDC signal is configured to be 2.5MHz, in order to ensure that the whole SMI interface can normally transmit data, the rising time of the rising edge and the falling time of the falling edge of the MDC signal are required to be less than 20ns, and the rising time of the rising edge of the MDIO signal is required to be less than 50ns.

As shown in fig. 2 and 3, the second level shift circuit 104 includes a transistor T1, a resistor R1, and a resistor R2. The transistor T1 may be an N-type metal oxide semiconductor field effect transistor (metal oxide semiconductor field effect transistor, MOSFET) (abbreviated as N-type MOS transistor). The first terminal P21 of the second level shifter circuit 104 is coupled to the first terminal of the resistor R1 and the first terminal (e.g., source) of the transistor T1, and the second terminal (e.g., drain) of the transistor T1 and the second terminal of the second resistor R2 are coupled to the second terminal P22 of the second level shifter circuit 104. The difference between fig. 2 and 3 is that:

in fig. 2, the supply voltage (first voltage V1) of the master device 101 is smaller than the supply voltage (second voltage V2) of the slave device 102. The first terminal P21 of the second level shifter circuit 104 is coupled to the MDIO interface of the master device 101 through an MDIO signal line, and the second terminal P22 of the second level shifter circuit 104 is coupled to the MDIO interface of the slave device 102 through an MDIO signal line. The second terminal of the resistor R1 and the gate of the transistor T1 input a first voltage V1 (e.g., 3.3V), and the first terminal of the second resistor R2 inputs a second voltage V2 (e.g., 5V).

In fig. 3, the supply voltage (first voltage V1) of the master device 101 is greater than the supply voltage (second voltage V2) of the slave device 102. The first terminal P21 of the second level shifter circuit 104 is coupled to the MDIO interface of the slave device 102 through an MDIO signal line, and the second terminal P22 of the second level shifter circuit 104 is coupled to the MDIO interface of the master device 101 through an MDIO signal line. The second terminal of the resistor R1 and the gate of the transistor T1 input a second voltage V2 (e.g., 5V), and the first terminal of the second resistor R2 inputs a first voltage V1 (e.g., 3.3V).

Since the SMI interface has no critical requirement on the rising time of the rising edge of the MDIO signal, the present application realizes level conversion through the transistor T1 and the pull-up resistors (the resistor R1 and the resistor R2), so as to ensure that the rising time of the rising edge of the MDIO signal is less than 50ns. Specifically, taking the second level shifter 104 shown in fig. 2 as an example, the working principle thereof is as follows:

for outputting an MDIO signal from the master device 101 to the slave device 102: when the MDIO signal output from the master device 101 to the first terminal (e.g., source) of the transistor T1 is at a low level, the transistor T1 is turned on, and the second terminal (e.g., drain) of the transistor T1 outputs a low level to the slave device 102. When the MDIO signal output from the master device 101 to the first terminal (e.g., source) of the transistor T1 is at a high level of the first voltage V1 (e.g., 3.3V), the transistor T1 is turned off, and the resistor R2 outputs a high level of the second voltage V2 (e.g., 5V) to the slave device 102 due to the pull-up action of the resistor R2.

The simulation waveforms of the MDIO signal S1 output by the master device 101 and the MDIO signal S2 received by the slave device 101 are shown in fig. 4, and the type of the P-type transistor involved in each simulation waveform in the embodiment of the present application is BS250, and the type of the N-type transistor is 2N7002. The rising time of the rising edge of the MDIO signal S2 is 41ns, and the falling time of the falling edge is 8ns, so that the requirement of the SMI interface is met. For the case where there is a step (shown as P in the figure) in the rising edge of the MDIO signal S2, this can be avoided by selecting a transistor with better performance. The relationship between the on and off of the transistor T1 and the high and low level of the MDIO signal is shown in table 1:

TABLE 1

Master device 101	Transistor T1	Slave device 102
			Low level (0)	Conduction	Low level (0)
High level (1)	Shut off	High level (1)

For outputting an MDIO signal from the master device 101 to the slave device 102: when the MDIO signal output from the device 102 to the second terminal (e.g., drain) of the transistor T1 is at a low level, the transistor T1 is turned on due to the body diode therein, and the first terminal (e.g., source) of the transistor T1 outputs a low level to the main device 101. When the MDIO signal output from the device 102 to the second terminal (e.g., drain) of the transistor T1 is at a high level of the second voltage V2 (e.g., 5V), the transistor T1 is turned off, and the resistor R1 outputs the high level of the first voltage V1 (e.g., 3.3V) to the main device 101 due to the pull-up action of the resistor R1.

The simulation waveforms of the MDIO signal S2 output from the device 101 and the MDIO signal S1 received by the master device 101 are shown in fig. 5, where the rising time of the rising edge of the MDIO signal S1 is 4ns, and the falling time of the falling edge is 8ns, so as to meet the requirements of the SMI interface. For the case where there is a back channel (shown as P in the figure) on the rising edge of the MDIO signal S1, this can be avoided by selecting a transistor with better performance. The relationship between the on and off of the transistor T1 and the high and low level of the MDIO signal is shown in table 2:

TABLE 2

Slave device 102	Transistor T1	Master device 101
			Low level (0)	Conduction	Low level (0)
High level (1)	Shut off	High level (1)

As shown in fig. 2 and 3, the first level shifter 103 includes an input terminal P11, an output terminal P12, a high-level conductive branch 1031, and a low-level conductive branch 1032. The high-level conductive branch 1031 and the low-level conductive branch 1032 are coupled in parallel between the input terminal P11 and the output terminal P12. Input terminal P11 is coupled to the MDC interface of master device 101 and output terminal P12 is coupled to the MDC interface of slave device 102. When the input terminal P11 inputs the high level of the first voltage V1, the high level conduction branch 1031 is turned on and outputs the high level of the second voltage V2 to the output terminal P12; when the input terminal P11 inputs a low level, the low level conductive branch 1032 is conductive and outputs a low level to the output terminal P12.

The high-level turn-on branch 1031 includes a first inverting circuit 10311 and a second inverting circuit 10312 coupled in series between the input terminal P11 and the output terminal P12, the first inverting circuit 10311 inputting the second voltage V2, the second inverting circuit 10312 inputting the second voltage V2 (i.e., being supplied by the second voltage V2). The first inverting circuit 10311 is configured to output a low level to the second inverting circuit 10312 when the input terminal P11 inputs a high level of the first voltage V1. The second inverting circuit 10312 is configured to output a high level of the second voltage V2 to the output terminal P12 when a low level is input from the first inverting circuit 10311.

The first inverting circuit 10311 includes a transistor T2 and a transistor T3, the second inverting circuit 10312 includes a transistor T4, the transistor T2 may be an N-type MOS transistor, the transistor T3 may be a P-type MOS transistor, and the transistor T4 may be a P-type MOS transistor. The first inverting circuit 10311 inverts the signal through the inverter made up of the transistor T2 and the transistor T3 while increasing the driving current (i.e., increasing the driving capability), the transistor T4 further increases the driving current (i.e., further increases the driving capability), the on-resistance of these transistors in the high-level on-branch 1031 is small, and a larger driving current is provided, and when a high level is input, the level at the MDC interface of the slave device 102 can be quickly pulled up to the high level of the second voltage, thereby reducing the rising time of the rising edge.

The gate of the transistor T2 and the gate of the transistor T3 are coupled to the input terminal P11, the first terminal (e.g., source) of the transistor T3 is used for inputting the second voltage V2, the second terminal (e.g., drain) of the transistor T3 and the first terminal (e.g., drain) of the transistor T2 are coupled to the gate of the transistor T4 in the second inverting circuit 10312, and the second terminal (e.g., source) of the transistor T2 is grounded. A first terminal (e.g., source) of the transistor T4 inputs the second voltage V2, and a second terminal (e.g., drain) of the transistor T4 is coupled to the output terminal P12.

The low-level conductive branch 1032 includes a transistor T5, and the transistor T5 may be an N-type MOS transistor. The gate of the transistor T5 inputs the first voltage V1, a first terminal (e.g., source) of the transistor T5 is coupled to the input terminal P11, and a second terminal (e.g., drain) of the transistor T5 is coupled to the output terminal P12.

Optionally, the first level shifter 103 further includes a resistor R3, and the output terminal P12 is grounded through the resistor R3. The resistor R3 is used as a pull-down resistor, and is used for shunting the current output by the output terminal P12, so as to avoid that excessive current is input into the slave device 102, and damage the slave device 102.

The first level shift circuit 103 operates as follows:

when the MDC signal output from the master device 101 to the first terminal (e.g., source) of the transistor T1 is at a low level, the transistor T3 is turned on, the transistors T2 and T4 are turned off, the transistor T5 is turned on, and the second terminal (e.g., drain) of the transistor T5 outputs a low level to the slave device 102. When the MDIO signal output from the master device 101 to the first terminal (e.g., source) of the transistor T1 is at a high level of the first voltage V1 (e.g., 3.3V), the transistor T3 is turned off, the transistors T2 and T4 are turned on, the transistor T5 is turned off, and the second terminal (e.g., drain) of the transistor T4 outputs a high level of the second voltage V2 to the slave device 102.

As shown in fig. 6, the simulation waveforms of the MDC signal S1 output from the master device 101 and the MDC signal S2 received from the slave device 101 show that the frequency of the MDC signal S1 is 2.5mhz, the rising time of the rising edge and the falling time of the falling edge of the MDC signal S1 are 5ns, the duty ratio is 50%, the low level is 0V, and the high level is 3.3V. From the simulation waveforms, the phase of the MDC signal S2 is not significantly delayed with respect to the MDC signal S1 before the level conversion, the rising time of the rising edge of the MDC signal S2 is 18ns (within 20 ns), the falling time of the falling edge is 4ns, the maximum voltage of the high level is 5.02V, the minimum voltage of the low level is-4 mV, and the requirements of the SMI interface are satisfied. For the case where there is a back channel (shown as P in the figure) on the rising edge of the MDC signal S2, this can be avoided by selecting a transistor with better performance. The relationship between the on and off of the transistors T2-T4 and the high and low levels of the MDC signal is shown in table 3:

TABLE 3 Table 3

Master device 101	Transistor T2	Transistor T3	Transistor T4	Transistor T5	Slave device 102
						Low level (0)	Shut off	Conduction	Shut off	Conduction	Low level (0)
High level (1)	Conduction	Shut off	Conduction	Shut off	High level (1)

The low level of the level conversion circuit and the electronic equipment is defined as 0V under different voltage classes, but the voltages corresponding to the high level are different, so that the high level of the input first voltage is converted into the low level through the first reverse circuit, and then the low level is converted into the high level of the second voltage through the second reverse circuit powered by the second voltage. The conversion of the high level between different voltages is realized through the circuit.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system, apparatus and module may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or components may be combined or integrated into another device, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, indirect coupling or communication connection of devices or modules, electrical, mechanical, or other form.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physically separate, i.e., may be located in one device, or may be distributed over multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A level shifter circuit, comprising: the input end, the output end and the high-level conduction branch circuit; the high-level conduction branch circuit comprises a first transistor, a second transistor and a third transistor; the input end is used for being coupled to the master device through a first management data clock signal line of the serial management interface, and the output end is used for being coupled to the slave device through a second management data clock signal line of the serial management interface; a gate of the first transistor and a gate of the second transistor are coupled to the input terminal, a first terminal of the first transistor is used for inputting a second voltage, a second terminal of the first transistor and a first terminal of the second transistor are coupled to a gate of the third transistor, and a second terminal of the second transistor is grounded; a first terminal of the third transistor inputs the second voltage, a second terminal of the third transistor is coupled to the output terminal;

when the management data clock signal input by the input end is at the high level of the first voltage, the management data clock signal output by the output end is at the high level of the second voltage.

2. The circuit of claim 1, wherein the first transistor is a P-type metal oxide semiconductor field effect transistor, the first end of the first transistor is a source, the second end of the first transistor is a drain, the second transistor is an N-type metal oxide semiconductor field effect transistor, the first end of the second transistor is a drain, and the second end of the second transistor is a source.

3. The circuit of claim 1, wherein the third transistor is a P-type metal oxide semiconductor field effect transistor, a first terminal of the third transistor is a source, and a second terminal of the third transistor is a drain.

4. A circuit according to any of claims 1-3, wherein the level shifting circuit further comprises a low level conductive branch, the low level conductive branch and the high level conductive branch being coupled in parallel between the input and the output;

the low level conduction branch is used for outputting low level to the output end when the input end inputs low level.

5. The circuit of claim 4, wherein the low-level turn-on branch comprises a fourth transistor having a gate that inputs the first voltage, a first terminal coupled to the input terminal, and a second terminal coupled to the output terminal.

6. The circuit of claim 5, wherein the fourth transistor is an N-type metal oxide semiconductor field effect transistor, a first terminal of the fourth transistor is a source, and a second terminal of the fourth transistor is a drain.

7. The circuit of any of claims 1-6, wherein the level shifter circuit further comprises a resistor through which the output is grounded.

8. An electronic device comprising a master device, a slave device and a level shifting circuit as claimed in any one of claims 1-7, the master device being coupled to the slave device via a management data clock signal line of a serial management interface and the level shifting circuit.