CN114095013A - Level conversion circuit and switching power supply - Google Patents

Level conversion circuit and switching power supply Download PDF

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Publication number
CN114095013A
CN114095013A CN202111320094.7A CN202111320094A CN114095013A CN 114095013 A CN114095013 A CN 114095013A CN 202111320094 A CN202111320094 A CN 202111320094A CN 114095013 A CN114095013 A CN 114095013A
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China
Prior art keywords
transistor
level
coupled
voltage
power supply
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Pending
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CN202111320094.7A
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Chinese (zh)
Inventor
荣家敬
吴松波
陈定昌
薄春生
陆霄
冯玉明
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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Application filed by Gree Electric Appliances Inc of Zhuhai, Zhuhai Zero Boundary Integrated Circuit Co Ltd filed Critical Gree Electric Appliances Inc of Zhuhai
Priority to CN202111320094.7A priority Critical patent/CN114095013A/en
Publication of CN114095013A publication Critical patent/CN114095013A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

The application relates to a level conversion circuit and a switching power supply. The level shift circuit includes: the first level conversion module is used for converting a first level signal into a second level signal of a second voltage domain under the condition of receiving the first level signal of the first voltage domain, wherein the power supply voltage of the first voltage domain is different from that of the second voltage domain, and the potential of the second level signal is opposite to that of the first level signal; and the second level conversion module is coupled with the first level conversion module and is used for converting the second level signal into a third level signal of a second voltage domain, wherein the third level signal has the same potential as the first level signal. The technical problem that level conversion can be realized only by combining a latch circuit is solved.

Description

Level conversion circuit and switching power supply
Technical Field
The application relates to the technical field of electronic circuit design, in particular to a level conversion circuit and a switching power supply.
Background
The circuit design is very complex as a whole, but the complex whole can be split into a plurality of simple modules, each module realizes independent function, and finally the modules are integrated into a product. However, the operating environment of each module may be different, such as a module using a device in a 3.3V voltage domain, and a module using a device in a 5V voltage domain. If signal transmission across voltage domains is required in a circuit design, a level shift circuit is required to shift signals from one voltage domain to another.
Referring to fig. 1, a level shift circuit exists in the related art, however, the level shift circuit needs to rely on a latch function to implement level shift, and the level shift circuit needs 11 MOS transistors, including 6 low-voltage transistors and 5 high-voltage transistors, and the area of the high-voltage transistor is about 9 times larger than that of the low-voltage transistor due to the manufacturing process of the high-voltage transistor, which results in a complex structure and high cost of the level shift circuit.
In order to solve the problem that the level conversion can be realized only by combining a latch circuit, an effective solution is not provided at present.
Disclosure of Invention
The application provides a level conversion circuit and a switching power supply, which aim to solve the technical problem that level conversion can be realized only by combining a latch circuit.
According to an aspect of an embodiment of the present application, there is provided a level shift circuit including:
the first level conversion module is used for converting a first level signal into a second level signal of a second voltage domain under the condition of receiving the first level signal of the first voltage domain, wherein the power supply voltage of the first voltage domain is different from that of the second voltage domain, and the potential of the second level signal is opposite to that of the first level signal;
and the second level conversion module is coupled with the first level conversion module and is used for converting the second level signal into a third level signal of a second voltage domain, wherein the third level signal has the same potential as the first level signal.
Optionally, the first level shift module includes:
the input end of the current mirror is coupled with the first power supply;
the grid electrode of the first transistor is coupled with the signal output end of the first voltage domain, the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is coupled with the grounding end of the current mirror;
and a first port of the clamper is coupled with a second power supply, a second port of the clamper is coupled with the first power supply, and a third port of the clamper is coupled with the output end of the current mirror.
Optionally, a power supply voltage of the first power supply is smaller than a power supply voltage of the second power supply, the first power supply is used for driving the transistor in the clamp to be turned on, the power supply voltage of the second power supply is the same as a power supply voltage of a second voltage domain, and the second power supply is used for generating a high potential of the second voltage domain.
Optionally, the current mirror comprises:
the drain electrode of the second transistor is the output end of the current mirror, and the source electrode of the second transistor is coupled with the drain electrode of the first transistor;
and the drain electrode of the third transistor is the input end of the current mirror, the grid electrode of the third transistor is coupled with the grid electrode of the second transistor, the source electrode of the third transistor is coupled with the drain electrode of the first transistor, and the drain electrode of the third transistor is connected with the grid electrode of the third transistor.
Optionally, a first resistor is further connected in series between the drain of the third transistor and the first power supply, and the first resistor is used for generating a driving current of the current mirror.
Optionally, the clamp comprises:
one end of the second resistor is a first port of the clamper;
and the drain electrode of the fourth transistor is coupled with the other end of the second resistor, the grid electrode of the fourth transistor is a second port of the clamper, and the source electrode of the fourth transistor is a third port of the clamper.
Optionally, the second level shift module includes:
and the first side port of the inverter is coupled with the second power supply, the second side port of the inverter is coupled with a reference voltage port, the reference voltage port is used for generating a low potential of the second voltage domain, the input end of the inverter is respectively coupled with the drain electrode of the second transistor and the source electrode of the fourth transistor, and the output end of the inverter is coupled with the input end of the second voltage domain.
Optionally, the inverter comprises:
a source electrode of the fifth transistor is a first side port of the inverter, a grid electrode of the fifth transistor is an input end of the inverter, and a drain electrode of the fifth transistor is an output end of the inverter;
and the grid electrode of the sixth transistor is coupled with the grid electrode of the fifth transistor, the drain electrode of the sixth transistor is coupled with the drain electrode of the fifth transistor, and the source electrode of the sixth transistor is the second side port of the inverter.
Optionally, the first transistor, the second transistor, the third transistor, and the sixth transistor are low-voltage NMOS transistors, the fourth transistor is a high-voltage NMOS transistor, and the fifth transistor is a low-voltage PMOS transistor.
According to another aspect of the embodiments of the present application, there is provided a switching power supply including the level shift circuit described above.
Compared with the related art, the technical scheme provided by the embodiment of the application has the following advantages:
the present application provides a level conversion circuit comprising: the first level conversion module is used for converting a first level signal into a second level signal of a second voltage domain under the condition of receiving the first level signal of the first voltage domain, wherein the power supply voltage of the first voltage domain is different from that of the second voltage domain, and the potential of the second level signal is opposite to that of the first level signal; and the second level conversion module is coupled with the first level conversion module and is used for converting the second level signal into a third level signal of a second voltage domain, wherein the third level signal has the same potential as the first level signal. This application need not with the help of latch circuit, only need two simple level conversion modules can realize the level transition function, utilize the level signal in the second voltage domain that self circuit characteristic is opposite with this first level signal potential according to the first level signal output in first voltage domain through first level conversion module promptly, convert second level signal into the third level signal the same with first level signal potential in the second voltage domain by second level conversion module again, thereby realize the level transition function through simple circuit structure, the technical problem that need combine latch circuit just can realize level transition has been solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without any creative effort.
FIG. 1 is a schematic diagram of a level shifting circuit provided in the prior art;
FIG. 2 is a schematic conversion diagram of an alternative level shift circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of an alternative level shifting circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a current mirror;
FIG. 5 is a schematic diagram of an inverter;
fig. 6 is a schematic diagram of an alternative switching power supply circuit according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for the convenience of description of the present application, and have no specific meaning in themselves. Thus, "module" and "component" may be used in a mixture.
In the related art, as shown in fig. 1, there is a level shift circuit, but the level shift circuit needs to rely on a latch function to implement level shift, and the level shift circuit needs 11 MOS transistors, including 6 low-voltage transistors and 5 high-voltage transistors, and the area of the high-voltage transistor is about 9 times larger than that of the low-voltage transistor due to the manufacturing process of the high-voltage transistor, which results in a complex structure and high cost of the level shift circuit.
To solve the problems mentioned in the background, according to an aspect of the embodiments of the present application, there is provided an embodiment of a level shift circuit, as shown in fig. 2, the level shift circuit including:
the first level conversion module 201 is configured to, when receiving a first level signal of a first voltage domain, convert the first level signal into a second level signal of a second voltage domain, where the first voltage domain and the second voltage domain have different power voltages, and the second level signal has an opposite potential to the first level signal.
In the embodiment of the present application, the power voltages of the first voltage domain and the second voltage domain are different, for example, the power voltage of the first voltage domain is 5V, and the power voltage of the second voltage domain is 10V. If the high level of the first voltage domain is 4V, signals outputting 4V or more are all represented by 1, the low level is 1V, signals outputting 1V or less are all represented by 0, and the high level of the second voltage domain is 9V, signals outputting more than or equal to 9V are all represented by 1, the low level is 5V, signals outputting less than or equal to 5V are all represented by 0, when the first level signal outputted from the first voltage domain is at a high level 1 (e.g. 4V), the high level of the first voltage domain is converted into a low level 0 (i.e. the second level signal, e.g. 5V) of the second voltage domain through the first level conversion module, or when the first level signal output by the first voltage domain is at a low level 0 (e.g., 1V), the low level of the first voltage domain is converted into a high level 1 (e.g., 9V) of the second voltage domain by the first level conversion module.
In the embodiment of the present application, the first level shift module does not directly shift the input signal of the first voltage domain, but connects the high level signal and the low level signal corresponding to the second voltage domain, and determines which signal the first level shift module outputs from the first voltage domain according to the first level signal from the first voltage domain, and based on the circuit characteristics of the first level shift module, when the first level signal is the high level signal of the first voltage domain, the first level shift module outputs the low level signal of the second voltage domain, that is, 1 to 0; when the first level signal is a low level signal of the first voltage domain, the first level conversion module outputs a high level signal of the second voltage domain, i.e. 0 to 1.
The second level shifting module 203 is coupled to the first level shifting module, and configured to shift the second level signal to a third level signal of the second voltage domain, where the third level signal has the same potential as the first level signal.
In the embodiment of the application, since the first level shift module shifts a high level signal of the first voltage domain to a low level signal of the second voltage domain, or shifts a low level signal of the first voltage domain to a high level signal of the second voltage domain, in order to realize level shift between different voltage domains, that is, in order to achieve consistent signal transmission between modules of different voltage domains, if a signal to be transmitted is high level, the signal to be transmitted is high level in different voltage domains, it is necessary to invert the signal output by the first level shift module, that is, the second level shift module shifts the second level signal output by the first level shift module to a third level signal of the second voltage domain, so that the potential of the third level signal is the same as the potential of the first level signal, and if the second level signal is a low level signal of the second voltage domain, the third level signal is a high level signal of the second voltage domain, the same potential as the first level signal (high level signal of the first voltage domain) finally realizes the level conversion from 1 to 0 to 1; when the second level signal is a high level signal in the second voltage domain, the third level signal is a low level signal in the second voltage domain, and the third level signal has the same potential as the first level signal (i.e., the low level signal in the first voltage domain), and finally, level conversion from 0 to 1 to 0 is realized.
This application need not with the help of latch circuit, only need two simple level conversion modules can realize the level transition function, utilize the level signal in the second voltage domain that self circuit characteristic is opposite with this first level signal potential according to the first level signal output in first voltage domain through first level conversion module promptly, convert second level signal into the third level signal the same with first level signal potential in the second voltage domain by second level conversion module again, thereby realize the level transition function through simple circuit structure, the technical problem that need combine latch circuit just can realize level transition has been solved.
Optionally, the first level shift module includes:
the input end of the current mirror is coupled with the first power supply;
a first transistor N1, a gate of which is coupled to the signal output terminal of the first voltage domain, a source of which is grounded, and a drain of which is coupled to the ground terminal of the current mirror;
and a first port of the clamper is coupled with a second power supply, a second port of the clamper is coupled with the first power supply, and a third port of the clamper is coupled with the output end of the current mirror.
In the embodiment of the present application, as shown in fig. 3, the first transistor is N1, the current mirror is composed of transistors N2 and N3, and the clamp is composed of a transistor N4 and a resistor R2. The gate of the first transistor N1 is coupled to the signal output terminal IN of the first voltage domain, the source of the first transistor N1 is connected to ground GND for providing a low level signal of the second voltage domain, and the drain of the first transistor N1 is coupled to the sources of the transistors N2 and N3 IN the current mirror, forming a connection node J1. The input terminal of the current mirror is the drain of transistor N3, and the drain of N3 is connected to the first power source LVCC. The first port of the clamp is one end of a resistor R2, one end of a resistor R2 is connected to the second power supply HVCC, the second port of the clamp is the gate of a transistor N4, the gate of the transistor N4 is connected to the first power supply LVCC, the third port of the clamp is the source of a transistor N4, the output of the current mirror is the drain of a transistor N2, and the third port of the clamp is coupled to the output of the current mirror, i.e., the source of a transistor N4 is coupled to the drain of a transistor N2.
Optionally, a power supply voltage of the first power supply is smaller than a power supply voltage of the second power supply, the first power supply is used for driving the transistor in the clamp to be turned on, the power supply voltage of the second power supply is the same as a power supply voltage of a second voltage domain, and the second power supply is used for generating a high potential of the second voltage domain.
In the embodiment of the present application, since the gate of the transistor N4 in the clamp is always connected to the first power source LVCC, the transistor N4 is always in the on state. The second power source HVCC is used to generate a high level signal of the second voltage domain.
Alternatively, as shown in fig. 3, the current mirror includes:
a second transistor N2, wherein the drain of the second transistor N2 is the output terminal of the current mirror, and the source of the second transistor N2 is coupled to the drain of the first transistor N;
the drains of the third transistor N3 and the third transistor N3 are input terminals of a current mirror, the gate of the third transistor N3 is coupled to the gate of the second transistor N2, the source of the third transistor N3 is coupled to the drain of the first transistor N1, and the drain of the third transistor N3 is connected to the gate of the third transistor N3.
In the embodiment of the present application, the principle of the current mirror is as shown in fig. 4, the second transistor N2 and the third transistor N3 operate in a saturation region, the third transistor N3 is a source of the current mirror, the second transistor N2 is a current mirroring the N3, the current of the third transistor N3 is fixed and known, and the current is Iref. According to the current formula of the saturation region, the method comprises the following steps:
Iref＝K*N*(W/L)N3*(VGS1-VTH1)2formula (1)
Wherein the content of the first and second substances,k is a constant, (W/L)N3Is the width-to-length ratio, V, of the third transistor N3GS1Is the gate-source voltage, V, of the third transistor N3TH1Is the threshold voltage of the third transistor N3. N is the number of parallel tubes.
Similarly, the drain current of the second transistor N2 can be obtained as shown in equation (2)
IOUT＝K*M*(W/L)N2*(VGS2-VTH2)2Formula (2)
Wherein K is a constant, (W/L)N2Is the width-to-length ratio, V, of the second transistor N2GS2Is the gate-source voltage, V, of the second transistor N2TH2Is the threshold voltage of the second transistor N2, and M is the number of N2 parallel connected transistors. The gate terminals of the third transistor N3 and the second transistor N2 are connected together, so the gate-source voltages of the two MOS transistors are equal, and the threshold voltages are also equal. When the current mirror is designed, the width-length ratio of the current mirror is set to be the same, and only the number of the parallel tubes is different. Formula (3) can be obtained by dividing formula (1) by formula (2)
IOUT＝(M/N)*IrefFormula (3)
From equation (3), it can be seen that the current mirror is equivalent to IrefIs replicated by (M/N) times.
Optionally, as shown in fig. 3, a first resistor R1 is further connected in series between the drain of the third transistor N3 and the first power source LVCC, and the first resistor R1 is used for generating the driving current of the current mirror.
Alternatively, as shown in fig. 3, the clamper includes:
one end of the second resistor R2 is a first port of the clamper;
a fourth transistor N4, a drain of the fourth transistor N4 is coupled to the other end of the second resistor, a gate of the fourth transistor N4 is the second port of the clamp, and a source of the fourth transistor N4 is the third port of the clamp.
Optionally, the second level shift module includes:
and the first side port of the inverter is coupled with the second power supply, the second side port of the inverter is coupled with a reference voltage port, the reference voltage port is used for generating a low potential of the second voltage domain, the input end of the inverter is respectively coupled with the drain electrode of the second transistor and the source electrode of the fourth transistor, and the output end of the inverter is coupled with the input end of the second voltage domain.
Optionally, the inverter comprises:
a fifth transistor P5, a source of the fifth transistor P5 is a first side port of the inverter, a gate of the fifth transistor P5 is an input terminal of the inverter, and a drain of the fifth transistor P5 is an output terminal of the inverter;
a gate of the sixth transistor N6, a gate of the sixth transistor N6 is coupled to the gate of the fifth transistor P5, a drain of the sixth transistor N6 is coupled to the drain of the fifth transistor P5, and a source of the sixth transistor N6 is a second side port of the inverter.
In the embodiment of the present application, the source of the fifth transistor P5 is coupled to the second power source HVCC for pulling the output terminal of the inverter to the HVCC potential, i.e. the high level of the second voltage domain, when the fifth transistor P5 is turned on. The source of the sixth transistor N6 is coupled to the reference voltage port SW, and the reference voltage port SW is used for generating a low level of the second voltage domain, and is used for pulling the potential of the output terminal of the inverter down to the SW potential, i.e. the low level of the second voltage domain, when the sixth transistor N6 is turned on. A gate of the fifth transistor P5 and a gate of the sixth transistor N6, which are used as input terminals of the inverter, are respectively coupled to a drain of the second transistor N2 and a source of the fourth transistor N4 to form a connection node J2, and a drain of the fifth transistor P5 and a drain of the sixth transistor N6 are both output terminals of the inverter, and are configured to output corresponding signals when the respective transistors are turned on.
The principle of the inverter is shown in fig. 5, the width-to-length ratio of PMOS and NMOS is first adjusted by design so that the flip voltage is at (VCC-GND)/2, i.e. VOUT equals to GND when the input voltage VIN is greater than (VCC-GND)/2, and VOUT equals to VCC when VIN is less than (VCC-GND)/2. Specifically, when VIN is less than (VCC-GND)/2, the PMOS transistor is in the on state and the NMOS transistor is in the off state, so VOUT is pulled to VCC potential. When VIN is larger than (VCC-GND)/2, the PMOS transistor is in the off state, and the NMOS transistor is in the on state, so VOUT is pulled to the GND potential.
Optionally, the clamp makes the voltage at the J2 node not exceed the LVCC potential, and is used to protect the inverter formed by the fifth transistor P5 and the sixth transistor N6, and prevent the gate breakdown of the fifth transistor P5 and the sixth transistor N6 caused by the too high voltage.
Optionally, the first transistor N1, the second transistor N2, the third transistor N3, and the sixth transistor N6 are low voltage NMOS transistors, the fourth transistor N4 is a high voltage NMOS transistor, and the fifth transistor P5 is a low voltage PMOS transistor.
In the embodiment of the present application, only 6 transistors and 2 resistors are needed to implement the level shift circuit, and only 5 low-voltage transistors and 1 high-voltage transistor are needed from the application type, whereas 11 transistors are needed in the prior art shown in fig. 1, where 6 low-voltage transistors and 5 high-voltage transistors are needed. The high-voltage MOS tube has an area of 8008um due to different manufacturing processes of the high-voltage tube and the low-voltage tube2The area of the low-voltage MOS tube is 880um2And the area of the high-voltage MOS tube is about 9 times of that of the low-voltage MOS tube, so that the technical scheme of the application can realize the level conversion circuit based on a simpler structure and lower cost, and the technical problem that the level conversion can be realized only by combining the latch circuit is solved without the help of the latch circuit.
The following describes the operation flow of the level shift circuit provided in the present application:
when the gate of the first transistor N1 receives the low level of the first voltage domain, the first transistor N1 is turned off, the current mirror formed by the second transistor N2 and the third transistor N3 is turned off, the fourth transistor N4 is driven by the first power supply to be turned on, the source potential of the fourth transistor N4 is pulled up to the high level of the second voltage domain by the second resistor R2, the fifth transistor P5 is turned off, the sixth transistor N6 is turned on, and the drain potential of the sixth transistor N6 is pulled down to the low level of the second voltage domain, so as to output the low level of the second voltage domain;
when the gate of the first transistor N1 receives the high level of the first voltage domain, the first transistor N1 is turned on, the current mirror formed by the second transistor N2 and the third transistor N3 is turned on, the drain of the second transistor N2 is pulled down to the low level of the second voltage domain, the fifth transistor P5 is turned on, the sixth transistor N6 is turned off, the drain of the fifth transistor P5 is pulled up to the high level of the second voltage domain, and the high level of the second voltage domain is output.
According to another aspect of the embodiments of the present application, there is provided a switching power supply including the level shift circuit described above.
In the embodiment of the present application, as shown in fig. 6, the switching power supply stabilizes the input voltage VIN to VOUT, the switching power supply in this patent is a BUCK topology, and the output rated voltage is VREF (R1+ R2)/R2. When VIN starts to be electrified, the output voltage is initially 0, and then the feedback voltage V of the feedback resistors R1 and R2FBAlso 0, error amplifier A1 will be VFBThe error with VREF is amplified, the high Level of the comparison output of the fixed frequency triangular wave is transmitted through an RS latch and a Level shifter, so that a tube N1 is opened, a tube N2 is closed, a capacitor C1 is charged through N1 and L1, VOUT begins to rise, and when the VOUT is greater than VREF (R1+ R2)/R2, a feedback voltage VFBWill be greater than VREF, the error amplifier will be VFBThe error with VREF is amplified, the high and low levels of the comparison output of the fixed-frequency triangular wave are transmitted through an RS latch and a Level shfter, so that the tube N1 is closed, the tube N2 is opened, the capacitor C1 is discharged through N2 and L1, switching is repeated, and finally the output is stabilized at VREF (R1+ R2)/R2.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A level shift circuit, comprising:
the device comprises a first level conversion module, a second level conversion module and a control module, wherein the first level conversion module is used for converting a first level signal of a first voltage domain into a second level signal of a second voltage domain under the condition of receiving the first level signal, the first voltage domain and the second voltage domain have different power supply voltages, and the second level signal is opposite to the first level signal in potential;
and the second level conversion module is coupled with the first level conversion module and is used for converting the second level signal into a third level signal of the second voltage domain, wherein the third level signal has the same potential as the first level signal.
2. The level shift circuit of claim 1, wherein the first level shift module comprises:
the input end of the current mirror is coupled with a first power supply;
a first transistor, a gate of which is coupled to the signal output terminal of the first voltage domain, a source of which is grounded, and a drain of which is coupled to a ground terminal of the current mirror;
a clamp, a first port of the clamp coupled to a second power supply, a second port of the clamp coupled to the first power supply, and a third port of the clamp coupled to an output of the current mirror.
3. The circuit of claim 2, wherein a supply voltage of the first power supply is less than a supply voltage of the second power supply, the first power supply is configured to drive the transistor of the clamp to conduct, the supply voltage of the second power supply is the same as a supply voltage of the second voltage domain, and the second power supply is configured to generate a high level of the second voltage domain.
4. The level shift circuit of claim 3, wherein the current mirror comprises:
a second transistor, a drain of the second transistor being the output of the current mirror, a source of the second transistor being coupled to a drain of the first transistor;
a third transistor, a drain of the third transistor being the input terminal of the current mirror, a gate of the third transistor being coupled to a gate of the second transistor, a source of the third transistor being coupled to a drain of the first transistor, a drain of the third transistor being connected to a gate of the third transistor.
5. The level shift circuit according to claim 4, wherein a first resistor is further connected in series between the drain of the third transistor and the first power supply, and the first resistor is used for generating a driving current of the current mirror.
6. The level shift circuit of claim 4, wherein the clamp comprises:
a second resistor, one end of the second resistor being the first port of the clamper;
a fourth transistor, a drain of the fourth transistor being coupled to the other end of the second resistor, a gate of the fourth transistor being the second port of the clamp, and a source of the fourth transistor being the third port of the clamp.
7. The level shift circuit of claim 6, wherein the second level shift module comprises:
a first side port of the inverter is coupled to the second power source, a second side port of the inverter is coupled to a reference voltage port, the reference voltage port is configured to generate a low potential of the second voltage domain, an input terminal of the inverter is coupled to a drain of the second transistor and a source of the fourth transistor, respectively, and an output terminal of the inverter is coupled to an input terminal of the second voltage domain.
8. The level shift circuit of claim 7, wherein the inverter comprises:
a fifth transistor, a source of the fifth transistor being the first side port of the inverter, a gate of the fifth transistor being the input end of the inverter, a drain of the fifth transistor being the output end of the inverter;
a sixth transistor, a gate of the sixth transistor coupled to a gate of the fifth transistor, a drain of the sixth transistor coupled to a drain of the fifth transistor, and a source of the sixth transistor being the second side port of the inverter.
9. The circuit of claim 8, wherein the first transistor, the second transistor, the third transistor, and the sixth transistor are low voltage NMOS transistors, the fourth transistor is a high voltage NMOS transistor, and the fifth transistor is a low voltage PMOS transistor.
10. A switching power supply comprising the level shift circuit according to any one of claims 1 to 9.
CN202111320094.7A 2021-11-09 2021-11-09 Level conversion circuit and switching power supply Pending CN114095013A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116054810B (en) * 2022-07-11 2023-11-14 荣耀终端有限公司 Level conversion circuit and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116054810B (en) * 2022-07-11 2023-11-14 荣耀终端有限公司 Level conversion circuit and electronic device

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