CN115981404B - Step-down voltage stabilizing circuit, voltage stabilizer, power manager and embedded system - Google Patents

Step-down voltage stabilizing circuit, voltage stabilizer, power manager and embedded system Download PDF

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CN115981404B
CN115981404B CN202310180640.4A CN202310180640A CN115981404B CN 115981404 B CN115981404 B CN 115981404B CN 202310180640 A CN202310180640 A CN 202310180640A CN 115981404 B CN115981404 B CN 115981404B
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parallel
serial
voltage
signal
capacitor
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CN115981404A (en
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郭亚东
罗锋
肖知明
孟逸飞
赵越
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Shenzhen Research Institute Of Nankai University
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Shenzhen Research Institute Of Nankai University
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The application provides a voltage-reducing voltage-stabilizing circuit, a voltage stabilizer, a power manager and an embedded system, which are applied to the technical fields of power supplies and integrated circuits, wherein the voltage-stabilizing circuit comprises a serial-parallel structure selection unit, a serial control unit, a parallel control unit, a switch driving unit and a capacitor serial-parallel execution unit, wherein the serial-parallel structure selection unit generates a selection signal, the serial control unit generates a serial signal, the parallel control unit generates a parallel signal, the switch driving unit generates an execution signal for controlling the capacitor to perform serial-parallel conversion by combining the serial signal and the parallel signal, and the capacitor serial-parallel execution unit triggers the capacitor to perform serial-parallel conversion according to the execution signal. The voltage reduction and stabilization is realized by adopting the capacitor serial-parallel conversion, so that the voltage reduction and stabilization device not only can adapt to a wide input voltage range, but also does not need an external energy storage inductor, an MOS tube and the like, has the advantages of small volume, low power consumption, high conversion efficiency and the like, and can provide good secondary power supply voltage for an embedded system.

Description

Step-down voltage stabilizing circuit, voltage stabilizer, power manager and embedded system
Technical Field
The application relates to the technical field of power supplies and integrated circuits, in particular to a voltage-reducing and stabilizing circuit, a voltage stabilizer, a power supply manager and an embedded system.
Background
In embedded systems, the most commonly used secondary power supply circuits are low dropout linear regulators (LDOs) and BUCK switching regulators (BUCK).
However, in the secondary power circuit LDO, when the input/output voltage difference is large, the voltage regulator consumes more power (i.e., the conversion to thermal effect is lost, resulting in huge heat generation, low efficiency, etc., and a large heat sink is required to be additionally added.
In the secondary power circuit BUCK, an external inductor, a large volume and even an external MOS tube are needed. Moreover, both input and output currents of the BUCK circuit pulsate, which causes electromagnetic interference to the input power supply and the emitter of the switching transistor in the BUCK circuit is not grounded, thus complicating the driving circuit.
Based on this, a new step-down circuit is required as a secondary power supply circuit.
Disclosure of Invention
In view of this, in order to overcome the defects of the conventional voltage reduction circuit, the application provides a novel voltage reduction structure with wide input voltage range and high efficiency, in which the series-parallel series number of the capacitive voltage division is determined by the input voltage, and the manner of using off-chip inductance in the conventional voltage reduction circuit is avoided.
The embodiment of the specification provides the following technical scheme:
the embodiment of the present specification provides a voltage-reducing and stabilizing circuit, including: the device comprises a serial-parallel structure selection unit, a serial control unit, a parallel control unit, a switch driving unit and a capacitor serial-parallel execution unit;
The serial-parallel structure selection unit is used for generating a serial-parallel selection signal corresponding to the series of the capacitor serial-parallel connection stage aiming at the input voltage under the triggering of the first level state of the first clock signal, and outputting the serial-parallel selection signal to the next-stage serial control unit;
The series control unit is used for generating a series signal for controlling the capacitors to be connected in series according to the input series-parallel selection signal, and outputting the series signal to the next-stage switch driving unit so as to convert the capacitors into a series structure in the capacitor series-parallel execution unit to realize capacitor voltage division type voltage reduction;
The parallel control unit is used for generating a parallel signal for controlling the capacitor to be connected in parallel under the triggering of the second level state of the first clock, and outputting the parallel signal to the next-stage switch driving unit so as to convert the capacitor into a parallel structure in the capacitor serial-parallel execution unit to realize voltage reduction and then provide output driving current;
The switch driving unit is used for generating serial-parallel execution signals corresponding to the polar plates at the two ends of the capacitor in the capacitor serial-parallel execution unit by the serial signal output by the serial control unit and the parallel signal output by the parallel control unit;
and the capacitor serial-parallel execution unit is used for realizing serial-parallel conversion of the capacitor between the serial structure and the parallel structure according to the serial-parallel execution signal so as to output corresponding voltage-reducing and voltage-stabilizing voltage.
Preferably, the serial-parallel structure selection unit includes a plurality of resistors and a plurality of comparators, wherein the plurality of resistors are used for dividing the input voltage into a plurality of different divided voltages, the plurality of different divided voltages are correspondingly input to the positive input ends of the corresponding comparators, and the negative input ends of the comparators are connected with the reference voltage.
Preferably, the serial-parallel structure selection unit further comprises a plurality of AND gates, a plurality of first current mirrors and a plurality of MOS tubes; the MOS transistor comprises an AND gate, a first current mirror and an MOS transistor, wherein the AND gate, the first current mirror and the MOS transistor are used for jointly generating a current control signal, one input end of the AND gate is connected with an output level signal of a corresponding comparator, the other input end of the AND gate is connected with a reference level, the output end of the AND gate is used for driving a grid electrode of the MOS transistor, a source electrode of the MOS transistor generates bias current through a resistor, and the bias circuit forms the current control signal after passing through the corresponding current mirror to serve as the serial-parallel connection selection signal.
Preferably, the series control unit comprises a plurality of second current mirrors, a plurality of first inverters and a series current branch; the series current branch is located between the output end of the second current mirror and the input end of the corresponding first inverter, the current of the current source in the series current branch flows through the connection point between the output end of the second current mirror and the input end of the corresponding first inverter, the second current mirror is used for being connected with the corresponding current control signal, so that after passing through the series resistor and the MOS tube on the series current branch, a corresponding first point potential is formed at the input end of the corresponding first inverter, and the corresponding series signal is formed after the first point potential passes through the first inverter.
Preferably, the parallel control unit comprises a plurality of first NMOS tubes, a plurality of second NMOS tubes, a plurality of pairs of tubes and a plurality of second inverters; the grid electrode of the first NMOS tube is connected with the second clock signal CLK_A, the source electrode of the first NMOS tube is connected with the lower polar plate of the corresponding capacitor, the drain electrode of the second NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the input end of the second inverter through a resistor and then is connected with the upper polar plate of the corresponding capacitor, the pair of the NMOS tubes are NMOS pair tubes, the grid electrodes of the pair of the NMOS pair tubes are respectively input with the corresponding clock signal pair triggered by the second clock signal CLK_A, the drain electrodes of the pair of the NMOS pair tubes are respectively connected with the upper polar plate voltage and the lower polar plate voltage, the source electrode of the pair of the NMOS pair tubes are connected with each other and then used for driving the grid electrodes of the second NMOS tube, so that the input end of the second inverter forms the corresponding parallel potential, and the second inverter reversely outputs the corresponding parallel signal.
Preferably, the switch driving unit includes a plurality of SR flip-flops, wherein an R input terminal of the SR flip-flop is used for accessing a corresponding parallel signal, an S input terminal is used for accessing a corresponding serial signal, and the corresponding serial-parallel execution signal is output according to the input parallel signal and serial signal.
Preferably, the capacitor serial-parallel execution unit comprises a plurality of stages of capacitor serial-parallel units; each stage of capacitor serial-parallel unit comprises a capacitor, a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube;
the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and connected with the serial-parallel execution signal corresponding to the serial signal;
The source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and the upper polar plate of the capacitor, and the connecting point is used as a connecting point for carrying out series-parallel connection with the serial-parallel connection unit of the capacitor at the upper stage;
The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and then is used as a connection point for carrying out series-parallel connection with the next-stage capacitor series-parallel unit;
the grid of the first NMOS tube is connected with the serial-parallel execution signal corresponding to the connected parallel signal;
The source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and the lower polar plate of the capacitor;
the drain electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded.
The embodiment of the specification also provides a buck regulator, which comprises a buck regulator unit, wherein the buck regulator unit comprises at least two buck regulator circuits which are cascaded in series, the output voltage of the previous stage buck regulator circuit is the input voltage of the next stage buck regulator circuit, and the buck regulator circuit is the buck regulator circuit according to any embodiment of the specification.
The embodiment of the specification also provides a power manager, which comprises a voltage stabilizing unit, wherein the voltage stabilizing unit comprises the voltage reducing and stabilizing circuit according to any embodiment of the specification, or the voltage stabilizing unit comprises the voltage reducing and stabilizing device according to any embodiment of the specification.
The embodiments of the present disclosure also provide an embedded system, including a secondary power module, where the secondary power module includes a buck regulator circuit according to any one of the embodiments of the present disclosure, or where the secondary power module includes a buck regulator according to any one of the embodiments of the present disclosure, or where the secondary power module includes a power manager according to any one of the embodiments of the present disclosure.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:
the voltage reduction function is realized through the serial-parallel connection of the capacitors, and no additional inductance is needed, so that the heat generation quantity is smaller, the occupied area is also greatly reduced, an extremely wide input voltage range can be realized, and the application range is extremely wide; the energy recovery effect is adopted in the middle, so that the conversion efficiency of the power converter is greatly improved, the output load in a certain range can be adjusted, and the power converter can be suitable for environments with different loads.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a circuit structure for realizing voltage reduction and stabilization based on capacitor serial-parallel conversion in the application;
FIG. 2 is a schematic diagram of a serial-parallel structure selection unit according to the present application;
FIG. 3 is a schematic diagram of a serial control unit according to the present application;
FIG. 4 is a schematic diagram of a parallel control unit according to the present application;
FIG. 5 is a schematic diagram of a switch driving unit and a capacitor serial-parallel execution unit in the present application;
FIG. 6 is a schematic diagram of the structure of the energy recovery in the capacitor serial-parallel conversion according to the present application;
FIG. 7 is a schematic diagram of a series connection of multi-stage buck regulator circuits according to the present application;
Fig. 8 is a schematic diagram of a series connection of multi-stage buck voltage regulator circuits according to the present application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.
The existing low dropout regulator (LDO) is not suitable for wide input voltage occasions because the voltage difference between the input voltage and the output voltage becomes the power consumption of the regulator, and is often only suitable for occasions with small voltage difference. The BUCK switching regulator (BUCK), although applicable to wide input voltage, is limited by its structure, and has poor electromagnetic performance, and requires additional energy storage inductance, even an external MOS transistor, and a complex driving circuit.
In view of this, after intensive research and improvement exploration on the voltage stabilizing circuit and the voltage reducing and stabilizing mode, the embodiment of the present specification proposes a voltage reducing and stabilizing processing scheme: as shown in FIG. 1, the series-parallel series number of the capacitor voltage division is determined, so that a novel voltage reduction circuit with wide input voltage range and high power conversion efficiency is realized by controlling the series-parallel connection of the capacitor, and the voltage reduction output voltage is not generated by adopting an off-chip inductance mode in a traditional mode. Wherein, this novel step-down circuit's functional module includes: the device comprises a serial-parallel structure selection unit, a serial control unit, a parallel control unit, a switch driving unit and a capacitor serial-parallel execution unit.
The serial-parallel structure selection unit is used for generating serial-parallel selection signals SPi (such as SP1 to SPm shown in fig. 1) related to series-parallel series of the capacitor aiming at different input voltages, and outputting the signals to the next-stage serial control unit and the parallel control unit;
The series control unit is used for generating a series signal DSi (shown as DS1 to DSm schematically in figure 1) for controlling the capacitors to be connected in series according to the input series-parallel selection signals, and outputting the series signal to the next-stage switch driving unit so as to realize the function of capacitive voltage division type voltage reduction when the capacitors are connected in series in the capacitive series-parallel execution unit;
The parallel control unit is used for generating parallel signals DRi (shown as DR1 to DRm shown in fig. 1) for controlling the parallel connection of the capacitors and outputting the parallel signals to the next-stage switch driving unit so as to realize the effect of providing output driving current after voltage reduction when the capacitors are connected in parallel in the capacitor series-parallel execution unit;
The switch driving unit is configured to generate, according to the input serial signal and parallel signal corresponding to each capacitor, an execution signal for controlling the two end plates of the capacitor to be connected to different positions (as shown by OUT1 to OUTq illustrated in fig. 1, it should be noted that the subscript q may be equal to or unequal to the subscript M described above, which is not limited herein), so that the capacitor in the capacitor serial-parallel execution unit completes the serial-parallel conversion action under the precise switch delay control of the execution signal, so that the output voltage is a corresponding voltage value after the input voltage is reduced, for example, in the step-down voltage stabilization in which M capacitors perform serial-parallel conversion, and the output voltage vo=vin/M.
The number of series-parallel capacitors, the number of control signals and the number of control signals generated by each circuit unit, and the like may be determined according to practical application requirements, and are not particularly limited herein.
The voltage reduction and stabilization is realized through the serial-parallel conversion based on the capacitor, so that the circuit can be suitable for a large-range input voltage application occasion, an external energy storage inductor, an MOS tube and the like are not required to be used in the traditional scheme, the electromagnetic interference to the input voltage is small, and the application requirements of various embedded systems to the secondary voltage can be met.
In addition, in the novel step-down voltage stabilizing circuit, the input voltage is directly used for deciding the series-parallel connection series number of the capacitors, so that a plurality of digital signals for controlling the capacitors to finish serial-parallel conversion can be generated by using the serial-parallel structure selection unit according to the input voltage, the step-down energy conversion is realized by depending on the capacitors, and the step-down voltage stabilizing is performed without using an external energy storage inductor or even a power MOS tube in the traditional scheme. Therefore, in addition to the application occasion adapting to the extremely wide input voltage range, even under the condition that a large voltage difference exists between the output voltage and the input voltage, the heat generated by the whole circuit is very little, a large-area radiator is not needed, and the occupied area of the circuit can be greatly reduced. And the output load in a certain range can be flexibly realized by adjusting the serial-parallel connection of the capacitors and serially connecting a plurality of modules, and the device can adapt to the environments of different loads.
In some embodiments, the serial-parallel structure selection unit may use a resistor and a comparator, obtain different divided voltages through resistor division, and then use the divided voltages for comparison by the comparator to output, so as to form a serial-parallel control signal according to the input voltage.
As shown in fig. 2, the serial-parallel structure selection unit includes a series of resistors for dividing the input voltage to obtain corresponding divided voltages (ref_1d1, ref_1dm as shown in fig. 2), the divided voltages are input to the positive input ends of the comparators respectively, and the other ends of the comparators are connected with the bandgap reference voltage VREF, so that the comparators output corresponding digital signals (on_2, on_m, etc. as shown in fig. 2) as serial-parallel signals respectively.
In some embodiments, the corresponding digital circuit may be used to shape and drive the comparator output to form a new signal, so that the new signal is easier to connect with the subsequent circuit, and is more suitable for signal transmission, driving control, and the like.
As shown in fig. 2, the comparator output signals (on_2 and on_m as shown in fig. 2) are connected to one input terminal of the corresponding and gate, the other input terminal of the and gate is connected to the output voltage reference level VREG, the output of the and gate is connected to the gate of the NMOS transistor, the source output of the NMOS transistor generates a corresponding bias current via a resistor, and the bias current forms a current control signal as a serial-parallel signal for the next stage circuit as an input after passing through the current mirror.
It should be noted that, the high and low levels of CLK correspond to VREG and 0V, so that accurate output control of the serial-parallel signal is achieved by the high level of CLK in combination with and gate.
As shown in fig. 2, the output of the first AND gate and_1 is connected to the gate of the first NMOS transistor m_1, AND the source output of the first NMOS transistor m_1 generates the first bias current Ibias1 through a resistor, AND the first bias current Ibias1 forms the current control signal I1 as the input of the next stage circuit (i.e., the series control unit) after passing through the first current mirror (i.e., the current mirror_1).
In some embodiments, when the control signal output by the serial-parallel structure selection unit is a current control signal, the serial control unit may generate a corresponding serial control signal according to the current control signal by using circuits such as a corresponding current mirror and an inverter.
The serial-parallel connection of the whole circuit can be controlled by a clock signal CLK with a duty ratio of 1/2, when CLK is high level, the circuit is in a serial state, and the high level CLK signal triggers a current source in a serial control unit to generate current, so that the circuit is serially connected from top to bottom. When the CLK signal is in a low level, the circuit is in a parallel state, the low level CLK signal triggers the parallel control unit to generate a clock signal CLK_A and a clock signal pair CTL_S1 and CTL_S1B triggered by the CLK_A, so that the circuit is connected in parallel step by step from bottom to top.
As shown in fig. 3, taking two-capacitor series control as an example, the series control unit may include a third current mirror (i.e. current mirror_3), a fourth current mirror (i.e. current mirror_4), and the input current signals of the current mirrors are the current control signals (i.e. I1 and I2) of the foregoing examples, respectively, and the respective outputs of the current mirrors are connected to the inputs of the corresponding first inverter (i.e. inverter_1) and second inverter (i.e. inverter_2) (ds_1 and ds_2 as illustrated in fig. 3).
The main branch of the series control unit is provided with a current source IBIAS, the current flows through ds_1 and a first resistor R1 to the source of the first PMOS tube pm_s1, and then the current flows through ds_2 and a second resistor R2 from the drain of the pm_s1 to the source of the second PMOS tube pm_s2. The voltages at the points DS_1 and DS_2 are respectively outputted by the first inverter and the second inverter to form serial signals DS1 and DS2.
In one example, the inverter may be composed of a plurality of MOS transistors. As shown in fig. 3, in the first inverter, the first upper plate level signal TOM corresponding to the first capacitor converts the voltage at ds_1 of the input inverter into the output DS1 of the inverter after passing through the resistor and the PMOS transistor, and the first lower plate level signal BOM converts the voltage at ds_1 of the input inverter into the output DS1 of the inverter after passing through the NMOS transistor. In other words, DS1 depends on BOM when DS_1 is at a high potential, and DS1 depends on TOM when DS_1 is at a low potential.
Further, in the circuit processing for determining DS1 for BOM, two NMOS transistors may be employed, wherein BOM is connected to the gate and source of the first NMOS transistor, the gate of the second NMOS transistor is connected to DS_1, the drain of the second NMOS transistor is connected to DS1, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor.
It should be noted that the second inverter may take the same circuit form as the first inverter, and in particular, see the schematic of fig. 3, which is not further developed herein.
After the series control unit adopts the inverter to output the series signal, the series signal can be output to the switch driving unit, and the switch driving unit is used for further processing to form the execution signal required by the capacitor series-parallel execution unit.
In some embodiments, the parallel control unit may employ a resistor, a MOS transistor, or the like, to generate the parallel signal.
As shown in fig. 4, the parallel control unit may include a third resistor R3 and a fourth resistor R4, and the point voltages (dr_1 and dr_2 as shown in fig. 4) after passing through the resistors.
On the one hand, the point voltage outputs corresponding voltages (DR 1, DR2 as illustrated in fig. 4) as input signals of the next stage switch driving unit after passing through the corresponding inverters;
On the other hand, the point voltage is connected to the drain of the corresponding MOS transistor (nm_p1, nm_p3 as illustrated in fig. 4), the source of the MOS transistor is connected to the drain of the corresponding other MOS transistor (nm_p2, nm_p4 as illustrated in fig. 4), wherein the gate of the other MOS transistor (nm_p2, nm_p4 as illustrated in fig. 4) is connected to the clock signal clk_a, and the source of the other MOS transistor is connected to the lower plate voltage (BO 1, BO0 as illustrated in fig. 4) of the corresponding different capacitors. The gates of the pair of transistors NM_P5 and NM_P6 are respectively connected with a clock signal pair CTL_S1 and CTL_S1B triggered by CLK_A, the drains of the pair of transistors are correspondingly connected with an upper polar plate voltage TO1 and a lower polar plate voltage BO2, and the sources are commonly connected with the gate of NM_P1;
Similarly, the gates of the pair of transistors NM_P7, NM_P8 are connected TO the corresponding pair of clock signals CTL_ S, CTL _S2B, the drains of the pair of transistors are connected TO the other upper plate voltage TO0 and the other lower plate voltage BO1, and the sources are connected TO the gates of NM_P3.
In implementation, the high and low levels of the second clock signal (clk_a as illustrated in fig. 4) are VREG and 0V, respectively, and when clk_a is VREG and the corresponding BO is GND, the NMOS connected to clk_a is turned on, so that the trigger circuits are connected in parallel. In addition, the high and low levels of the reverse clock pair ctl_s correspond to the voltages of the upper and lower plates of the capacitor of the stage, after the parallel connection of the stage circuit is completed, the corresponding NMOS corresponding to the high clk_sb is turned on, that is, after the parallel connection is completed, the drain electrode of the NMOS is connected with the voltage of the lower plate of the capacitor, the source electrode output of the NMOS is at the low level, the NMOS controlled by the source electrode (such as nm_p1 and nm_p3 shown in fig. 4) is turned off, at this time, the branch circuit has no current, and the loss is reduced.
Therefore, the serial-parallel conversion of the circuit is controlled by the first clock signal CLK, the circuit reset state can be a capacitance parallel state, when CLK is high level, the serial branch circuit is triggered to realize the gradual serial connection of the circuits, when the CLK signal becomes low after the serial connection is completed and the Vin input energy is utilized to finish charging, the parallel branch circuit is triggered to realize the parallel output of the circuits, and the parallel signal only briefly triggers the SR flip-flop, so that the circuits realize the stable output after the voltage reduction.
Accurate parallel signal generation and output control are realized through the coordination control of the clock signal CLK_A and the clock signal pair CTR_S.
In some embodiments, the switch driving unit may generate corresponding serial-parallel execution signals by using an SR flip-flop (may also be referred to as an RS flip-flop, and not be distinguished here) based on the input serial signal and parallel signal, so that the serial-parallel execution signals can be mutually exclusive, and the correctness and reliability of the circuit operation are ensured.
As shown in fig. 5, the switch driving unit may include a digital logic part based on an SR flip-flop. The input terminals S1, R1 of the first flip-flop (SR flip-flop_1 as illustrated in fig. 5) are connected to the series control unit and the parallel control unit DS1, DR1, respectively, and the flip-flop switch driving output signals are OUT1, OUT2, respectively.
Similarly, the input terminals S2, R2 of a second SR flip-flop (e.g., SR flip-flop_2 shown in fig. 5) are connected to the series control unit and the parallel control units DS2, DR2, respectively, and the flip-flop switch driving output signals are correspondingly OUT3, OUT4.
In some embodiments, the capacitor serial-parallel execution unit may be a circuit unit in which a plurality of capacitors are serial-parallel converted under the control of an output signal of the switch driving unit, that is, the capacitor serial-parallel execution unit includes a plurality of capacitors and a switch circuit for connecting and converting the plurality of capacitors in series, parallel.
As shown in fig. 5, the capacitive serial-parallel execution unit includes a first capacitive serial-parallel unit and a second capacitive serial-parallel unit. The first capacitor serial-parallel unit comprises MOS tubes of PM1, PM2, NM1, NM2 and the like, and a first capacitor C1; the second capacitor serial-parallel unit comprises MOS transistors of PM3, PM4, NM3, NM4 and the like, and a second capacitor C2.
The connection relationship is schematically as follows: the gates of PM1 and NM1 are respectively connected with OUT1 and OUT2 output by the switch driving unit, the gate of PM1 is connected with the gate of PM2, the source of PM1 is connected with the source of PM2 and is connected with the upper polar plate of the first capacitor C1, the drain of PM1 is connected with the drain of NM1 and is connected with the upper polar plate of the second capacitor C2. The drain electrode of PM2 is connected with the grid electrode of NM2, and the source electrode of NM1 is connected with the drain electrode of NM2 and is connected with the lower polar plate of the first capacitor C1 together;
Similarly, the gates of PM3 and NM3 are respectively connected with OUT3 and OUT4 output by the switch driving unit, the gate of PM3 is connected with the gate of PM4, the source of PM3 is connected with the source of PM4 and is connected with the upper electrode plate of the second capacitor C2, the drain of PM3 is connected with the drain of NM3, the drain of PM4 is connected with the gate of NM4 pipe, and the source of NM3 is connected with the drain of NM4 and is connected with the lower electrode plate of the second capacitor C2;
The drains of PM1 and NM1 are connected to the sources of PM3 and PM4 to form a structure for performing serial-parallel conversion between two capacitor serial-parallel units.
Referring to fig. 2-5, and the above examples, the process of step-down by capacitor string-parallel is schematically illustrated as follows:
According to different input voltage ranges, the output voltage obtained by each stage is relatively different after resistor voltage division. The output signal obtained after resistor voltage division is compared with a reference voltage through a comparator to generate corresponding high-low level signals, the series of the series-parallel connection is controlled by the high-low level, and the capacitor which does not participate in the series-parallel conversion and the lowest-level capacitor are connected in parallel to participate in circuit work, so that the voltage-reducing and voltage-stabilizing output of the input voltage Vin is realized to obtain the output voltage Vo.
Referring to fig. 2-5, and the above example, the capacitive serial-parallel implementation is schematically illustrated as follows:
When the series-parallel connection is switched, the parallel connection is sequentially carried out from low level to high level, the voltage of the upper polar plate of the first capacitor C1 is kept unchanged in the switching process, and the voltage at the two ends of the capacitor can not be suddenly changed by pulling the lower polar plate of the first capacitor C1 to the ground, so that the parallel connection of C1 and C2 is realized. It should be noted that under the multi-stage condition, the capacitors are pulled down step by step in the same way, and finally the conversion from serial to parallel is realized;
when the parallel connection is switched to the series connection, the series connection is sequentially carried out from the high level to the low level, the conversion process is that the lower polar plate of the first capacitor C1 is connected with the upper polar plate of the second capacitor C2, and the series connection of the C1 and the C2 is realized by pulling the lower polar plate of the first capacitor C1 high and not changing the voltage at the two ends of the capacitor suddenly. It should be noted that under the multi-stage condition, the capacitor is pulled up step by step in the same way, and finally the conversion from parallel to serial is realized.
Referring to fig. 2-5, and examples of the above, one example of a trigger capacitor series-parallel condition is as follows:
When switching from series to parallel, the voltage bo0=gnd=0v at the previous series moment; at the time of the parallel connection, the clock signal clk_a voltage is equal to VREG. At this time, the MOS tube NM_P4 in the parallel control unit is opened to pull down the dot voltage DR_2, and the switch driving unit is triggered to perform capacitor parallel connection. Since the voltage BO1 is equal TO0 at the previous series time, when the clock signal clk_a=vreg, the MOS transistor nm_p2 cannot be turned on and the dot voltage dr_1 cannot be pulled down, so that the capacitance is gradually changed from bottom TO top;
When the parallel connection is changed into the series connection, a branch current is provided by an on-current source IBIAS, the voltage of the input end of the Gao Fanxiang device is gradually pulled through resistor voltage division, and the switch driving unit is triggered to realize capacitor series connection. The current of the branch circuit is gradually increased through the resistor, so that the capacitor is gradually increased from top to bottom through parallel connection.
Referring to fig. 6, one implementation of improving efficiency by energy recovery is as follows:
When the capacitor is in a series charging condition, charge flows into parasitic devices such as parasitic diodes in addition to the upper plate of the capacitor. When the circuit starts to be connected in parallel from series, the voltage on the parasitic device is larger than the voltage of the upper plate of the capacitor, and the charges existing on the parasitic device can flow back to the upper plate of the capacitor again, so that energy recovery is realized. By energy recovery, energy loss is reduced, thereby improving the conversion efficiency of the power converter. Therefore, the conversion efficiency of the voltage reduction and stabilization is greatly improved through the energy recovery effect in the serial-parallel conversion.
Based on the same inventive concept, the present disclosure further provides a buck regulator, where the core of the voltage stabilizing unit of the buck regulator is the buck regulator circuit of any one of the foregoing embodiments, that is, the buck regulator unit includes at least two cascaded buck regulator circuits in series, where the output voltage of the previous stage buck regulator circuit is the input voltage of the next stage buck regulator circuit.
Referring to fig. 7-8, one example of a voltage stabilizing core circuit constituted by a two-stage step-down voltage stabilizing circuit is as follows:
In the practical circuit construction process, a structure which is completely symmetrical left and right is adopted, and the working modes of the circuits at the left end and the right end are controlled through complementary clock signals. The circuit structure adopts two stages in series, the first stage is an M-stage capacitor series-parallel structure, the second stage is an N-stage capacitor series-parallel structure, and TO0 output by the first stage is used as the input of the second stage circuit, so that the circuit can realize voltage reduction by M times and N times. Therefore, when the first stage uses the M-stage capacitor for serial-parallel connection and the second stage uses the N-stage capacitor for serial-parallel connection, the function that the output voltage is 1/M times N times of the input voltage can be realized.
Based on the same inventive concept, the present disclosure further provides a power manager, where the voltage stabilizing unit in the power manager may include a voltage reducing and stabilizing circuit as described in any one of the foregoing examples, or be a voltage reducing and stabilizing circuit as described in the foregoing examples, and is a circuit core unit for performing secondary voltage stabilization in power management.
Based on the same inventive concept, the present disclosure also provides an embedded system, in which a core module of a secondary power supply of the embedded system may include a buck voltage stabilizing circuit, or a buck voltage stabilizer, or a power manager, as described in any one of the foregoing examples, so as to provide a stable secondary voltage for the embedded system based on the core module.
In this specification, identical and similar parts of the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the description is relatively simple for the embodiments described later, and reference is made to the description of the foregoing embodiments for relevant points.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims (10)

1. A voltage step-down and stabilizing circuit, comprising: the device comprises a serial-parallel structure selection unit, a serial control unit, a parallel control unit, a switch driving unit and a capacitor serial-parallel execution unit;
The serial-parallel structure selection unit is used for generating a serial-parallel selection signal corresponding to the series of the capacitor serial-parallel connection stage aiming at the input voltage under the triggering of the first level state of the first clock signal, and outputting the serial-parallel selection signal to the next-stage serial control unit;
The series control unit is used for generating a series signal for controlling the capacitors to be connected in series according to the input series-parallel selection signal, and outputting the series signal to the next-stage switch driving unit so as to convert the capacitors into a series structure in the capacitor series-parallel execution unit to realize capacitor voltage division type voltage reduction;
The parallel control unit is used for generating a parallel signal for controlling the capacitor to be connected in parallel under the triggering of the second level state of the first clock, and outputting the parallel signal to the next-stage switch driving unit so as to convert the capacitor into a parallel structure in the capacitor serial-parallel execution unit to realize voltage reduction and then provide output driving current;
The switch driving unit is used for generating serial-parallel execution signals corresponding to the polar plates at the two ends of the capacitor in the capacitor serial-parallel execution unit by the serial signal output by the serial control unit and the parallel signal output by the parallel control unit;
and the capacitor serial-parallel execution unit is used for realizing serial-parallel conversion of the capacitor between the serial structure and the parallel structure according to the serial-parallel execution signal so as to output corresponding voltage-reducing and voltage-stabilizing voltage.
2. The buck voltage regulator circuit according to claim 1, wherein the series-parallel structure selection unit includes a plurality of resistors and a plurality of comparators, wherein the plurality of resistors are configured to divide an input voltage into a plurality of different divided voltages, the plurality of different divided voltages are respectively input to positive inputs of the corresponding comparators, and negative inputs of the comparators are connected to the reference voltage.
3. The buck and voltage regulator circuit according to claim 2, wherein the serial-parallel structure selection unit further includes a plurality of and gates, a plurality of first current mirrors, and a plurality of MOS transistors; the MOS transistor comprises an AND gate, a first current mirror and an MOS transistor, wherein the AND gate, the first current mirror and the MOS transistor are used for jointly generating a current control signal, one input end of the AND gate is connected with an output level signal of a corresponding comparator, the other input end of the AND gate is connected with a reference level, the output end of the AND gate is used for driving a grid electrode of the MOS transistor, a source electrode of the MOS transistor generates bias current through a resistor, and the bias circuit forms the current control signal after passing through the corresponding current mirror to serve as the serial-parallel connection selection signal.
4. The buck voltage regulator circuit according to claim 3, wherein the series control unit includes a plurality of second current mirrors, a plurality of first inverters, and a series current branch; the series current branch is located between the output end of the second current mirror and the input end of the corresponding first inverter, the current of the current source in the series current branch flows through the connection point between the output end of the second current mirror and the input end of the corresponding first inverter, the second current mirror is used for being connected with the corresponding current control signal, so that after passing through the series resistor and the MOS tube on the series current branch, a corresponding first point potential is formed at the input end of the corresponding first inverter, and the corresponding series signal is formed after the first point potential passes through the first inverter.
5. The buck and voltage regulator circuit according to claim 3, wherein the parallel control unit includes a plurality of first NMOS transistors, a plurality of second NMOS transistors, a plurality of pairs of transistors, and a plurality of second inverters; the grid electrode of the first NMOS tube is connected with the second clock signal CLK_A, the source electrode of the first NMOS tube is connected with the lower polar plate of the corresponding capacitor, the drain electrode of the second NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the input end of the second inverter through a resistor and then is connected with the upper polar plate of the corresponding capacitor, the pair of the NMOS tubes are NMOS pair tubes, the grid electrodes of the pair of the NMOS pair tubes are respectively input with the corresponding clock signal pair triggered by the second clock signal CLK_A, the drain electrodes of the pair of the NMOS pair tubes are respectively connected with the upper polar plate voltage and the lower polar plate voltage, the source electrode of the pair of the NMOS pair tubes are connected with each other and then used for driving the grid electrodes of the second NMOS tube, so that the input end of the second inverter forms the corresponding parallel potential, and the second inverter reversely outputs the corresponding parallel signal.
6. The buck voltage regulator circuit according to claim 1, wherein the switch driver unit includes a plurality of SR flip-flops, wherein an R input terminal of the SR flip-flop is configured to be coupled to a corresponding parallel signal, an S input terminal of the SR flip-flop is configured to be coupled to a corresponding serial signal, and the serial-parallel execution signal is output according to the input parallel signal and serial signal.
7. The buck voltage regulator circuit according to claim 1, wherein the capacitor serial-parallel execution unit includes a plurality of stages of capacitor serial-parallel units; each stage of capacitor serial-parallel unit comprises a capacitor, a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube;
the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and connected with the serial-parallel execution signal corresponding to the serial signal;
The source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and the upper polar plate of the capacitor, and the connecting point is used as a connecting point for carrying out series-parallel connection with the serial-parallel connection unit of the capacitor at the upper stage;
The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and then is used as a connection point for carrying out series-parallel connection with the next-stage capacitor series-parallel unit;
the grid of the first NMOS tube is connected with the serial-parallel execution signal corresponding to the connected parallel signal;
The source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and the lower polar plate of the capacitor;
the drain electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded.
8. A buck regulator comprising a buck regulator unit, wherein the buck regulator unit comprises at least two buck regulator circuits connected in series, wherein the output voltage of the previous stage buck regulator circuit is the input voltage of the next stage buck regulator circuit, and the buck regulator circuit is the buck regulator circuit of any one of claims 1-7.
9. A power supply manager comprising a voltage stabilizing unit, characterized in that the voltage stabilizing unit comprises a buck voltage stabilizing circuit according to any one of claims 1-7, or the voltage stabilizing unit comprises a buck voltage stabilizer according to claim 8.
10. An embedded system comprising a secondary power module, wherein the secondary power module comprises a buck regulator circuit according to any one of claims 1 to 7, or wherein the secondary power module comprises a buck regulator according to claim 8, or wherein the secondary power module comprises a power manager according to claim 9.
CN202310180640.4A 2023-02-28 2023-02-28 Step-down voltage stabilizing circuit, voltage stabilizer, power manager and embedded system Active CN115981404B (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104883058A (en) * 2015-06-30 2015-09-02 株洲科瑞变流电气有限公司 Power source based on IGBT serial-parallel connection

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI384741B (en) * 2009-08-17 2013-02-01 Richtek Technology Corp Switching regulator with transient control function and control circuit and method therefor
JP2012243193A (en) * 2011-05-23 2012-12-10 Renesas Electronics Corp Semiconductor integrated circuit and operation method therefor
CN211377896U (en) * 2019-08-31 2020-08-28 南京伟思医疗科技股份有限公司 NMOS transistor-based wide-voltage-input direct-current voltage reduction circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104883058A (en) * 2015-06-30 2015-09-02 株洲科瑞变流电气有限公司 Power source based on IGBT serial-parallel connection

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
基于串联开关型稳压电源的分析与研究;武峭山;;电子设计工程;20151105(第21期);全文 *

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