CN115981404A - Voltage reduction and stabilization circuit, voltage stabilizer, power supply manager and embedded system - Google Patents

Abstract

The application provides a step-down voltage stabilizing circuit, the voltage stabilizer, power manager and embedded system, be applied to power and integrated circuit technical field, wherein voltage stabilizing circuit includes serial and parallel structure selection unit, the series control unit, parallel control unit, switch drive unit and electric capacity serial and parallel execution unit, wherein serial and parallel structure selection unit generates the select signal, the series control unit generates the series signal, parallel control unit generates the parallel signal, switch drive unit combines series signal and parallel signal to generate the execute signal that is used for controlling electric capacity to carry out the serial and parallel conversion, electric capacity serial and parallel execution unit triggers electric capacity according to the execute signal and carries out the serial and parallel conversion. The voltage reduction and stabilization are realized by adopting the series-parallel conversion of the capacitor, the wide input voltage range can be adapted, an external energy storage inductor, an MOS (metal oxide semiconductor) tube and the like are not needed, the power supply has the advantages of small volume, low power consumption, high conversion efficiency and the like, and good secondary power supply voltage can be provided for an embedded system.

Description

Voltage reduction and stabilization circuit, voltage stabilizer, power supply manager and embedded system

Technical Field

The application relates to the technical field of power supplies and integrated circuits, in particular to a voltage reduction and stabilization circuit, a voltage stabilizer, a power supply manager and an embedded system.

Background

In embedded systems, the most commonly used secondary power supply circuits are low dropout linear regulators (LDO) and BUCK switching regulators (BUCK).

However, in the secondary power supply circuit LDO, when the voltage difference between the input and the output is large, the voltage regulator consumes more power (i.e., the heat effect is lost, which results in huge heat generation, low efficiency, etc., and a large heat sink is additionally required).

In the secondary power circuit BUCK, an external inductor is needed, the size is large, and even an external MOS tube is needed. Further, the BUCK circuit has ripples in both input and output currents, causing electromagnetic interference with the input power supply and making the emitter of the switching transistor in the BUCK circuit not grounded, which complicates the driving circuit.

Based on this, a new step-down circuit is required as the secondary power supply circuit.

Disclosure of Invention

In view of this, the present application provides a novel voltage reduction structure with a wide input voltage range and high efficiency to overcome the defects of the conventional voltage reduction circuit, and in the structure, the series-parallel connection stage number of the capacitor voltage division is determined by the input voltage, so that the off-chip inductance used by the conventional voltage reduction circuit is avoided.

The embodiment of the specification provides the following technical scheme:

an embodiment of the present specification provides a voltage reduction and stabilization circuit, including: the device comprises a serial-parallel structure selection unit, a serial control unit, a parallel control unit, a switch driving unit and a capacitor serial-parallel execution unit;

the serial-parallel structure selection unit is used for generating serial-parallel selection signals corresponding to the serial-parallel series of the capacitor aiming at the input voltage under the trigger of the first level state of the first clock signal and outputting the serial-parallel selection signals to the next-stage serial control unit;

the series control unit is used for generating a series signal for controlling the capacitors to be connected in series according to the input series-parallel selection signal and outputting the series signal to the next-stage switch driving unit so as to convert the capacitors into a series structure in the capacitor series-parallel execution unit to realize capacitor voltage division type voltage reduction;

the parallel control unit is used for generating a parallel signal for controlling the capacitors to be connected in parallel under the trigger of a second level state of the first clock, and outputting the parallel signal to the next-stage switch driving unit so as to convert the capacitors into a parallel structure in the capacitor series-parallel execution unit to realize voltage reduction and provide output driving current;

the switch driving unit is used for generating serial-parallel execution signals corresponding to electrode plates at two ends of a capacitor in the capacitor serial-parallel execution unit according to the serial signals output by the serial control unit and the parallel signals output by the parallel control unit;

and the capacitor serial-parallel execution unit is used for realizing serial-parallel conversion of the capacitor between a serial structure and a parallel structure according to the serial-parallel execution signal so as to output corresponding voltage reduction and stabilization voltage.

Preferably, the serial-parallel structure selection unit includes a plurality of resistors and a plurality of comparators, wherein the plurality of resistors are used for dividing the input voltage into a plurality of different divided voltages, the plurality of different divided voltages are correspondingly input to the positive input terminals of the corresponding comparators, and the negative input terminals of the comparators are connected to the reference voltage.

Preferably, the serial-parallel structure selection unit further comprises a plurality of and gates, a plurality of first current mirrors and a plurality of MOS transistors; the device comprises an AND gate, a first current mirror and an MOS (metal oxide semiconductor) tube, wherein the AND gate, the first current mirror and the MOS tube are used for generating a current control signal together, one input end of the AND gate is connected with an output level signal of a corresponding comparator, the other input end of the AND gate is connected with a reference level, the output end of the AND gate is used for driving a grid electrode of the MOS tube, a source electrode of the MOS tube generates a bias current through a resistor, and the bias circuit forms the current control signal as the series-parallel connection selection signal after passing through the corresponding current mirror.

Preferably, the series control unit comprises a plurality of second current mirrors, a plurality of first inverters and a series current branch; the series current branch circuit is positioned between the output end of the second current mirror and the input end of the corresponding first phase inverter, the current of a current source in the series current branch circuit flows through a connecting point between the output end of the second current mirror and the input end of the corresponding first phase inverter, the second current mirror is used for connecting corresponding current control signals, and after passing through a series resistor and an MOS (metal oxide semiconductor) tube on the series current branch circuit, a corresponding first point potential is formed at the input end of the corresponding first phase inverter, so that the first point potential forms a corresponding series signal after passing through the first phase inverter.

Preferably, the parallel control unit comprises a plurality of first NMOS transistors, a plurality of second NMOS transistors, a plurality of pair transistors and a plurality of second inverters; the grid electrode of the first NMOS tube is connected with a second clock signal CLK _ A, the source electrode of the first NMOS tube is connected with the lower pole plate of the corresponding capacitor, the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the input end of the second inverter and is connected with the upper pole plate of the corresponding capacitor after passing through a resistor, the pair tubes are NMOS pair tubes, the grid electrodes of the NMOS pair tubes are respectively input with the corresponding clock signal pair triggered by the second clock signal CLK _ A, the drain electrodes are respectively connected with the upper pole plate voltage and the lower pole plate voltage, the source electrodes of the NMOS pair tubes are mutually connected and then are used for driving the grid electrode of the second NMOS tube, so that corresponding parallel potentials are formed at the input end of the second inverter, and the parallel potentials are reversely output by the second inverter.

Preferably, the switch driving unit includes a plurality of SR flip-flops, wherein R input terminals of the SR flip-flops are used to access corresponding parallel signals, and S input terminals of the SR flip-flops are used to access corresponding serial signals, and output corresponding serial-parallel execution signals according to the input parallel signals and serial signals.

Preferably, the capacitor serial-parallel execution unit comprises a plurality of stages of capacitor serial-parallel units; each stage of capacitor serial-parallel unit comprises a capacitor, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube;

the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are connected with each other and are connected with the serial-parallel execution signal corresponding to the serial-connection signal;

the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the upper electrode plate of the capacitor are interconnected, and the connection point is used as a connection point for series-parallel connection with the upper-stage capacitor series-parallel unit;

the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are interconnected and then serve as a connecting point for series-parallel connection with a next-stage capacitor series-parallel unit;

the grid of the first NMOS tube is connected into the serial-parallel execution signal corresponding to the parallel signal;

the source electrode of the first NMOS tube is interconnected with the drain electrode of the second NMOS tube and the lower polar plate of the capacitor;

the drain electrode of the second PMOS tube is interconnected with the grid electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded.

The embodiment of the present specification further provides a step-down voltage regulator, which includes a step-down and voltage-stabilizing unit, where the step-down and voltage-stabilizing unit includes at least two cascaded step-down voltage-stabilizing circuits connected in series, where an output voltage of a previous step-down voltage-stabilizing circuit is an input voltage of a next step-down voltage-stabilizing circuit, and the step-down voltage-stabilizing circuit is the step-down voltage-stabilizing circuit according to any one embodiment of the present specification.

An embodiment of the present specification further provides a power manager, including a voltage stabilizing unit, where the voltage stabilizing unit includes the step-down voltage stabilizing circuit according to any one of the embodiments of the present specification, or the voltage stabilizing unit includes the step-down voltage stabilizer according to any one of the embodiments of the present specification.

An embodiment of the present specification further provides an embedded system, including a secondary power supply module, where the secondary power supply module includes the step-down voltage stabilizing circuit according to any one embodiment of the present specification, or the secondary power supply module includes the step-down voltage stabilizer according to any one embodiment of the present specification, or the secondary power supply module includes the power manager according to any one embodiment of the present specification.

Compared with the prior art, the beneficial effects that can be achieved by the at least one technical scheme adopted by the embodiment of the specification at least comprise:

the voltage reduction function is realized through series-parallel connection of the capacitors, no additional inductor is needed, so that the heat generation quantity is small, the occupied area is greatly reduced, the extremely wide input voltage range can be realized, and the application occasions are extremely wide; the middle part of the power supply converter greatly improves the conversion efficiency of the power supply converter through an energy recovery effect, can realize the adjustability of output load within a certain range, and can adapt to the environments with different loads.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a circuit structure for implementing voltage reduction and voltage stabilization based on series-parallel conversion of capacitors in the present application;

FIG. 2 is a schematic diagram of a serial-parallel structure selection unit in the present application;

FIG. 3 is a schematic diagram of the structure of a series control unit in the present application;

FIG. 4 is a schematic diagram of the structure of a parallel control unit in the present application;

FIG. 5 is a schematic structural diagram of a switch driving unit and a capacitor serial-parallel execution unit in the present application;

FIG. 6 is a schematic diagram of the structure of the capacitor in series-parallel conversion for energy recovery;

FIG. 7 is a schematic diagram of a series configuration of a multi-stage buck voltage regulator circuit according to the present application;

FIG. 8 is a schematic diagram of a series configuration of a multi-stage buck voltage regulator circuit according to the present application.

Detailed Description

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. The application is capable of other and different embodiments and its several details are capable of modifications and various changes in detail without departing from the spirit of the application. It should be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number and aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.

The existing low dropout voltage regulator (LDO) cannot be applied to the occasion of wide input voltage because the voltage difference between the input voltage and the output voltage becomes the power consumption of the voltage regulator, and can only be applied to the occasion of small voltage difference. The BUCK switching regulator (BUCK) is suitable for wide input voltage, but is limited by its structure, poor in electromagnetic performance, and requires an additional energy storage inductor, even an external MOS transistor, and a complex driving circuit.

In view of this, after deep research and improved exploration are performed on a voltage regulator circuit and a buck-boost mode, an embodiment of the present disclosure provides a buck-boost processing scheme: as shown in fig. 1, by determining the series-parallel stage number of the divided voltage of the capacitor, the novel step-down circuit with wide input voltage range and high power conversion efficiency is realized by controlling the series-parallel connection of the capacitor, and the step-down output voltage is not generated by the off-chip inductance method in the conventional method. Wherein, this novel step-down circuit's functional module includes: the device comprises a serial-parallel structure selection unit, a serial control unit, a parallel control unit, a switch driving unit and a capacitor serial-parallel execution unit.

A serial-parallel structure selection unit for generating serial-parallel selection signals SPi (shown as SP1 to SPm in fig. 1) related to serial-parallel progression of capacitors under different input voltages, and outputting the signals to the next-stage serial control unit and the parallel control unit;

the series control unit is used for generating series signals DSi (such as DS 1-DSm shown in figure 1) for controlling the capacitors to be connected in series according to the input series-parallel selection signals and outputting the series signals to the next-stage switch driving unit so as to realize the function of voltage division and voltage reduction of the capacitors when the capacitors are connected in series in the capacitor series-parallel execution unit;

the parallel control unit is used for generating parallel signals DRi (such as DR1 to DRm illustrated in fig. 1) for controlling the capacitors to be connected in parallel and outputting the parallel signals to the next-stage switch driving unit so as to realize the effect of outputting driving current after voltage reduction when the capacitors are connected in parallel in the capacitor series-parallel execution unit;

the switch driving unit is configured to generate, according to the input serial signal and parallel signal corresponding to each capacitor, an execution signal (for example, OUT1 to OUTq shown in fig. 1, it is to be noted that a subscript q may be equal to or different from the subscript M, and is not limited herein) that controls plates at two ends of the capacitor to be connected to different positions, so that the capacitors in the capacitor serial-parallel execution unit complete a serial-parallel conversion action under precise switch delay control of the execution signal, so that the output voltage is a corresponding voltage value after the input voltage is reduced, for example, in a voltage reduction and stabilization process in which M capacitors perform serial-parallel conversion, the output voltage Vo = Vin/M.

The number of the series-parallel capacitors, the number of the control signals generated by each circuit unit, and the like may be determined according to the actual application requirements, and are not particularly limited herein.

The voltage reduction and the voltage stabilization are realized through series-parallel connection conversion based on the capacitor, the voltage reduction and the voltage stabilization can be adapted to large-range input voltage application occasions, external energy storage inductors, MOS (metal oxide semiconductor) tubes and the like are not needed in the circuit in the traditional scheme, the electromagnetic interference on the input voltage is small, and the application requirements of various embedded systems on secondary voltage can be met.

In addition, in the novel voltage reduction and voltage stabilization circuit, the input voltage is directly used for deciding the series-parallel series number of the capacitor, so that a plurality of control capacitors can be generated by the series-parallel structure selection unit according to the input voltage to complete the digital signals for series-parallel conversion, the voltage reduction energy conversion is realized by the capacitor, and the voltage reduction and voltage stabilization are not required to be carried out by using an external energy storage inductor or even a power MOS (metal oxide semiconductor) tube in the traditional scheme. Therefore, in an application occasion suitable for an extremely wide input voltage range, even if a large voltage difference exists between an output voltage and an input voltage, the heat generated by the whole circuit is very little, a large-area radiator is not needed, and the occupied area of the circuit can be greatly reduced. And by adjusting the series-parallel connection of the capacitors and the series connection of the modules, the output load within a certain range can be flexibly adjusted, and the adjustable output load can adapt to environments with different loads.

In some embodiments, the serial-parallel structure selection unit may employ a resistor and a comparator, obtain different divided voltages by dividing voltages through the resistor, and then use the divided voltages for the comparator to compare and output, so as to form a serial-parallel control signal according to an input voltage.

As shown in fig. 2, the serial-parallel structure selection unit includes a series of resistors to divide the input voltage to obtain corresponding divided voltages (REF _1D1, REF _1Dm shown in fig. 2), which are correspondingly input to the positive input terminals of the comparators, and the other terminals of the comparators are connected to the bandgap reference voltage VREF, so that the comparators correspondingly output corresponding digital signals (ON _2, ON _ M, etc. shown in fig. 2) as serial-parallel signals.

In some embodiments, the output of the comparator may be shaped and driven by a corresponding digital circuit to form a new signal, so that the new signal is more easily connected with a subsequent circuit, and is more suitable for signal transmission, driving control and the like.

As shown in fig. 2, the output signals of the comparators (such as ON _2, ON _ M shown in fig. 2) are connected to one input end of the corresponding and gate, the other input end of the and gate is connected to the output voltage reference level VREG, the output of the and gate is connected to the gate of the NMOS transistor, the source output of the NMOS transistor generates a corresponding bias current through a resistor, and the bias current forms a current control signal as a series-parallel signal after being current-mirrored, which can be used as an input for the next stage of circuit.

It should be noted that the high and low levels of CLK correspond to VREG and 0V, so that the accurate output control of the serial-parallel signals is realized by the high level of CLK in combination with the and gate.

As shown in fig. 2, the output of the first AND gate AND _1 is connected to the gate of the first NMOS transistor M _1, the source output of the first NMOS transistor M _1 generates a first bias current Ibias1 via a resistor, AND the first bias current Ibias1 passes through a first current mirror (i.e., the current mirror _ 1) to form a current control signal I1 as the input of the next stage circuit (i.e., the series control unit).

In some embodiments, when the control signal output by the serial-parallel structure selection unit is a current control signal, the serial control unit may generate a corresponding serial control signal according to the current control signal by using a circuit such as a corresponding current mirror and an inverter.

The series-parallel connection of the whole circuit can be controlled by a clock signal CLK with a duty ratio of 1/2, when the CLK is at a high level, the circuit is in a series connection state, the high level CLK signal triggers a current source in the series connection control unit to generate current, and the circuit is connected in series from top to bottom. When the CLK signal is at low level, the circuit is in parallel connection, the low level CLK signal triggers the parallel connection control unit to generate the clock signal CLK _ A and the clock signal pair CTL _ S1 and CTL _ S1B triggered by the CLK _ A, and the circuit is connected in parallel step by step from bottom to top.

As shown in fig. 3, taking the two-capacitor series control as an example, the series control unit may include a third current mirror (i.e., current mirror _ 3) and a fourth current mirror (i.e., current mirror _ 4), the input current signals of the respective current mirrors are the current control signals (i.e., I1 and I2) of the foregoing examples, respectively, and the respective output terminals of the current mirrors are connected to the input terminals (DS _1 and DS _ 2) of the corresponding first inverter (i.e., inverter _ 1) and second inverter (i.e., inverter _ 2) as illustrated in fig. 3.

The main branch of the series control unit is supplied with current by a current source IBIAS, which flows through DS _1 and a first resistor R1 to the source of the first PMOS transistor PM _ S1, and then flows through DS _2 and a second resistor R2 from the drain of PM _ S1 to the source of the second PMOS transistor PM _ S2. The voltages at the points DS _1 and DS _2 are output as series signals DS1 and DS2 after passing through the first inverter and the second inverter, respectively.

In one example, the inverter may be formed of a plurality of MOS transistors. As shown in fig. 3, in the first inverter, the first upper plate level signal TOM corresponding to the first capacitor converts the voltage at DS _1 of the input inverter into the output DS1 of the inverter through the resistor and the PMOS transistor, and the first lower plate level signal BOM converts the voltage at DS _1 of the input inverter into the output DS1 of the inverter through the NMOS transistor. In other words, when DS _1 is high, DS1 depends on BOM, and when DS _1 is low, DS1 depends on TOM.

Further, in the circuit processing for determining DS1 for BOM, two NMOS transistors may be used, where BOM is connected to the gate and source of the first NMOS transistor, the gate of the second NMOS transistor is connected to DS _1, the drain of the second NMOS transistor is connected to DS1, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor.

It should be noted that the second inverter may adopt the same circuit form as the first inverter, and particularly refer to the schematic diagram of fig. 3, which is not expanded here.

After the inverter is adopted in the series control unit to output the series signal, the series signal can be output to the switch driving unit, and the switch driving unit further processes the series signal to form an execution signal required by the capacitor series-parallel execution unit.

In some embodiments, the parallel control unit may employ a resistor, a MOS transistor, or the like to generate the parallel signal.

As shown in fig. 4, the parallel control unit may include a third resistor R3 and a fourth resistor R4, and the point voltages (DR _1 and DR _2 shown in fig. 4) are passed through the resistors.

On one hand, the dot voltage passes through the corresponding inverter and then outputs corresponding voltages (e.g. DR1 and DR2 as shown in fig. 4) as input signals of the next stage of switch driving unit;

on the other hand, the dot voltage is connected to the drain of the corresponding MOS transistor (NM _ P1, NM _ P3 shown in fig. 4), the source of the corresponding MOS transistor is connected to the drain of the corresponding other MOS transistor (NM _ P2, NM _ P4 shown in fig. 4), the gate of the other MOS transistor (NM _ P2, NM _ P4 shown in fig. 4) is connected to the clock signal CLK _ a, and the source of the other MOS transistor is connected to the bottom plate voltage (BO 1, BO0 shown in fig. 4) of the corresponding different plate capacitance. The gates of the pair transistors NM _ P5 and NM _ P6 are respectively connected with clock signal pairs CTL _ S1 and CTL _ S1B triggered by CLK _ A, the drains of the pair transistors are correspondingly connected with an upper plate voltage TO1 and a lower plate voltage BO2, and the sources are commonly connected with the gate of NM _ P1;

similarly, the gates of the pair of transistors NM _ P7 and NM _ P8 are connected TO the corresponding pair of clock signals CTL _2S, CTL _ S2B, the drains of the pair of transistors are connected TO the other upper plate voltage TO0 and the other lower plate voltage BO1, and the sources are connected TO the gate of NM _ P3.

In the implementation, the high and low levels of the second clock signal (such as CLK _ a shown in fig. 4) correspond to VREG and 0V, and when CLK _ a is VREG and the corresponding BO is connected to GND, the NMOS connected to CLK _ a is turned on, so that the trigger circuits are connected in parallel. In addition, the high and low levels of the inverse clock pair CTL _ S correspond to the voltages of the upper and lower plates of the corresponding stage capacitor, when the stage circuit is completed in parallel, the NMOS corresponding to the CLK _ SB high is turned on, that is, the drain of the NMOS after completion of parallel connection is connected to the lower plate voltage of the capacitor, which is GND, the source output of the NMOS transistor is low level, the NMOS controlled by the source (such as NM _ P1 and NM _ P3 shown in fig. 4) will be turned off, and at this time, the branch circuit has no current, thus reducing the loss.

Therefore, the series-parallel conversion of the circuit is controlled by the first clock signal CLK, the reset state of the circuit can be a capacitor parallel state, when the CLK is at a high level, the series branch circuit is triggered to realize the step-by-step series connection, when the series connection is completed and the charging is completed by using Vin input energy, and the CLK signal becomes low, the parallel branch circuit is triggered to realize the parallel output of the circuit, and the parallel signal only triggers the SR trigger temporarily, so that the circuit realizes the stable output after the voltage reduction.

And the clock signal CLK _ A and the clock signal are used for controlling the cooperation of the CTR _ S, so that the accurate parallel signal generation and output control are realized.

In some embodiments, the switch driving unit may generate corresponding serial and parallel execution signals by using an SR flip-flop (also referred to as an RS flip-flop, which is not distinguished herein) based on the input serial signal and parallel signal, so that the serial and parallel execution signals are mutually exclusive, and the correctness and reliability of the circuit operation are ensured.

As shown in fig. 5, the switch driving unit may include a digital logic portion mainly including an SR flip-flop. The input terminals S1 and R1 of the first flip-flop (such as SR flip-flop _1 illustrated in fig. 5) are respectively connected to the series control unit and the parallel control units DS1 and DR1, and the flip-flop switches drive output signals corresponding to OUT1 and OUT2.

Similarly, the input terminals S2 and R2 of the second SR flip-flop (such as SR flip-flop _2 shown in fig. 5) are respectively connected to the series control unit and the parallel control unit DS2 and DR2, and the switch driving output signals of the second SR flip-flop are corresponding to OUT3 and OUT4.

In some embodiments, the capacitor serial-parallel execution unit may be a circuit unit in which a plurality of capacitors are serial-parallel converted under the control of an output signal of the switch driving unit, that is, the capacitor serial-parallel execution unit includes a plurality of capacitors and a switch circuit for connecting, connecting and converting the plurality of capacitors in series, in parallel.

As shown in fig. 5, the capacitor serial-parallel execution unit includes a first capacitor serial-parallel unit and a second capacitor serial-parallel unit. The first capacitor series-parallel unit comprises MOS (metal oxide semiconductor) tubes such as PM1, PM2, NM1 and NM2 and a first capacitor C1; the second capacitor series-parallel unit comprises MOS (metal oxide semiconductor) tubes such as PM3, PM4, NM3 and NM4 and a second capacitor C2.

The connection relationship is schematically as follows: the grid electrodes of PM1 and NM1 are respectively connected with OUT1 and OUT2 output by the switch driving unit, the grid electrode of PM1 is connected with the grid electrode of PM2, the source electrode of PM1 is connected with the source electrode of PM2 and is connected with the upper plate electrode of the first capacitor C1, and the drain electrode of PM1 is connected with the drain electrode of NM1 and is connected with the upper plate electrode of the second capacitor C2. The drain electrode of the PM2 is connected with the grid electrode of the NM2, and the source electrode of the NM1 is connected with the drain electrode of the NM2 and connected with the lower electrode plate of the first capacitor C1;

similarly, the gates of PM3 and NM3 are respectively connected to OUT3 and OUT4 outputted by the switch driving unit, the gate of PM3 is connected to the gate of PM4, the source of PM3 is connected to the source of PM4 and connected to the upper electrode plate of the second capacitor C2, the drain of PM3 is connected to the drain of NM3, the drain of PM4 is connected to the gate of the NM4 transistor, the source of NM3 is connected to the drain of NM4 and connected to the lower electrode plate of the second capacitor C2;

in addition, the drains of PM1 and NM1 are connected with the sources of PM3 and PM4 to form a structure for performing series-parallel conversion between the two capacitor series-parallel units.

With reference to fig. 2-5, and the above exemplary disclosure, the process of stepping down through the capacitor string is schematically illustrated as follows:

according to different input voltage ranges, after the voltage is divided by the resistors, the output voltage obtained by each stage is different relatively. The output signal obtained after the voltage division of the resistors is compared with a reference voltage through a comparator to generate corresponding high and low level signals, the high and low levels control the series-parallel connection stage number, and the capacitor which does not participate in the series-parallel connection conversion is connected with the lowest stage capacitor in parallel to participate in the circuit work, so that the voltage reduction and voltage stabilization output of the input voltage Vin is realized to obtain the output voltage Vo.

With reference to fig. 2-5, and the above exemplary contents, the capacitor series-parallel implementation is schematically illustrated as follows:

when the conversion from series connection to parallel connection is carried out, low-level to high-level are sequentially connected in parallel step by step, the voltage of the upper plate of the first capacitor C1 is kept unchanged in the conversion process, and the lower plate of the first capacitor C1 is pulled to the ground, so that the C1 and the C2 are connected in parallel according to the fact that the voltage at two ends of the capacitor cannot change suddenly. It should be noted that, the capacitance is pulled down step by step in the same way under the condition of multiple stages, and the conversion from series to parallel is finally realized;

when the conversion is from parallel connection to series connection, the series connection is sequentially carried out from high level to low level, the conversion process is that the lower polar plate of the first capacitor C1 is connected with the upper polar plate of the second capacitor C2, and the voltage cannot change suddenly according to the voltage at two ends of the capacitor by pulling the lower polar plate of the first capacitor C1 high, so that the series connection of the C1 and the C2 is realized. It should be noted that, in the case of multiple stages, the capacitor is pulled up step by step, and finally, parallel-to-serial conversion is realized.

Referring to fig. 2-5, and the above example, one example of a triggered capacitive series-parallel condition is as follows:

when switching from series to parallel, at the previous series moment, the voltage BO0= GND =0V; at the parallel time, the voltage of the clock signal CLK _ A is equal to VREG. At the moment, the MOS tube NM _ P4 in the parallel control unit is opened, the point voltage DR _2 is pulled down, and the switch driving unit is triggered to carry out capacitor parallel connection. Since the voltage BO1 is equal TO0 at the previous serial time, when the clock signal CLK _ a = VREG, the MOS transistor NM _ P2 cannot be turned on, and the dot voltage DR _1 cannot be pulled down, the capacitor is switched from serial TO serial and is performed step by step from bottom TO top;

when the parallel connection is changed into the series connection, a branch current is provided by a starting current source IBIAS, the voltage of the input end of the inverter is gradually increased through resistance voltage division, and the switch driving unit is triggered to realize the series connection of the capacitors. Because the branch current is required to be carried out step by step through the resistor to raise the voltage, the parallel-serial connection of the capacitor is carried out step by step from top to bottom.

Referring to fig. 6, one implementation of improving efficiency through energy recovery is as follows:

when the capacitor is in a series charging condition, charges flow into parasitic devices such as parasitic diodes in addition to the upper plate of the capacitor. When the circuit starts to be switched from series connection to parallel connection, the voltage on the parasitic device is larger than the voltage of the upper electrode plate of the capacitor, and the charges existing on the parasitic device can flow back to the upper electrode plate of the capacitor again, so that the energy recovery is realized. Through energy recovery, energy loss is reduced, and therefore conversion efficiency of the power converter is improved. Therefore, the conversion efficiency of voltage reduction and voltage stabilization is greatly improved through the energy recovery effect in the series-parallel conversion.

Based on the same inventive concept, the present specification further provides a step-down voltage regulator, where a core of a voltage stabilizing unit of the step-down voltage regulator is the step-down voltage stabilizing circuit of any one of the embodiments, that is, the step-down voltage stabilizing unit includes at least two step-down voltage stabilizing circuits cascaded in series, where an output voltage of a previous step-down voltage stabilizing circuit is an input voltage of a next step-down voltage stabilizing circuit.

Referring to fig. 7-8, an example of a regulator core circuit formed by a two-stage buck regulator circuit is as follows:

in the actual circuit building process, a left-right completely symmetrical structure is adopted, and the working modes of the left-right circuit are controlled through complementary clock signals. The circuit structure adopts two-stage series connection, the first stage is an M-stage capacitor series-parallel connection structure, the second stage is an N-stage capacitor series-parallel connection structure, and the TO0 output by the first stage is used as the input of the second stage circuit, so that the circuit can realize voltage reduction M x N times. Therefore, when the first stage is connected in series and parallel by using M stages of capacitors and the second stage is connected in series and parallel by using N stages of capacitors, a function that the output voltage is 1/M N times of the input voltage can be realized.

Based on the same inventive concept, the present specification further provides a power supply manager, in a voltage stabilizing unit in the power supply manager, the voltage stabilizing unit may include the voltage reduction and stabilization circuit described in any one of the foregoing examples, or the voltage reduction and stabilization regulator described in the foregoing example, and is a circuit core unit for performing secondary voltage stabilization in power supply management.

Based on the same inventive concept, the present specification further provides an embedded system, in which a core module of a secondary power supply of the embedded system may include the buck regulator circuit, or the buck regulator, or the power manager, as described in any of the foregoing examples, so as to provide a stable secondary voltage for the embedded system based on the core module.

In the present specification, the same and similar parts among the various embodiments may be referred to each other, and each embodiment focuses on differences from the other embodiments. In particular, for the embodiments described later, the description is simple, and the relevant points can be referred to the partial description of the previous embodiments.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A buck voltage regulator circuit, comprising: the device comprises a serial-parallel structure selection unit, a serial control unit, a parallel control unit, a switch driving unit and a capacitor serial-parallel execution unit;

the serial-parallel structure selection unit is used for generating serial-parallel selection signals corresponding to the serial-parallel series of the capacitor aiming at the input voltage under the trigger of the first level state of the first clock signal and outputting the serial-parallel selection signals to the next-stage serial control unit;

the series control unit is used for generating a series signal for controlling the capacitors to be connected in series according to an input series-parallel selection signal and outputting the series signal to the next-stage switch driving unit so as to convert the capacitors into a series structure in the capacitor series-parallel execution unit to realize capacitor voltage division type voltage reduction;

the parallel control unit is used for generating a parallel signal for controlling the capacitors to be connected in parallel under the trigger of a second level state of the first clock, and outputting the parallel signal to the next-stage switch driving unit so as to convert the capacitors into a parallel structure in the capacitor series-parallel execution unit to realize voltage reduction and then provide output driving current;

the switch driving unit is used for generating serial-parallel execution signals corresponding to electrode plates at two ends of a capacitor in the capacitor serial-parallel execution unit according to the serial signals output by the serial control unit and the parallel signals output by the parallel control unit;

and the capacitor serial-parallel execution unit is used for realizing serial-parallel conversion of the capacitor between the serial structure and the parallel structure according to the serial-parallel execution signal so as to output corresponding voltage reduction and stabilization voltage.

2. The voltage reducing and stabilizing circuit of claim 1, wherein the serial-to-parallel configuration selecting unit includes a plurality of resistors and a plurality of comparators, wherein the plurality of resistors are used for dividing the input voltage into a plurality of different divided voltages, the plurality of different divided voltages are correspondingly input to the positive input terminals of the corresponding comparators, and the negative input terminals of the comparators are connected to the reference voltage.

3. The voltage reducing and stabilizing circuit of claim 2, wherein the serial-parallel structure selection unit further comprises a plurality of AND gates, a plurality of first current mirrors and a plurality of MOS transistors; the device comprises an AND gate, a first current mirror and an MOS (metal oxide semiconductor) tube, wherein the AND gate, the first current mirror and the MOS tube are used for generating a current control signal together, one input end of the AND gate is connected with an output level signal of a corresponding comparator, the other input end of the AND gate is connected with a reference level, the output end of the AND gate is used for driving a grid electrode of the MOS tube, a source electrode of the MOS tube generates a bias current through a resistor, and the bias circuit forms the current control signal as the series-parallel connection selection signal after passing through the corresponding current mirror.

4. The buck regulator circuit of claim 3, wherein the series control unit includes a plurality of second current mirrors, a plurality of first inverters, and a series current branch; the series current branch circuit is positioned between the output end of the second current mirror and the input end of the corresponding first phase inverter, the current of a current source in the series current branch circuit flows through a connecting point between the output end of the second current mirror and the input end of the corresponding first phase inverter, the second current mirror is used for connecting corresponding current control signals, and after passing through a series resistor and an MOS (metal oxide semiconductor) tube on the series current branch circuit, a corresponding first point potential is formed at the input end of the corresponding first phase inverter, so that the first point potential forms a corresponding series signal after passing through the first phase inverter.

5. The voltage reducing and stabilizing circuit of claim 3, wherein the parallel control unit comprises a plurality of first NMOS transistors, a plurality of second NMOS transistors, a plurality of pair transistors and a plurality of second inverters; the grid electrode of the first NMOS tube is connected with a second clock signal CLK _ A, the source electrode of the first NMOS tube is connected with the lower pole plate of the corresponding capacitor, the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the input end of the second inverter and is connected with the upper pole plate of the corresponding capacitor after passing through a resistor, the pair tubes are NMOS pair tubes, the grid electrodes of the NMOS pair tubes are respectively input with the corresponding clock signal pair triggered by the second clock signal CLK _ A, the drain electrodes are respectively connected with the upper pole plate voltage and the lower pole plate voltage, the source electrodes of the NMOS pair tubes are mutually connected and then are used for driving the grid electrode of the second NMOS tube, so that corresponding parallel potentials are formed at the input end of the second inverter, and the parallel potentials are reversely output by the second inverter.

6. The buck voltage stabilizing circuit according to claim 1, wherein the switch driving unit includes a plurality of SR flip-flops, wherein R input terminals of the SR flip-flops are used for receiving corresponding parallel signals, and S input terminals of the SR flip-flops are used for receiving corresponding serial signals, and outputting corresponding serial-parallel execution signals according to the input parallel signals and serial signals.

7. The buck voltage stabilizing circuit of claim 1, wherein the capacitor cascode execution unit includes a plurality of stages of capacitor cascode units; each stage of capacitor serial-parallel unit comprises a capacitor, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube;

the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are mutually connected and are connected into the serial-parallel execution signal corresponding to the serial signal;

the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the upper electrode plate of the capacitor are interconnected, and a connection point is used as a connection point for series-parallel connection with the upper-stage capacitor series-parallel unit;

the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are interconnected and then serve as a connecting point for series-parallel connection with the next-stage capacitor series-parallel unit;

the grid of the first NMOS tube is connected into the serial-parallel execution signal corresponding to the parallel signal;

the source electrode of the first NMOS tube is interconnected with the drain electrode of the second NMOS tube and the lower electrode plate of the capacitor;

the drain electrode of the second PMOS tube is interconnected with the grid electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded.

8. A step-down voltage regulator comprising a step-down and voltage-stabilizing unit, wherein the step-down and voltage-stabilizing unit comprises at least two step-down voltage-stabilizing circuits cascaded in series, wherein an output voltage of a previous step-down voltage-stabilizing circuit is an input voltage of a next step-down voltage-stabilizing circuit, and the step-down voltage-stabilizing circuit is the step-down voltage-stabilizing circuit according to any one of claims 1 to 7.

9. A power manager comprising a regulation unit, wherein the regulation unit comprises a buck regulator circuit as claimed in any one of claims 1 to 7, or wherein the regulation unit comprises a buck regulator as claimed in claim 8.

10. An embedded system comprising a secondary power supply module, wherein the secondary power supply module comprises a buck regulator circuit as claimed in any one of claims 1 to 7, or the secondary power supply module comprises a buck regulator as claimed in claim 8, or the secondary power supply module comprises a power manager as claimed in claim 9.

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