CN103746681A - Power-on/power-down output tri-state control circuit for CMOS device power supply - Google Patents
Power-on/power-down output tri-state control circuit for CMOS device power supply Download PDFInfo
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- CN103746681A CN103746681A CN201310718846.4A CN201310718846A CN103746681A CN 103746681 A CN103746681 A CN 103746681A CN 201310718846 A CN201310718846 A CN 201310718846A CN 103746681 A CN103746681 A CN 103746681A
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Abstract
The invention discloses a power-on/power-down output tri-state control circuit for a CMOS device power supply. The tri-state control circuit comprises an MOS tube series resistance voltage-division circuit, a PMOS switching tube, and a shaping filtering circuit. According to the shaping filtering circuit, a PMOS transistor being equivalent to a capacitor is coupled to a grid terminal and a power supply terminal of the PMOS switching tube; an NMOS transistor being equivalent to a capacitor is coupled to a drain terminal and the power supply terminal of the PMOS switching tube; and a buffer circuit is connected to the drain terminal and a control circuit output terminal of the PMOS switching tube. According to the invention, when the power-on value or the power-down value of the power supply of the device is lower than the set threshold level, the device output port is controlled to be in a high impedance state, thereby maintaining accuracy of signal transmission at the device output bus and protecting the device from being damaged; and when the power-on value or the power-down value of the power supply of the device is higher than the set threshold level, the control circuit returns the control to the controlled device output port and thus the device can output an enabling signal OE to control three states of the output port.
Description
Technical field
The present invention relates to a kind of cmos device power supply power-on and power-off output tri-state control circuit, particularly a kind of device power source power on or lower electricity lower than arrange threshold level value time, control device output port keeps the circuit structure of high-impedance state, belongs to device control field.
Background technology
Along with the high speed development of IC industry, and the even more complex of applied environment is changeable, for the requirement that guarantees bus transfer signal integrity, becomes more and more important.The warm swap of veneer is an important application function in communication apparatus, in order to realize the warm swap of veneer, needs corresponding interface device to meet certain characteristic.Whether traditional interface device, under the pattern of power supply normal power supply, can be operated in high-impedance state by enable signal selector output, to guarantee the integrality of signal transmission in bus.If but under the pattern of the improper power supply of power supply, particularly in power supply electrifying or lower electric process, traditional interface device often normally control output end be operated in high-impedance state, the mistake upset while easily causing the transmission of signal in bus, the even damage of interface device.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of simple and practical control circuit structure is provided, can device power source power on or lower electric process in effective control device output operating state, when especially power supply electrifying or lower electricity are lower than the threshold level of a certain design, force device output port to keep high-impedance state, guarantee that the signal transmission in bus can maintain integrality under device power source non-normal working pattern.
Technical solution of the present invention is: the tri-state of device output end mouth is controlled by two control signals, one is control circuit of the present invention, one is output enable signal (Output Enable, OE), when power supply electrifying or lower electricity lower than set normal power supply threshold level time, control circuit output Q output signal 0 of the present invention, device output end mouth is now set to high-impedance state; When power supply electrifying or lower electricity higher than set normal power supply threshold level time, control circuit output Q output signal 1 of the present invention, if now OE is output as 1, device output end mouth is set to high-impedance state, if OE is output as 0, device output end mouth determines to be output as high or low by the internal logic circuit of device.
Control circuit of the present invention is a kind of cmos device power supply power-on and power-off output tri-state control circuit, comprises metal-oxide-semiconductor string resistance bleeder circuit, PMOS switching tube P5 and plastic filter circuit.Metal-oxide-semiconductor string resistance bleeder circuit is comprised of resistance R 3 and resistance R 4, one end of resistance R 3 is connected with one end of resistance R 4, and as the output of MOS string resistance bleeder circuit, be connected with the grid end of PMOS switching tube P5, the other end of resistance R 3 is connected with power source voltage Vcc, and the other end of resistance R 4 is connected to the ground.The source of PMOS switching tube P5 is all connected with power source voltage Vcc with substrate terminal, and drain terminal is connected with one end of resistance R 6, and is connected with the input of output buffer, and the other end of resistance R 6 is connected to the ground.Plastic filter circuit is by capacitor C 7, capacitor C 8 and output buffer form, one end of capacitor C 7 is connected with the grid end of PMOS switching tube P5, the other end is connected with power source voltage Vcc, one end of capacitor C 8 is connected with the drain terminal of PMOS switching tube P5, the other end is connected with power source voltage Vcc, and the input of output buffer is connected with the drain terminal of PMOS switching tube P5, and the output of output buffer is as the output output control signal of control circuit of the present invention.
Metal-oxide-semiconductor string resistance bleeder circuit, by the resistance value ratio of adjusting resistance R3 and resistance R 4, obtains the proportion divider value of power source voltage Vcc, and is connected to the grid end of PMOS switching tube P5 at node A, control conducting and the shutoff of PMOS switching tube P5.
In the process of power supply electrifying or lower electricity, when the voltage of output node A of metal-oxide-semiconductor string resistance bleeder circuit and the pressure reduction of power source voltage Vcc are during lower than the on state threshold voltage of PMOS switching tube P5, PMOS switching tube P5 is in off state, resistance R 6 is pulled low to zero potential by Node B, be that control circuit is output as 0 control signal, force device output end mouth to be set to high-impedance state, when the voltage of output node A of metal-oxide-semiconductor string resistance bleeder circuit and the pressure reduction of power source voltage Vcc are during higher than the on state threshold voltage of PMOS switching tube P5, PMOS switching tube P5 is in opening, because the conducting resistance of PMOS switching tube P5 design is less with respect to the resistance of resistance R 6, so the current potential of Node B keeps identical with power source voltage Vcc, be that control circuit is output as 1 control signal, now device can normally be worked under power source voltage Vcc power supply, power-on and power-off output tri-state control circuit discharges the control to device output end mouth, by device output enable signal OE, carried out the tri-state of control device output port, by selecting the PMOS switching tube P5 of different threshold voltages or selecting the resistance value ratio of different resistance R 3 and resistance R 4, can design the control circuit of different electrical power threshold voltage level, the level that makes control circuit output node Q so far overturns during threshold level with supply voltage power-on and power-off.
Capacitor C 7 in plastic filter circuit guarantees, when the fluctuation of non-power-on and power-off appears in power source voltage Vcc, can not cause Node B level to occur that wrong upset makes to export control signal mistake; Capacitor C 8 guaranteed when the moment of the P5 conducting of PMOS switching tube or shutoff, avoided because clock feed-through effect makes the larger burr of Node B output; Output buffer is after the level shaping of Node B, to send control circuit output Q of the present invention to, has improved driving force and the output impedance of control circuit output Q.
The present invention's advantage is compared to the prior art:
(1) the present invention designs a kind of control circuit of cmos device, by designing a supply voltage threshold level, when powering on, device power source voltage also do not reach this threshold level, or when under supply voltage, electricity is lower than this threshold level, device electricity shortage cannot normally be worked, this control circuit output signal 0, pressure makes device output end be set to high-impedance state, can not cause device power on or lower electric process in, bus signals is produced and disturbed, and the integrality that affects bus signal transmission even causes the damage of device.
(2) when device power source voltage powers on over this threshold level, or when under supply voltage, electricity is not also lower than this threshold level, supply voltage power supply can meet device and normally work, this control circuit output signal 1, now control circuit discharges the control to device output end mouth, is carried out the tri-state of control device output port by device output enable signal OE.
(3) under standard CMOS process, carry out emulation, control signal oscillogram simulation result from the final output of the present invention, the supply voltage threshold level that the present invention pre-sets is 2.1V, when supply voltage powers on while also not reaching under 2.1V or supply voltage electricity lower than 2.1V, device electricity shortage cannot normally be worked, this control circuit output signal 0, forces to make device output end be set to high-impedance state; When under supply voltage powers on over 2.1V or supply voltage, electricity is not also lower than 2.1V, supply voltage power supply can meet device and normally work, this control circuit output signal 1, now control circuit discharges the control to device output end mouth, is carried out the tri-state of control device output port by device output enable signal OE.
Accompanying drawing explanation
Fig. 1 is cmos device power supply power-on and power-off output tri-state control circuit structure chart of the present invention;
Fig. 2 be in cmos device power supply power-on and power-off of the present invention output tri-state control circuit Node B level with the variation simulation waveform figure of power supply power-on and power-off.
Fig. 3 is that cmos device power supply power-on and power-off output tri-state control circuit output Q level of the present invention is with the variation simulation waveform figure of power supply power-on and power-off.
Embodiment
As shown in Figure 1, be the structure chart of a kind of cmos device power supply of the present invention power-on and power-off output tri-state control circuit, comprise metal-oxide-semiconductor string resistance bleeder circuit 1, PMOS switching tube P5 and plastic filter circuit 2.Metal-oxide-semiconductor string resistance bleeder circuit 1 comprises resistance R 3 and resistance R 4, and plastic filter circuit 2 comprises capacitor C 7, capacitor C 8 and output buffer 9.
In the present invention, metal-oxide-semiconductor used is enhancement mode metal-oxide-semiconductor.
Device power source power on or the process of lower electricity in, metal-oxide-semiconductor string resistance bleeder circuit 1 is by the dividing potential drop of resistance R 3 and resistance R 4, at node A, obtain the proportion divider value of power source voltage Vcc, and be connected to the grid end of PMOS switching tube P5, control conducting and the shutoff of PMOS switching tube P5.When the voltage of output node A of metal-oxide-semiconductor string resistance bleeder circuit 1 and the pressure reduction of power source voltage Vcc are during lower than the on state threshold voltage of PMOS switching tube P5, PMOS switching tube P5 is in off state, resistance R 6 is pulled low to zero potential by Node B, be that control circuit is output as 0 control signal, force device output end mouth to be set to high-impedance state; When the voltage of output node A of metal-oxide-semiconductor string resistance bleeder circuit 1 and the pressure reduction of power source voltage Vcc are during higher than the on state threshold voltage of PMOS switching tube P5, PMOS switching tube P5 is in opening, because the conducting resistance of PMOS switching tube P5 design is less with respect to the resistance of resistance R 6, so the current potential of Node B keeps identical with power source voltage Vcc, be that control circuit is output as 1 control signal, now control circuit discharges the control to device output end mouth, is carried out the tri-state of control device output port by device output enable signal OE.Capacitor C 7 guarantees, when the fluctuation of non-power-on and power-off appears in power source voltage Vcc, can not cause Node B level to occur that wrong upset makes to export control signal mistake; Capacitor C 8 guaranteed when the moment of the P5 conducting of PMOS switching tube or shutoff, can not export larger burr because clock feed-through effect does not make Node B; The effect of output buffer 9 is after the level shaping of Node B, to send control circuit output Q to, has improved driving force and the output impedance of control circuit output Q.
As shown in Figure 2, for Node B level in cmos device power supply power-on and power-off output tri-state control circuit of the present invention is with the variation simulation waveform figure of power supply power-on and power-off, in figure, power source voltage Vcc normal power supply level is 3.3V, the threshold level value of power source voltage Vcc of design is 2.1V, and during actual design, this supply voltage threshold level value can recently redesign by choosing the PMOS switching tube P5 of different on state threshold voltages or different resistance R 3 and the resistance of resistance R 4.By simulation waveform Fig. 2, can find out, when power source voltage Vcc powers on while also not reaching 2.1V or lower electricity lower than 2.1V, Node B is low level, and control circuit is output as 0 control signal, forces device output end mouth to be set to high-impedance state; When power source voltage Vcc powers on while reaching 2.1V or lower electricity also not lower than 2.1V, the level of Node B keeps identical with power source voltage Vcc, be that control circuit is output as 1 control signal, now control circuit discharges the control to device output end mouth, is carried out the tri-state of control device output port by device output enable signal OE.
As shown in Figure 3, for cmos device power supply power-on and power-off of the present invention are exported the output Q level of tri-state control circuit with the variation simulation waveform figure of power supply power-on and power-off, by simulation waveform Fig. 3, can find out, the level of Node B is by after the shaping filter of plastic filter circuit 2, affected by ghost effect diminishes, make the wave form varies of control circuit output Q more precipitous, signal response upset is rapider.
The present invention has should be noted that at 2:
1, as shown in Figures 2 and 3, in power supply electrifying or lower electric process, when the value of power source voltage Vcc is very little, because metal-oxide-semiconductor in circuit exists ghost effect, so the output signal of control circuit has imperfect fluctuation, because of the amplitude that for this reason fluctuates with respect to supply voltage value, say very little, so can not affect the working condition of circuit integral body.
2, due to the existence of capacitor C 7 and capacitor C 8 in the plastic filter circuit 2 of control circuit, thus require power supply power on or lower electric speed can not be too fast.
The content not being described in detail in this specification belongs to professional and technical personnel in the field's known technology.
Claims (4)
1. a cmos device power supply power-on and power-off output tri-state control circuit, is characterized in that: comprise metal-oxide-semiconductor string resistance bleeder circuit (1), PMOS switching tube P5 and plastic filter circuit (2); Metal-oxide-semiconductor string resistance bleeder circuit (1) is comprised of resistance R 3 and resistance R 4, one end of resistance R 3 is connected with one end of resistance R 4, and as the output of MOS string resistance bleeder circuit (1), be connected with the grid end of PMOS switching tube P5, the other end of resistance R 3 is connected with power source voltage Vcc, and the other end of resistance R 4 is connected to the ground; The source of PMOS switching tube P5 is all connected with power source voltage Vcc with substrate terminal, and drain terminal is connected with one end of resistance R 6, and is connected with the input of output buffer (9), and the other end of resistance R 6 is connected to the ground; Plastic filter circuit (2) is by capacitor C 7, capacitor C 8 and output buffer (9) form, one end of capacitor C 7 is connected with the grid end of PMOS switching tube P5, the other end is connected with power source voltage Vcc, one end of capacitor C 8 is connected with the drain terminal of PMOS switching tube P5, the other end is connected with power source voltage Vcc, and the input of output buffer (9) is connected with the drain terminal of PMOS switching tube P5, and the output of output buffer (9) is as the output of control circuit of the present invention.
2. tri-state control circuit is exported in a kind of cmos device power supply power-on and power-off according to claim 1, it is characterized in that: metal-oxide-semiconductor string resistance bleeder circuit (1) is by the resistance value ratio of adjusting resistance R3 and resistance R 4, at node A, obtain the proportion divider value of power source voltage Vcc, and be connected to the grid end of PMOS switching tube P5, control conducting and the shutoff of PMOS switching tube P5.
3. tri-state control circuit is exported in a kind of cmos device power supply power-on and power-off according to claim 1, it is characterized in that: in the process of power supply electrifying or lower electricity, when the voltage of output node A of metal-oxide-semiconductor string resistance bleeder circuit (1) and the pressure reduction of power source voltage Vcc are during lower than the on state threshold voltage of PMOS switching tube P5, PMOS switching tube P5 is in off state, resistance R 6 is pulled low to zero potential by Node B, be that control circuit is output as 0 control signal, force device output end mouth to be set to high-impedance state, when the voltage of output node A of metal-oxide-semiconductor string resistance bleeder circuit (1) and the pressure reduction of power source voltage Vcc are during higher than the on state threshold voltage of PMOS switching tube P5, PMOS switching tube P5 is in opening, because the conducting resistance of PMOS switching tube P5 design is less with respect to the resistance of resistance R 6, so the current potential of Node B keeps identical with power source voltage Vcc, be that control circuit is output as 1 control signal, now device can normally be worked under power source voltage Vcc power supply, power-on and power-off output tri-state control circuit discharges the control to device output end mouth, by device output enable signal OE, carried out the tri-state of control device output port, by selecting the PMOS switching tube P5 of different threshold voltages or selecting the resistance value ratio of different resistance R 3 and resistance R 4, can design the control circuit of different electrical power threshold voltage level, the level that makes control circuit output node Q so far overturns during threshold level with supply voltage power-on and power-off.
4. tri-state control circuit is exported in a kind of cmos device power supply power-on and power-off according to claim 1, it is characterized in that: the capacitor C 7 in plastic filter circuit (2) guarantees, when the fluctuation of non-power-on and power-off appears in power source voltage Vcc, can not cause Node B level to occur that wrong upset makes to export control signal mistake; Capacitor C 8 guaranteed when the moment of the P5 conducting of PMOS switching tube or shutoff, avoided because clock feed-through effect makes the larger burr of Node B output; Output buffer (9) is after the level shaping of Node B, to send control circuit output Q of the present invention to, has improved driving force and the output impedance of control circuit output Q.
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| CN201310718846.4A CN103746681B (en) | 2013-12-24 | 2013-12-24 | A kind of upper and lower electricity output tri-state control circuit of cmos device power supply |
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| CN201310718846.4A CN103746681B (en) | 2013-12-24 | 2013-12-24 | A kind of upper and lower electricity output tri-state control circuit of cmos device power supply |
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| CN110277899A (en) * | 2018-03-16 | 2019-09-24 | 力智电子股份有限公司 | PWM controller and third state voltage generating method |
| CN111049513A (en) * | 2019-11-29 | 2020-04-21 | 北京时代民芯科技有限公司 | Rail-to-rail bus holding circuit with cold backup function |
| CN111698438A (en) * | 2020-06-11 | 2020-09-22 | 中国科学院长春光学精密机械与物理研究所 | TDI CCD power-on time sequence control circuit |
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| CN109217402A (en) * | 2017-07-07 | 2019-01-15 | 神讯电脑(昆山)有限公司 | The control circuit and its control method of cradle |
| CN110277899A (en) * | 2018-03-16 | 2019-09-24 | 力智电子股份有限公司 | PWM controller and third state voltage generating method |
| CN110277899B (en) * | 2018-03-16 | 2021-08-03 | 力智电子股份有限公司 | Pulse width modulation controller and third state voltage generation method |
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| CN111698438A (en) * | 2020-06-11 | 2020-09-22 | 中国科学院长春光学精密机械与物理研究所 | TDI CCD power-on time sequence control circuit |
| CN111698438B (en) * | 2020-06-11 | 2021-07-06 | 中国科学院长春光学精密机械与物理研究所 | TDI CCD power-on time sequence control circuit |
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