CN109004923A - Sequential control circuit - Google Patents
Sequential control circuit Download PDFInfo
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- CN109004923A CN109004923A CN201810986866.2A CN201810986866A CN109004923A CN 109004923 A CN109004923 A CN 109004923A CN 201810986866 A CN201810986866 A CN 201810986866A CN 109004923 A CN109004923 A CN 109004923A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Direct Current Feeding And Distribution (AREA)
Abstract
The present invention provides a kind of sequential control circuits, including discharge cell, upper electric unit, the first level-cell, second electrical level unit and third level-cell, described discharge cell one end connects reseting port, the other end connects the output end of upper electric unit, the output end of upper electric unit is also connected with the first level-cell, second electrical level unit and the third level-cell of cascade setting, and the output end of the third level-cell is by being connected to ground ground resistance.The beneficial effects of the present invention are: provide the I/O port control without CPU, the sequential control circuit of the low discrete component design of hardware cost, it is bad that this scheme neither will cause timing control, again the design cost of complete machine and the workload of software designer can be greatly reduced to avoid the awkward situation of hardware design I/O port shortage of resources.
Description
Technical field
The present invention relates to power supply control technical fields, refer in particular to a kind of sequential control circuit.
Background technique
POS machine is a kind of multi-functional terminal end, it be mounted on the franchised business of credit card and accept in site with computer
It is unified into network, can be achieved with electronic funds automatic account transfer, it has the function of to support consumption, pre-authorization, inquiry into balance and account transfer etc.,
It uses safely, quickly, reliably, is widely used in the places such as supermarket, chain store, hypermarket, restaurant.As mobile electron end
End can all be related to the operation of switching on and shutting down, then certainly will have the power-on and power-off of power supply, and the power-on and power-off timing of power supply sets electronics
It is even more important for extremely important more particularly to financial security POS machine for standby because in addition to function can it is impacted other than,
The security mechanism triggering of POS machine indispensability can be also involved, therefore often needs are very small when designing this partial circuit
The heart.
Such as Fig. 1, the scheme of existing sequential control circuit is all that timing IC is selected to control electricity respectively to control, or with CPU
Source enables foot, although these schemes are using having popularized, this kind of design cost is high, and design is complicated, and more CPU is needed to manage
Foot resource, more complicated software execute algorithm, thus design circuit and writing needed on software a large amount of time, manually at
This, and it is limited in system I/O port resource, and both schemes are difficult to realize in the limited situation in pcb board space.
Summary of the invention
The technical problems to be solved by the present invention are: provide a kind of I/O port without occupying CPU, hardware cost it is low when
Sequence control circuit.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention are as follows: a kind of sequential control circuit, including electric discharge
Unit, upper electric unit, the first level-cell, second electrical level unit and third level-cell, discharge cell one end connection are multiple
Bit port, the other end connect the output end of upper electric unit, and the output end of upper electric unit is also connected with the first level of cascade setting
Unit, second electrical level unit and third level-cell, the output end of the third level-cell is by being connected to ground ground resistance.
Further, the discharge cell includes first resistor and first capacitor, the input terminal of the discharge cell and institute
State one end connection of first resistor, the other end of first resistor connect with one end of the first capacitor, first capacitor it is another
End is connect with the output end of the discharge cell.
Further, the resistance value of the first resistor is 0 Ω, and the capacitance of first capacitor is 4.7UF.
Further, the first capacitor is NPO material capacitor.
Further, the upper electric unit includes second resistance and diode, the cathode of the diode and upper electric unit
Input terminal connection, diode anode connect with the output end of upper electric unit, the second resistance is parallel to the diode.
Further, the resistance value of the second resistance is 5.1K Ω, and the power of second resistance is 1/20W；The type of diode
Number be 1N4148WT.
Further, first level-cell includes 3rd resistor and the first electric level interface, and the one of the 3rd resistor
End is connect with the input terminal of first level-cell, and the other end of 3rd resistor is connect with the output end of the first level-cell,
First electric level interface is connect with the output end of the first level-cell.
Further, the second electrical level unit include the 4th resistance and second electrical level interface, the one of the 4th resistance
End is connect with the input terminal of the second electrical level unit, and the other end of the 4th resistance is connect with the output end of second electrical level unit,
The second electrical level interface is connect with the output end of second electrical level unit.
Further, the third level-cell include the 5th resistance and third electric level interface, the one of the 5th resistance
End is connect with the input terminal of the third level-cell, and the other end of the 5th resistance is connect with the output end of third level-cell,
The third electric level interface is connect with the output end of third level-cell.
Further, the resistance value of the 3rd resistor is 150K Ω, and the power of 3rd resistor is 1/20W；4th electricity
The resistance value of resistance is 27K Ω, and the power of the 4th resistance is 1/20W；The resistance value of 5th resistance is 10K Ω, the function of the 5th resistance
Rate is 1/20W；The resistance value to ground resistance is 120K Ω, and the power to ground resistance is 1/20W.
The beneficial effects of the present invention are: provide the I/O port control without CPU, the low discrete first device of hardware cost
The sequential control circuit of part design, it is bad that this scheme neither will cause timing control, and can be to avoid hardware design I/O port resource
The awkward situation of shortage, greatly reduces the design cost of complete machine and the workload of software designer.
Detailed description of the invention
Specific structure of the invention is described in detail with reference to the accompanying drawing:
Fig. 1 is the circuit structure diagram of control sequential in the prior art；
Fig. 2 is electrical block diagram of the invention；
Fig. 3 is electrifying timing sequence figure of the invention；
R1- first resistor；R2- second resistance；R3- 3rd resistor；The 4th resistance of R4-；The 5th resistance of R5-；R6- is electric over the ground
Resistance；
D1- diode；C1- first capacitor.
Specific embodiment
In order to describe the technical content, the structural feature, the achieved object and the effect of this invention in detail, below in conjunction with embodiment
And attached drawing is cooperated to be explained in detail.
Embodiment 1
Referring to Fig. 2, a kind of sequential control circuit, including discharge cell, upper electric unit, the first level-cell, the second electricity
Flat unit and third level-cell, described discharge cell one end connect reseting port, and the other end connects the output end of upper electric unit,
The output end of upper electric unit is also connected with the first level-cell, second electrical level unit and the third level-cell of cascade setting, institute
The output end of third level-cell is stated by being connected to ground to ground resistance.
The discharge cell is used to slow down the power-up speeds of VCC-1, VCC-2 and VCC-3.The discharge cell includes first
Resistance R1 and first capacitor C1, the input terminal of the discharge cell are connect with one end of the first resistor R1, first resistor R1
The other end connect with one end of the first capacitor C1, the output end of the other end of first capacitor C1 and the discharge cell connects
It connects.
The upper electric unit is used to provide high level for VCC-1, VCC-2 and VCC-3.The upper electric unit includes the second electricity
Resistance R2 and diode D1, the cathode of the diode D1 are connect with the input terminal of upper electric unit, diode D1 it is positive with power on
The output end of unit connects, and the second resistance R1 is parallel to the diode D1.
First level-cell is used to provide high level for VCC-1, when VCC-1 is high level, for being in system
The 1.5V power supply of Kernel/QVDD power supply starts to power.First level-cell includes that 3rd resistor R3 and the first level connect
Mouthful, one end of the 3rd resistor R3 connect with the input terminal of first level-cell, the other end of 3rd resistor R3 and the
The output end of one level-cell connects, and first electric level interface is connect with the output end of the first level-cell.
The second electrical level unit is used to provide high level for VCC-2, when VCC-2 is high level, for being in system
The 3.3V power supply of CPU/NAND/MCU power supply and the 1.8V power supply for powering for DDR start to power.The second electrical level unit
Including the 4th resistance R4 and second electrical level interface, one end of the 4th resistance R4 and the input terminal of the second electrical level unit connect
It connects, the other end of the 4th resistance R4 is connect with the output end of second electrical level unit, the second electrical level interface and second electrical level list
The output end connection of member.
The third level-cell is used to provide high level for VCC-3, when VCC-3 is high level, for being in system
The 3.3V power supply of REF/Fuse power supply and the 1.5V power supply for powering for PLL start to power.The third level-cell includes
One end of 5th resistance R5 and third electric level interface, the 5th resistance R5 is connect with the input terminal of the third level-cell,
The other end of 5th resistance R5 is connect with the output end of third level-cell, the third electric level interface and third level-cell
Output end connection.
As can be seen from the above description, the beneficial effects of the present invention are: provide the I/O port control without CPU, hardware
The sequential control circuit of discrete component design at low cost, it is bad that this scheme neither will cause timing control, and can be to avoid
The awkward situation of hardware design I/O port shortage of resources greatly reduces the design cost of complete machine and the workload of software designer.
Embodiment 2
On the basis of embodiment 1, the first capacitor C1 is NPO material capacitor.
In the present embodiment, NPO capacitor is one of capacitance and the most stable of capacitor of dielectric loss.In temperature from -55
Volume change is 0 ± 30ppm/ DEG C when DEG C to+125 DEG C, and the variation of capacitance with frequencies is less than ± 0.3 Δ C.The drift of NPO capacitor
It moves or lag is less than ± 0.05%, relatively larger than being negligible for ± 2% thin-film capacitor.Its typical capacity
The variation in relative usage service life is less than ± 0.1%.
Be conducive to the reliability of this sequential control circuit using NPO capacitor.
Embodiment 3
On the basis of embodiment 2, the resistance value of the first resistor R1 is 0 Ω, and the capacitance of first capacitor C1 is 4.7UF；
The resistance value of the second resistance R2 is 5.1K Ω, and the power of second resistance R2 is 1/20W；The model of diode D1
1N4148WT；The resistance value of the 3rd resistor R3 is 150K Ω, and the power of 3rd resistor R3 is 1/20W；The 4th resistance R4
Resistance value be 27K Ω, the power of the 4th resistance R4 is 1/20W；The resistance value of the 5th resistance R5 is 10K Ω, the 5th resistance R5
Power be 1/20W；The resistance value to ground resistance R6 is 120K Ω, and the power to ground resistance R6 is 1/20W.
In the present embodiment, the resistance, capacitor and diode of appropriate size are selected, when can increase the reliability of circuit and realization
Sequence is precisely controlled.
Referring to Fig. 3, circuit powered on moment, reset signal RESET keeps low level 100ms or so, and VCC starts to supply
3.3V, the characteristic that cannot be mutated using capacitor both ends potential difference, the potential of VCC-1 will be slow rising, and the rise time, T was by circuit
Discharge cell R1 and C1 determine,
T=R1C1ln [(U-U0)/U])
Due to series relationship, it is easy to find out that the sequencing for reaching high level is followed successively by VCC-1, VCC-2 and VCC-3.
Be thus controlled the electrifying timing sequence of several power supplys, compared with traditional design mode, this circuit be more convenient for design, more save at
This, circuit structure is simple, and product reliability can be improved.
Among the above, first, second ... only represents the differentiation of its title, do not represent they significance level and position have it is assorted
It is different.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant skills
Art field, is included within the scope of the present invention.
Claims (10)
1. a kind of sequential control circuit, it is characterised in that: including discharge cell, upper electric unit, the first level-cell, second electrical level
Unit and third level-cell, described discharge cell one end connect reseting port, and the other end connects the output end of upper electric unit, on
The output end of electric unit is also connected with the first level-cell, second electrical level unit and the third level-cell of cascade setting, described
The output end of third level-cell is by being connected to ground ground resistance.
2. sequential control circuit as described in claim 1, it is characterised in that: the discharge cell includes first resistor and first
Capacitor, the input terminal of the discharge cell are connect with one end of the first resistor, the other end of first resistor and described first
One end of capacitor connects, and the other end of first capacitor is connect with the output end of the discharge cell.
3. sequential control circuit as claimed in claim 2, it is characterised in that: the resistance value of the first resistor is 0 Ω, the first electricity
The capacitance of appearance is 4.7UF.
4. sequential control circuit as claimed in claim 3, it is characterised in that: the first capacitor is NPO material capacitor.
5. sequential control circuit as claimed in claim 4, it is characterised in that: the upper electric unit includes second resistance and two poles
Pipe, the cathode of the diode are connect with the input terminal of upper electric unit, and the anode of diode is connect with the output end of upper electric unit,
The second resistance is parallel to the diode.
6. sequential control circuit as claimed in claim 5, it is characterised in that: the resistance value of the second resistance is 5.1K Ω, the
The power of two resistance is 1/20W；The model 1N4148WT of diode.
7. sequential control circuit as claimed in claim 6, it is characterised in that: first level-cell include 3rd resistor and
First electric level interface, one end of the 3rd resistor are connect with the input terminal of first level-cell, 3rd resistor it is another
End is connect with the output end of the first level-cell, and first electric level interface is connect with the output end of the first level-cell.
8. sequential control circuit as claimed in claim 7, it is characterised in that: the second electrical level unit include the 4th resistance and
One end of second electrical level interface, the 4th resistance is connect with the input terminal of the second electrical level unit, the 4th resistance it is another
End is connect with the output end of second electrical level unit, and the second electrical level interface is connect with the output end of second electrical level unit.
9. sequential control circuit as claimed in claim 8, it is characterised in that: the third level-cell include the 5th resistance and
One end of third electric level interface, the 5th resistance is connect with the input terminal of the third level-cell, the 5th resistance it is another
End is connect with the output end of third level-cell, and the third electric level interface is connect with the output end of third level-cell.
10. sequential control circuit as claimed in claim 9, it is characterised in that: the resistance value of the 3rd resistor is 150K Ω, the
The power of three resistance is 1/20W；The resistance value of 4th resistance is 27K Ω, and the power of the 4th resistance is 1/20W；Described 5th
The resistance value of resistance is 10K Ω, and the power of the 5th resistance is 1/20W；The resistance value to ground resistance is 120K Ω, to ground resistance
Power is 1/20W.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810986866.2A CN109004923A (en) | 2018-08-28 | 2018-08-28 | Sequential control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810986866.2A CN109004923A (en) | 2018-08-28 | 2018-08-28 | Sequential control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109004923A true CN109004923A (en) | 2018-12-14 |
Family
ID=64593997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810986866.2A Pending CN109004923A (en) | 2018-08-28 | 2018-08-28 | Sequential control circuit |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1606784A (en) * | 2001-12-18 | 2005-04-13 | 英特尔公司 | Flash device operating from a power-supply-in-package (psip) or from a power supply on chip |
| US20050140404A1 (en) * | 2003-12-30 | 2005-06-30 | Chang-Ho Do | Power-up circuit in semiconductor memory device |
| CN103604975A (en) * | 2013-11-18 | 2014-02-26 | 同济大学 | An anti-interference low-voltage detection circuit |
| CN103746681A (en) * | 2013-12-24 | 2014-04-23 | 北京时代民芯科技有限公司 | Power-on/power-down output tri-state control circuit for CMOS device power supply |
| CN103869856A (en) * | 2012-12-11 | 2014-06-18 | 中兴通讯股份有限公司 | Multi-voltage time sequence control circuit |
| CN104238627A (en) * | 2014-09-05 | 2014-12-24 | 浪潮电子信息产业股份有限公司 | Method for realizing server power-on/off sequential control by using hardware circuit |
| CN204578503U (en) * | 2015-05-29 | 2015-08-19 | 中国航空无线电电子研究所 | A kind of power supply lagging circuit |
| CN105320040A (en) * | 2015-11-20 | 2016-02-10 | 上海斐讯数据通信技术有限公司 | Power-on sequence control circuit, power-on sequence control method, control device and electronic terminal |
-
2018
- 2018-08-28 CN CN201810986866.2A patent/CN109004923A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1606784A (en) * | 2001-12-18 | 2005-04-13 | 英特尔公司 | Flash device operating from a power-supply-in-package (psip) or from a power supply on chip |
| US20050140404A1 (en) * | 2003-12-30 | 2005-06-30 | Chang-Ho Do | Power-up circuit in semiconductor memory device |
| CN103869856A (en) * | 2012-12-11 | 2014-06-18 | 中兴通讯股份有限公司 | Multi-voltage time sequence control circuit |
| CN103604975A (en) * | 2013-11-18 | 2014-02-26 | 同济大学 | An anti-interference low-voltage detection circuit |
| CN103746681A (en) * | 2013-12-24 | 2014-04-23 | 北京时代民芯科技有限公司 | Power-on/power-down output tri-state control circuit for CMOS device power supply |
| CN104238627A (en) * | 2014-09-05 | 2014-12-24 | 浪潮电子信息产业股份有限公司 | Method for realizing server power-on/off sequential control by using hardware circuit |
| CN204578503U (en) * | 2015-05-29 | 2015-08-19 | 中国航空无线电电子研究所 | A kind of power supply lagging circuit |
| CN105320040A (en) * | 2015-11-20 | 2016-02-10 | 上海斐讯数据通信技术有限公司 | Power-on sequence control circuit, power-on sequence control method, control device and electronic terminal |
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| PB01 | Publication | ||
| PB01 | Publication | ||
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Application publication date: 20181214 |