CN204578503U - A kind of power supply lagging circuit - Google Patents
A kind of power supply lagging circuit Download PDFInfo
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- CN204578503U CN204578503U CN201520358307.9U CN201520358307U CN204578503U CN 204578503 U CN204578503 U CN 204578503U CN 201520358307 U CN201520358307 U CN 201520358307U CN 204578503 U CN204578503 U CN 204578503U
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Abstract
A kind of power supply lagging circuit, belongs to electronic engineering field.A kind of power supply lagging circuit, comprise clock circuit, MOSFET pipe, power supply supply Vcc and chip power supply Vdd, the grid G of MOSFET pipe is connected to the transmit control signal clock circuit of CTL of MOSFET pipe, the drain D series chip power supply supply Vdd of MOSFET pipe, power supply supply Vcc powers to power supply lagging circuit, and the drain D of described MOSFET pipe and source S supply Vcc and chip power at power supply and supply between Vdd and construct a Grounding.The utility model can meet the application needs of most of occasion, applied widely, and restriction is few, makes the use of power supply lagging circuit more convenient.
Description
Technical field
The utility model relates to a kind of power supply lagging circuit, and it comprises N-channel MOS FET type power supply lagging circuit and P channel mosfet type power supply lagging circuit, belongs to electronic engineering field.
Background technology
Chip is requisite components and parts in Electronic Design, major part chip internal has electrify restoration circuit, when supply power voltage is greater than threshold voltage VTT, reset circuit carries out initialization (reset) operation, and reset circuit initialization generally needs clock to drive, therefore clock supply needs to supply with power supply to match, in general, before supply power voltage arrives VTT, the clock signal guarantee electrification reset that chip need receive at least 3 cycles normally carries out, and chip internal electrification reset sequential as shown in Figure 1.And clock supply is generally produced by clock circuit, on same circuit board, clock circuit and chip are generally powered by same power supply (power supply circuits), Fig. 2 is shown in by its schematic diagram, from this figure, because clock circuit has processing delay, therefore the supply of the power supply of chip will supply early than clock, and this just needs to increase power supply lagging circuit by delayed for the power supply of chip supply, and the processing delay of clock circuit need be greater than lag time, as shown in Figure 3.
Common power supply lagging circuit method for designing uses resistance capacitance to form charge-discharge circuit, using the charging interval of electric capacity as delayed time delay, circuit theory is shown in Fig. 4, t at any time, there is following formula: Vdd=Vcc × [1-exp (-t/RC)], can draw as t=3RC from this formula, Vdd=0.95Vcc ≈ VTT, namely need the time through 3RC, the supply power voltage of chip power just reaches threshold voltage VTT.
Another conventional power supply lagging circuit method for designing adopts the circuit be made up of relay to realize, circuit theory is shown in Fig. 5, by default, it is INA1 → OUTA that the input and output of relay are closed, INB1 → OUTB, now Vdd=0, by the input and output relation of the control break relay of external signal, such as, clock circuit is after normal operation, it can be allowed to send the control signal CTL of a high level, relay input and output relation under the control of CTL becomes INA2 → OUTA, INB2 → OUTB, such Vdd=Vcc, namely after ensure that clock supply is normal, the power supply just normal supply of chip.
Although the capacitor type power supply lagging circuit often formed with resistance capacitance or the relay-type power supply lagging circuit that formed with relay are to realize the delayed supply of power supply, but these two kinds of power supply lagging circuit designs can not meet the application demand of a lot of occasion, the lag time of such as capacitor type power supply lagging circuit is t=3RC, the precedence relationship that it is not determined with the time delay T of clock circuit, in order to make t>T, the R of large resistance value and the C of bulky capacitor value can only be selected as far as possible, and the value of R when too senior general causes actual use because pressure drop causes too greatly Vdd can not reach chip minimum value, the value of C too senior general makes the load capacitance of Vcc very large, be unfavorable for the safe handling of Vcc, although relay can ensure that in sequencing control the clock supply of chip is prior to power supply supply, the encapsulation volume of relay is comparatively large, and has level demand to control signal CTL, can not meet some special applications.
Utility model content
The purpose of this utility model is to provide a kind of power supply lagging circuit, wherein contain MOSFET pipe, MOSFET pipe is field effect transistor, a slice N-channel MOS FET pipe or a slice P channel mosfet pipe is used to build power supply supply lagging circuit, make this power supply lagging circuit can meet the application needs of most of occasion, applied widely, restriction is few, makes the use of power supply lagging circuit more convenient.
Realize above-mentioned purpose, the technical scheme that the utility model is taked is as follows:
A kind of power supply lagging circuit, comprise clock circuit, MOSFET pipe, power supply supply Vcc and chip power supply Vdd, the grid G of MOSFET pipe is connected to the transmit control signal clock circuit of CTL of MOSFET pipe, the drain D series chip power supply supply Vdd of MOSFET pipe, power supply supply Vcc powers to power supply lagging circuit, and the drain D of described MOSFET pipe and source S supply Vcc and chip power at power supply and supply between Vdd and construct a Grounding.
Further, described power supply lagging circuit comprises N-channel MOS FET type power supply lagging circuit and P channel mosfet type power supply lagging circuit.
Further, when described power supply lagging circuit is N-channel MOS FET type power supply lagging circuit, also comprise resistance R, the resistance R playing dividing potential drop effect is connected in the middle of the drain D of power supply supply Vcc and MOSFET pipe, the source S ground connection of MOSFET pipe, when the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is high level, MOSFET pipe is opening, and chip is in non-power-up state; When the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is low level, MOSFET pipe is full pinch off state, and chip is in power-up state.
Further, when described power supply lagging circuit is P channel mosfet type power supply lagging circuit, source S and the power supply of MOSFET pipe supply Vcc and connect, when the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is high level, MOSFET pipe is full pinch off state, and chip is in non-power-up state; When the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is low level, MOSFET pipe is opening, and chip is in power-up state.
The utility model has following beneficial effect:
The utility model proposes a kind of MOSFET pipe to realize the device of the delayed supply of power supply.It realize simple, reliable and stable, facilitate easy-to-use, simultaneously because of it, to have cost low, characteristic applied widely, therefore this device generalization is strong, has significant economic benefit.
Accompanying drawing explanation
Fig. 1 is chip electrifying timing sequence figure;
Fig. 2 is board clock, power supply supply schematic diagram;
Fig. 3 is board clock after improving, power supply supply schematic diagram;
Fig. 4 is capacitor type power supply lagging circuit design drawing;
Fig. 5 is relay-type power supply lagging circuit design drawing;
Fig. 6 is N-channel MOS FET type power supply lagging circuit design drawing;
Fig. 7 is P channel mosfet type power supply lagging circuit design drawing;
Fig. 8 is modified model N-channel MOS FET type power supply lagging circuit design drawing;
Fig. 9 is modified model P channel mosfet type power supply lagging circuit design drawing.
Embodiment
Specific embodiment of the utility model is as follows:
As shown in Fig. 6 ~ Fig. 7, a kind of power supply lagging circuit, comprise clock circuit, MOSFET pipe, power supply supply Vcc and chip power supply Vdd, the grid G of MOSFET pipe is connected to the transmit control signal clock circuit of CTL of MOSFET pipe, the drain D series chip power supply supply Vdd of MOSFET pipe, power supply supply Vcc powers to power supply lagging circuit, and the drain D of described MOSFET pipe and source S supply Vcc and chip power at power supply and supply between Vdd and construct a Grounding.
Further, described power supply lagging circuit comprises N-channel MOS FET type power supply lagging circuit and P channel mosfet type power supply lagging circuit.
As shown in Figure 6, when described power supply lagging circuit is N-channel MOS FET type power supply lagging circuit, also comprise resistance R, the resistance R playing dividing potential drop effect is connected in the middle of the drain D of power supply supply Vcc and MOSFET pipe, the source S ground connection of MOSFET pipe, when the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is high level, MOSFET pipe is opening, and chip is in non-power-up state; When the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is low level, MOSFET pipe is full pinch off state, and chip is in power-up state.
As shown in Figure 8, can add a resistance R1 again on former N-channel MOS FET type power supply lagging circuit, make resistance R1 one end series-connection power supplies supply Vcc, the other end connects the grid G of clock circuit and MOSFET pipe simultaneously.Under default situations, control signal CTL is the grid G that high level is added in MOSFET, can pass through resistance R1 (as 10k ohm) and be pulled to Vcc, and now MOSFET pipe is opened, and forms conduction N raceway groove, Vdd=V between drain D and source S
dS, because of V
dSgeneral less (as the V of 2N7002
dS≈ 2V), do not reach the minimum of chip operation, so time chip be in non-power-up state, after the clock of clock circuit to chip has supplied, just an exportable low level is to the grid G of MOSFET pipe, MOSFET pipe is made to be in full pinch off state, conduction N raceway groove between drain D and source S disappears, Vdd=Vcc-R × i (electric current of i needed for chip operation), in order to make Vdd>=chip operation minimum, the value of resistance R can not be too large, can according to actual conditions determination resistance, such chip can normally power on, the clock supply meeting chip supplies early than power supply, chip electrification reset can normally carry out.
External power source, after port input, through the dividing potential drop of resistance R, receives the two ends of MOSFET pipe and chip supply power.The effect of resistance R is: be 1. used for avoiding the excessive damage causing MOSFET of voltage; 2. be used for ensureing that MOSFET pipe is when opening, the V formed
dSmuch smaller than the operating voltage of chip.
As shown in Figure 7, further, when described power supply lagging circuit is P channel mosfet type power supply lagging circuit, source S and the power supply of MOSFET pipe supply Vcc and connect, when the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is high level, MOSFET pipe is full pinch off state, and chip is in non-power-up state; When the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is low level, MOSFET pipe is opening, and chip is in power-up state.
As shown in Figure 9, can add a resistance R1 again on former P channel mosfet type power supply lagging circuit, make resistance R1 one end series-connection power supplies supply Vcc, the other end connects the grid G of clock circuit and MOSFET pipe simultaneously.Under default situations, control signal CTL is the grid G that high level is added in MOSFET pipe, resistance R1 (as 10k ohm) can be passed through and be pulled to Vcc, now MOSFET pipe is in full pinch off state, conduction P raceway groove between drain D and source S disappears, Vdd=0, now chip is in non-power-up state, after the clock of clock circuit to chip has supplied, just an exportable low level is to the grid G of MOSFET pipe, MOSFET pipe is opened, conduction P raceway groove is formed between drain D and source S, Vdd=Vcc-VSD, because the general comparatively I of VSD is ignored (the VSD ≈ 10mV as NDS356AP), therefore Vdd ≈ Vcc, such chip can normally power on, the clock supply meeting chip supplies early than power supply, chip electrification reset can normally carry out.
The effect increasing resistance R1 is: can the control signal CTL that exports of simplifier clock circuit, and when not having resistance R1, CTL exports need have low and high level to change, and when there being resistance R1, CTL only needs output low level.
Claims (4)
1. a power supply lagging circuit, comprise clock circuit, MOSFET pipe, power supply supply Vcc and chip power supply Vdd, it is characterized in that: connect the grid G of MOSFET pipe to the transmit control signal clock circuit of CTL of MOSFET pipe, the drain D series chip power supply supply Vdd of MOSFET pipe, power supply supply Vcc powers to power supply lagging circuit, and the drain D of described MOSFET pipe and source S supply Vcc and chip power at power supply and supply between Vdd and construct a Grounding.
2. a kind of power supply lagging circuit according to claim 1, is characterized in that: described power supply lagging circuit comprises two types, is respectively N-channel MOS FET type power supply lagging circuit and P channel mosfet type power supply lagging circuit.
3. a kind of power supply lagging circuit according to claim 2, it is characterized in that: when described power supply lagging circuit is N-channel MOS FET type power supply lagging circuit, also comprise resistance R, the resistance R playing dividing potential drop effect is connected in the middle of the drain D of power supply supply Vcc and MOSFET pipe, the source S ground connection of MOSFET pipe, when the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is high level, MOSFET pipe is opening, and chip is in non-power-up state; When the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is low level, MOSFET pipe is full pinch off state, and chip is in power-up state.
4. a kind of power supply lagging circuit according to claim 2, it is characterized in that: when described power supply lagging circuit is P channel mosfet type power supply lagging circuit, source S and the power supply of MOSFET pipe supply Vcc and connect, when the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is high level, MOSFET pipe is full pinch off state, and chip is in non-power-up state; When the control signal CTL that clock circuit exports to the grid G of MOSFET pipe is low level, MOSFET pipe is opening, and chip is in power-up state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520358307.9U CN204578503U (en) | 2015-05-29 | 2015-05-29 | A kind of power supply lagging circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520358307.9U CN204578503U (en) | 2015-05-29 | 2015-05-29 | A kind of power supply lagging circuit |
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| CN204578503U true CN204578503U (en) | 2015-08-19 |
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| CN201520358307.9U Active CN204578503U (en) | 2015-05-29 | 2015-05-29 | A kind of power supply lagging circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109004923A (en) * | 2018-08-28 | 2018-12-14 | 深圳市新国都技术股份有限公司 | Sequential control circuit |
-
2015
- 2015-05-29 CN CN201520358307.9U patent/CN204578503U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109004923A (en) * | 2018-08-28 | 2018-12-14 | 深圳市新国都技术股份有限公司 | Sequential control circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information |
Inventor after: Zhang Shengyan Inventor after: Liu Xiaokang Inventor after: Hu Shuixian Inventor after: Tong Xin Inventor before: Zhang Shengyan |
|
| COR | Change of bibliographic data |