CN204578503U - A kind of power supply lagging circuit - Google Patents

Abstract

A kind of power supply lagging circuit, belongs to electronic engineering field.A kind of power supply lagging circuit, comprise clock circuit, MOSFET pipe, power supply supply Vcc and chip power supply Vdd, the grid G of MOSFET pipe is connected to the transmit control signal clock circuit of CTL of MOSFET pipe, the drain D series chip power supply supply Vdd of MOSFET pipe, power supply supply Vcc powers to power supply lagging circuit, and the drain D of described MOSFET pipe and source S supply Vcc and chip power at power supply and supply between Vdd and construct a Grounding.The utility model can meet the application needs of most of occasion, applied widely, and restriction is few, makes the use of power supply lagging circuit more convenient.

Description

A power hysteresis circuit

technical field

The utility model relates to a power supply hysteresis circuit, which comprises an N-channel MOSFET type power supply hysteresis circuit and a P-channel MOSFET type power supply hysteresis circuit, belonging to the field of electronic engineering.

Background technique

The chip is an indispensable component in electronic design. Most chips have a power-on reset circuit inside. When the power supply voltage is greater than the threshold voltage VTT, the reset circuit performs initialization (reset) operation, and the initialization of the reset circuit generally requires a clock to drive. Therefore, the clock supply needs to match the power supply. Generally speaking, before the power supply voltage reaches VTT, the chip needs to receive at least 3 cycles of the clock signal to ensure the normal power-on reset. The internal power-on reset sequence of the chip is shown in Figure 1. Show. The clock supply is generally generated by the clock circuit. On the same circuit board, the clock circuit and the chip are generally powered by the same power supply (power supply circuit). , so the power supply of the chip is earlier than the clock supply, and this requires adding a power hysteresis circuit to delay the power supply of the chip, and the lag time must be greater than the processing delay of the clock circuit, as shown in Figure 3.

A common power supply hysteresis circuit design method is to use resistors and capacitors to form a charging and discharging circuit, and the charging time of the capacitor is used as the lag time delay. The circuit principle is shown in Figure 4. At any time t, there is the following formula: Vdd=Vcc×[1-exp( -t/RC)], it can be drawn from this formula that when t=3RC, Vdd=0.95Vcc≈VTT, that is, it takes 3RC for the supply voltage of the chip power supply to reach the threshold voltage VTT.

Another commonly used power hysteresis circuit design method is to use a circuit composed of relays. The circuit principle is shown in Figure 5. In the default state, the relationship between the input and output of the relay is INA1→OUTA, INB1→OUTB. At this time, Vdd= 0, the relationship between the input and output of the relay can be changed through the control of external signals. For example, after the clock circuit is in normal operation, it can send a high-level control signal CTL, and the relationship between the input and output of the relay under the control of CTL becomes INA2→OUTA, INB2→OUTB, so that Vdd=Vcc, that is, after the clock supply is guaranteed, the power supply of the chip is normally supplied.

Although a capacitive power hysteresis circuit composed of resistors and capacitors or a relay-type power hysteresis circuit composed of relays are often used to realize the hysteresis supply of power, these two power hysteresis circuit designs cannot meet the application requirements of many occasions, such as capacitive power hysteresis The delay time of the circuit is t=3RC, which has no definite relationship with the time delay T of the clock circuit. In order to make t>T, we can only choose R with a large resistance value and C with a large capacitance value as much as possible, and the value of R is too large. It will lead to the fact that Vdd cannot reach the minimum working voltage value of the chip due to too large voltage drop in actual use. If the value of C is too large, the load capacitance of Vcc will be large, which is not conducive to the safe use of Vcc; The clock supply is prior to the power supply, but the packaging volume of the relay is relatively large, and there is a level requirement for the control signal CTL, which cannot meet some special applications.

Utility model content

The purpose of this utility model is to provide a power supply hysteresis circuit, which includes a MOSFET tube, and the MOSFET tube is a field effect tube. A piece of N-channel MOSFET tube or a piece of P-channel MOSFET tube is used to construct a power supply hysteresis circuit, so that the power supply lags The circuit can meet the application needs of most occasions, has a wide range of applications, and has few restrictions, so that the use of the power hysteresis circuit is more convenient.

Realize above-mentioned purpose, the technical scheme that the utility model takes is as follows:

A power hysteresis circuit, including a clock circuit, a MOSFET tube, a power supply Vcc and a chip power supply Vdd, the clock circuit that sends a control signal CTL to the MOSFET tube is connected to the gate G of the MOSFET tube, and the drain D of the MOSFET tube is connected in series to the chip power supply Vdd, the power supply Vcc supplies power to the power hysteresis circuit, and the drain D and source S of the MOSFET tube construct a grounding channel between the power supply Vcc and the chip power supply Vdd.

Further, the power hysteresis circuit includes an N-channel MOSFET power hysteresis circuit and a P-channel MOSFET power hysteresis circuit.

Further, when the power supply hysteresis circuit is an N-channel MOSFET type power supply hysteresis circuit, it also includes a resistor R, and the resistor R acting as a voltage divider is connected in series between the power supply Vcc and the drain D of the MOSFET tube, and the source of the MOSFET tube When the pole S is grounded, when the control signal CTL output by the clock circuit to the gate G of the MOSFET is high, the MOSFET is turned on and the chip is in an unpowered state; when the clock circuit outputs the control signal to the gate G of the MOSFET When the signal CTL is at a low level, the MOSFET tube is fully pinched off, and the chip is in a power-on state.

Further, when the power hysteresis circuit is a P-channel MOSFET type power hysteresis circuit, the source S of the MOSFET is connected in series with the power supply Vcc, and when the control signal CTL output by the clock circuit to the gate G of the MOSFET is a high voltage Normally, the MOSFET is fully pinched off and the chip is not powered on; when the control signal CTL output from the clock circuit to the gate G of the MOSFET is low, the MOSFET is turned on and the chip is powered on.

The utility model has the following beneficial effects:

The utility model proposes a device which uses a MOSFET tube to realize the lagging power supply. It is simple, stable and reliable, convenient and easy to use, and because of its low cost and wide application range, the device has strong popularization and significant economic benefits.

Description of drawings

Figure 1 is a timing diagram of chip power-on;

Figure 2 is a schematic diagram of circuit board clock and power supply;

Figure 3 is a schematic diagram of the improved circuit board clock and power supply;

Fig. 4 is a design diagram of a capacitive power supply hysteresis circuit;

Fig. 5 is a design diagram of a relay type power supply hysteresis circuit;

Figure 6 is a design diagram of an N-channel MOSFET type power supply hysteresis circuit;

Figure 7 is a design diagram of a P-channel MOSFET type power supply hysteresis circuit;

Figure 8 is a design diagram of an improved N-channel MOSFET power supply hysteresis circuit;

Figure 9 is a design diagram of an improved P-channel MOSFET power supply hysteresis circuit.

Detailed ways

The specific embodiment of the utility model is as follows:

As shown in Figures 6 to 7, a power hysteresis circuit includes a clock circuit, a MOSFET, a power supply Vcc, and a chip power supply Vdd. The clock circuit that sends a control signal CTL to the MOSFET is connected to the gate G of the MOSFET, and the MOSFET The drain D of the tube is connected in series with the chip power supply Vdd, and the power supply Vcc supplies power to the power hysteresis circuit. The drain D and source S of the MOSFET tube build a grounding channel between the power supply Vcc and the chip power supply Vdd.

Further, the power hysteresis circuit includes an N-channel MOSFET power hysteresis circuit and a P-channel MOSFET power hysteresis circuit.

As shown in Figure 6, when the power hysteresis circuit is an N-channel MOSFET type power hysteresis circuit, it also includes a resistor R, and the resistor R that acts as a voltage divider is connected in series between the power supply Vcc and the drain D of the MOSFET tube. The source S of the tube is grounded. When the control signal CTL output by the clock circuit to the gate G of the MOSFET tube is at a high level, the MOSFET tube is turned on and the chip is in an unpowered state; when the clock circuit outputs to the gate G of the MOSFET tube When the control signal CTL of G is at a low level, the MOSFET tube is in a pinch-off state, and the chip is in a power-on state.

As shown in Figure 8, a resistor R1 can be added to the original N-channel MOSFET power hysteresis circuit, so that one end of the resistor R1 is connected in series with the power supply Vcc, and the other end is connected to the clock circuit and the gate G of the MOSFET. By default, the control signal CTL is at a high level and applied to the gate G of the MOSFET, which can be pulled up to Vcc through a resistor R1 (such as 10k ohms). N-channel, Vdd=V _DS , because V _DS is generally small (such as 2N7002’s V _DS ≈ 2V), it cannot reach the minimum working voltage of the chip, so the chip is not powered on at this time, when the clock circuit is on the chip After the clock supply is completed, a low level can be output to the gate G of the MOSFET, so that the MOSFET is in a full pinch-off state, and the conductive N channel between the drain D and the source S disappears, Vdd=Vcc-R ×i (i is the current required for the chip to work), in order to make Vdd ≥ the minimum working voltage of the chip, the value of the resistor R should not be too large, and the resistance value can be determined according to the actual situation, so that the chip can be powered on normally to meet the clock speed of the chip The supply is earlier than the power supply, and the power-on reset of the chip can be performed normally.

After the external power is input from the port, it is connected to both ends of the power supply of the MOSFET tube and the chip through the voltage division of the resistor R. The function of the resistor R is: 1. It is used to avoid damage to the MOSFET caused by excessive voltage; 2. It is used to ensure that when the MOSFET tube is in the on state, the formed V _DS is much smaller than the working voltage of the chip.

As shown in Figure 7, further, when the power hysteresis circuit is a P-channel MOSFET type power hysteresis circuit, the source S of the MOSFET tube is connected in series with the power supply Vcc, when the clock circuit outputs to the gate G of the MOSFET tube When the control signal CTL is at high level, the MOSFET tube is fully pinched off, and the chip is not powered on; when the control signal CTL output from the clock circuit to the gate G of the MOSFET tube is at low level, the MOSFET tube is in the open state, and the chip is in the power-up state.

As shown in Figure 9, a resistor R1 can be added to the original P-channel MOSFET power hysteresis circuit, so that one end of the resistor R1 is connected in series with the power supply to Vcc, and the other end is connected to the clock circuit and the gate G of the MOSFET. By default, the control signal CTL is high and applied to the gate G of the MOSFET, which can be pulled up to Vcc through the resistor R1 (such as 10k ohms). At this time, the MOSFET is in a fully pinched state, and the drain D and the source The conductive P channel between S disappears, Vdd=0, and the chip is not powered on at this time. When the clock circuit supplies the clock to the chip, it can output a low level to the gate G of the MOSFET tube, so that The MOSFET tube is turned on, and a conductive P channel is formed between the drain D and the source S, Vdd=Vcc-VSD, because VSD is generally small and negligible (such as VSD≈10mV of NDS356AP), so Vdd≈Vcc, so the chip can work normally After power-on, the clock supply of the chip is earlier than the power supply, and the power-on reset of the chip can be performed normally.

The effect of adding resistor R1 is: it can simplify the control signal CTL output by the clock circuit. When there is no resistor R1, the output of CTL needs to have high and low level changes, and when there is resistor R1, CTL only needs to output low level.

Claims (4)

1. A power hysteresis circuit, comprising clock circuit, MOSFET tube, power supply Vcc and chip power supply Vdd, is characterized in that: the clock circuit sending control signal CTL to MOSFET tube is connected to the gate G of MOSFET tube, the drain of MOSFET tube The pole D is connected in series with the chip power supply Vdd, and the power supply Vcc supplies power to the power hysteresis circuit. The drain D and source S of the MOSFET tube construct a grounding channel between the power supply Vcc and the chip power supply Vdd. 2. A power hysteresis circuit according to claim 1, characterized in that: said power hysteresis circuit includes two types, namely an N-channel MOSFET power hysteresis circuit and a P-channel MOSFET power hysteresis circuit. 3. A kind of power supply hysteresis circuit according to claim 2, characterized in that: when said power supply hysteresis circuit is an N-channel MOSFET type power supply hysteresis circuit, it also includes a resistor R, and the resistor R which acts as a voltage divider is connected in series The power supply is between Vcc and the drain D of the MOSFET, and the source S of the MOSFET is grounded. When the control signal CTL output by the clock circuit to the gate G of the MOSFET is high, the MOSFET is turned on and the chip is not on. Power state; when the control signal CTL output from the clock circuit to the gate G of the MOSFET is at low level, the MOSFET is fully pinched off and the chip is in a power-on state. 4. A kind of power hysteresis circuit according to claim 2, characterized in that: when the power hysteresis circuit is a P-channel MOSFET type power hysteresis circuit, the source S of the MOSFET tube is connected in series with the power supply Vcc, and when the clock When the control signal CTL output by the circuit to the gate G of the MOSFET is high, the MOSFET is fully pinched off and the chip is not powered on; when the control signal CTL output by the clock circuit to the gate G of the MOSFET is low When the level is low, the MOSFET is turned on and the chip is powered on.