CN110196678A - Data stores determination device - Google Patents
Data stores determination device Download PDFInfo
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- CN110196678A CN110196678A CN201810155392.7A CN201810155392A CN110196678A CN 110196678 A CN110196678 A CN 110196678A CN 201810155392 A CN201810155392 A CN 201810155392A CN 110196678 A CN110196678 A CN 110196678A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3212—Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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Abstract
It includes a switch module, a signal generator module and a control module that the present invention, which provides a kind of data storage determination device,.When a power supply module abnormal power-down, the switch module is controlled by a first control signal and continues at one section of predetermined time and export an output power as one first electric power, the signal generator module responds first electric power and the output power and continued operation, and a trigger signal and a second control signal are generated according to a notification signal and the output power, the control module is used to generate the first control signal, and respond the second control signal and continued operation, and control signal output is generated according to its detecting obtained detecting result of one memory module and the trigger signal to control how the memory module stores its data currently received.
Description
[technical field]
The invention relates to a kind of devices, particularly relate to a kind of data storage determination device.
[background technique]
Existing computer system can programmed logic dress comprising the complexity that a power supply module, one are electrically connected the power supply module
(Complex Programmable Logic Device, CPLD) is set, one there is a volatile storage and one non-volatile deposit
The memory module of reservoir, one are connected electrically in control module and other necessary components between the CPLD and the memory module.
The power supply module is electrically connected to the power supply of one input electric power of a supply in such a way that one is pluggable, and according to this
Input electric power supplies power to all elements in the computer system.The CPLD is to detect whether the power supply module has reception
To the input electric power, and a trigger signal is generated accordingly, and the trigger signal is transmitted to the control module.If the power supply is supplied
Module receives the input electric power (that is, the power supply module is electrically connected to the power supply and being capable of normal power supply), the then touching
It signals to be located at a high logic level (that is, high potential)；If the power supply module does not receive the input electric power (that is, the electricity
Source supply module is not electrically connected to the power supply and the power supply module by abnormal power-down), then the trigger signal is located at one and low patrols
Volume level (that is, low potential) exports at this point, the control module generates a control signal according to the trigger signal, and by the control
Signal output is transmitted to the memory module, so that the memory module exports according to the control signal and deposits its volatility
The data (e.g., the central processing unit in the computer system) that reservoir is currently received is stored to the non-volatile holographic storage
In device.
In said structure, which is that relative program is written one by the research staff of Intel (Intel) company
It is made in certain chip, and the cost of the CPLD and sells rather expensive, cause existing computer system to have higher
Cost.Therefore, existing computer system still has improved space.
[summary of the invention]
The technical problem to be solved by the present invention is to be to provide a kind of data storage determination device.
In order to solve the above technical problems, a kind of data stores determination device, it is suitable for a computer system, the computers
System includes the memory module and one of one of both first and second memory cells according to the defeated of an exchange
Enter electric power generate a direct current output power power supply module, the power supply module be also used to generate an instruction its own
The notification signal for whether receiving the input electric power, when the power supply module suffers abnormal power-down, which is located at one
Indicate that the power supply module does not receive the low logic level of the input electric power, and data storage determination device is defeated according to this
Electric power and the notification signal generate a control signal output to control how the memory module stores what it was currently received out
Data.It includes a switch module, a signal generator module and a control module that the data, which stores determination device,.
The switch module receives a first control signal, and for being electrically connected the power supply module to receive output electricity
Power, when the power supply module abnormal power-down, which is controlled by the first control signal and continues at one section and make a reservation for
Time exports the output power as one first electric power.
The signal generator module is electrically connected the switch module and the power supply module, to receive from the switch module
First electric power, and the output power and the notification signal from the power supply module, when power supply module exception
When power-off, which responds first electric power and the output power and continued operation, and according to the notification signal and
The output power generates a trigger signal for being relevant to the notification signal, and generates a second control signal.
The control module is used to generate the first control signal, and is connected electrically in the signal generator module and the memory mould
Between block, detecting the memory module includes the first memory unit or the second memory unit to obtain a detecting knot
Fruit, and the trigger signal and the second control signal from the signal generator module are received, when power supply module exception
When power-off, which responds the second control signal and continued operation, and is produced according to the detecting result and the trigger signal
Raw control signal output, and control signal output is transmitted to the memory module.
Compared to the prior art, in data storage determination device of the present invention, the switch module and the signal generator module are
Implemented with the framework of hardware circuit, the power supply module, the switch module and the signal generator module, which match, may replace habit
Know a complexity that technology is mentioned can program logic device, and the power supply module, the switch module and the signal generator module
Total manufacturing cost be only the complexity can program logic device half so that according to the data store determination device composed by
The computer system has lower cost compared to existing computer system.
[Detailed description of the invention]
Fig. 1 is a block diagram, illustrates one first state sample implementation of an embodiment of data storage determination device of the present invention.
Fig. 2 is a circuit diagram, illustrates a switch module of the embodiment.
Fig. 3 is a circuit block diagram, illustrates a signal generator module of the embodiment.
Fig. 4 is a circuit diagram, illustrates one second phase inverter of the signal generator module of the embodiment.
Fig. 5 is a block diagram, illustrates a delay cell of the signal generator module of the embodiment.
Fig. 6 is a timing diagram, illustrates the operation of the embodiment.
Fig. 7 is a block diagram, illustrates one second state sample implementation of the embodiment.
[specific embodiment]
First embodiment:
As shown in fig.1, the embodiment that the present invention provides a kind of data storage determination device 1 is suitable for a computer system 2,
To determine how data stores in the computer system 2 power-off.
The computer system 2 includes a first memory unit 211 and a second memory unit (not shown)
The memory module 21 of one of the two, a power supply module 22 and other necessary components are (not shown, and it is this technology
Have known to general knowledge person in field, omit do not repeat herein).In this embodiment, which includes being somebody's turn to do
First memory unit 211, and the first memory unit 211 is a non-volatile dual inline memory modules (Non-
Volatile Dual In-line Memory Module, NVDIMM).There is the first memory unit 211 volatility to deposit
Reservoir (not shown) and a non-volatility memorizer (not shown).When the power supply module 22 does not suffer abnormal power-down (that is, the electricity
Source supply module 22 is electrically connected to a power supply and being capable of normal power supply) and when 2 normal operation of computer system, the department of computer science
System 2 mainly stores data into the volatile storage of the first memory unit 211.The power supply module 22 with
One pluggable mode is electrically connected to the power supply (not shown) of the input electric power Vin of the supply one exchange, and according to input electricity
Power Vin generates the output power Vo of a direct current.The power supply module 22 is also used to generate an instruction whether its own receives
The notification signal D1 of input electric power Vin.When the power supply module 22 is by abnormal power-down (that is, the power supply module 22
It is not electrically connected to the power supply), notification signal D1 indicates that the power supply module 22 does not receive input electric power Vin(that is, should
Notification signal D1 is located at a low logic level (that is, 0 〞 level of logic 〝)), at this point, the power supply module 22 is according in its own
On portion's circuit board the remaining electric power of each element come continue generate output power Vo so that the data storage determination device 1 be able to
A control signal output Cout is generated according to output power Vo and notification signal D1 to control the first memory unit 211
The data that its volatile storage is currently received is stored to the non-volatility memorizer of the first memory unit 211
In.
It includes a switch module 4, a signal generator module 5 and a control mould that the present embodiment data, which stores determination device 1,
Block 6.
The switch module 4 receives a first control signal C1, and is somebody's turn to do for being electrically connected the power supply module 22 with receiving
Output power Vo.When first control signal C1 is located at a high logic level (that is, 1 〞 level of logic 〝), the switch module 4 by
The first control signal C1 control and by output power Vo export and as one first electric power V1.As first control signal C1
When positioned at the low logic level, it is output power Vo's which, which is controlled by first control signal C1 without exporting,
First electric power V1.In this embodiment, the implementation of the switch module 4 is refering to shown in Fig. 2.
The signal generator module 5 is electrically connected the control module 6, the switch module 4 and the power supply module 22.When this
Signal generator module 5 receives first electric power V1 from the switch module 4, the output from the power supply module 22
When electric power Vo and notification signal D1, which responds the first electric power V1 and output power Vo and operates, and
According at least to notification signal D1 and output power Vo, a trigger signal Ts and one for being relevant to notification signal D1 is generated
Second control signal C2.In addition, the signal generator module 5 also receives a delay selection signal Ds, and the memory module 21 is also
It is controlled by delay selection signal Ds.
It further regards to shown in Fig. 3, in this embodiment, which includes a signal generation unit 51, one
Switch unit 52, a delay cell 53, a logic gate unit 54 and an electric power adjustment unit 55.
The signal generation unit 51 is electrically connected the power supply module 22 and the switch module 4.When the signal generation unit
51 receive output power Vo and notification signal D1 from the power supply module 22, and receive from the switching molding
When first electric power V1 of block 4, which responds the first electric power V1 and output power Vo and operates, and root
Trigger signal Ts and a switching signal S1 are generated according to output power Vo and notification signal D1.The phase of switching signal S1
Reverse phase is in the phase of notification signal D1.In this embodiment, which includes first and second phase inverter
511,512, with first and second flip-flop 513,514.It is positive and negative that first and second equal flip-flop 513,514 is respectively a D type
Device.
First phase inverter 511 is electrically connected the power supply module 22 to receive notification signal D1, and according to the notice
Signal D1 generates an inversion signal Rs.The reverse-phase of inversion signal Rs is in the phase of notification signal D1.
There is first flip-flop 513 the data input end D of a reception output power Vo, one to be electrically connected first reverse phase
Device 511 with receive inversion signal Rs clock input CLK, one be electrically connected the switch module 4 to receive first electric power V1
The noninverting data output end Q of power input VCC and one.First flip-flop 513 is believed according to output power Vo, the reverse phase
Number Rs and first electric power V1 generates a pulse wave signal Ps in its noninverting data output end Q.
Second phase inverter 512 is electrically connected the noninverting data output end Q of first flip-flop 513 to receive the pulse wave
Signal Ps, and trigger signal Ts is generated according to pulse wave signal Ps, the reverse-phase of trigger signal Ts is in the pulse wave signal
The phase of Ps.In this embodiment, the implementation of second phase inverter 512 is as shown in fig.4, trigger signal Ts includes a triggering
The phase of a signal section Ts1 and interrupt signal part SMI, trigger signal part Ts1 are with interrupt signal part SMI's
Phase is identical.
Second flip-flop 514 has the electricity of the data input end D for being electrically connected to each other and receiving output power Vo and one
Source input terminal VCC, one are electrically connected the noninverting data output end Q of first flip-flop 513 to receive pulse wave signal Ps's
The noninverting data output end Q of clock input CLK and one.Second flip-flop 514 is believed according to output power Vo and the pulse wave
Number Ps generates switching signal S1 in the noninverting data output end Q.
The delay cell 53 receives delay selection signal Ds, and is electrically connected the power supply module 22 to receive the notice
Signal D1, and a postpones signal is generated according to notification signal D1 and delay selection signal Ds and exports Do.Further referring to
Shown in Fig. 5, in this embodiment, which includes first and second delay circuit 531,532 and a switching circuit
533。
First delay circuit 531 is electrically connected the power supply module 22 to receive notification signal D1, and by the notice
Signal D1 delay one generates one first postpones signal De1 at the first time.Second delay circuit 532 is electrically connected power supply supply
Notification signal D1 was postponed for one second time and generates one second postpones signal by module 22 to receive notification signal D1
De2.In this embodiment, this is 600us at the first time, which is 15ms.
The switching circuit 533 receives delay selection signal Ds, and be electrically connected the grade first and second delay circuit 531,
532 to receive first and second postpones signal De1, De2 of the grade respectively, and generates postpones signal output Do accordingly.The switching
Circuit 533 is operated according to delay selection signal Ds, and when delay selection signal Ds is located at the high logic level, this first
Postpones signal De1 exports Do as the postpones signal, and when delay selection signal Ds is located at the low logic level, this second prolongs
Slow signal De2 exports Do as the postpones signal.
The logic gate unit 54 is electrically connected the delay cell 53 and the power supply module 22 to receive delay letter respectively
Number output Do and notification signal D1, and Do and notification signal D1 are exported according to the postpones signal and generate an output signal Os.
In this embodiment, which is an anti-lock unit.
The electric power adjustment unit 55 is electrically connected the power supply module 22 and the logic gate unit 54, receives respectively from this
The output power Vo and output signal Os of power supply module 22 and the logic gate unit 54, and according to output power Vo
And output signal Os generates electric power adjustment signal Pa.In this embodiment, it includes multiple which, which is one,
The existing component of the transformer sequentially concatenated, when output signal Os is located at the high logic level, the isallobaric device is according to this
Output power Vo sequentially starts to generate respectively multiple voltage signals with different potentials each other in different timing and supplies the calculating
Related elements in machine system 2, and the voltage signal instruction power supply timing for being finally generated and exporting is completed and as this
Electric power adjustment signal Pa.When output signal Os is located at the low logic level, which sequentially distinguishes in different timing
Stop for voltage signals should be waited to the related elements in the computer system 2.
The noninverting data output end Q, the power supply module of the switch unit 52 electrical connection second flip-flop 514
22 and the electric power adjustment unit 55 to receive switching signal S1, output power Vo and electric power adjustment signal Pa respectively, and
Second control signal C2 is generated accordingly.The switch unit 52 is operated according to switching signal S1, when the switching signal S1
When the high logic level (that is, 22 abnormal power-down of power supply module), the switch unit 52 according to switching signal S1 and
It, should when switching signal S1 is located at the low logic level by output power Vo output and as second control signal C2
Switch unit 52 exports according to switching signal S1 and by the electric power adjustment signal Pa and as second control signal C2.
The control module 6 is used to generate and export first control signal C1 to the switch module 4, and is connected electrically in the letter
Number between generation module 5 and the memory module 21, the memory module 21 is detected to obtain the instruction memory module 21 and be
Detecting result D2 including the first memory unit 211 or the second memory unit, and receive and generated from the signal
The trigger signal Ts and second control signal C2 of module 5.The control module 6 generates delay choosing according to detecting result D2
Signal Ds is selected, and delay selection signal Ds is exported to the switching circuit 533 of the delay cell 53 and the first memory
Unit 211.When the power supply module 22 is by abnormal power-down, which responds second control signal C2 and continues
Running, and control signal output Cout is generated according to detecting result D2 and trigger signal Ts, and the control signal is defeated
Cout is transmitted to the first memory unit 211 out, so that the first memory unit 211 exports Cout according to the control signal
And the data that its internal volatile storage is currently received is stored that internal this is non-to it by delay selection signal Ds
In volatile storage.In this embodiment, which includes a processing unit 61 and a control unit 62.The control
Unit 62 is implemented with a platform path controller (Platform Controller Hub, PCH).
The processing unit 61 is used to be electrically connected the memory module 21, and when the computer system 2 is switched on, the processing
Unit 61 detects the type of the memory module 21, to generate detecting result D2.In this embodiment, detecting result D2 refers to
Show that the memory module 21 includes the first memory unit 211.
The control unit 62 is electrically connected the processing unit 61 and the signal generator module 5, and is used to generate first control
For signal C1(when the computer system 2 is to carry out normal boot-strap, the control unit 62 is according to the received booting signal of its institute
(not shown) generates the first control signal C1 with the high logic level, and when the computer system 2 is normally to be closed
When machine, which notifies the control unit 62 to generate the first control signal C1 with the low logic level).When this
Control unit 62 receives the detecting result D2 from the processing unit 61, the letter of the triggering from the signal generator module 5
When number Ts and second control signal C2, which generates delay selection signal Ds according to detecting result D2, and
When the power supply module 22 is by abnormal power-down, which responds second control signal C2 and continued operation, and
One first power down notification signal Pd1 is generated according to detecting result D2 and trigger signal Ts and the control signal exports Cout,
And by the first power down notification signal Pd1 and control signal output Cout is transmitted separately to the processing unit 61 and this first is deposited
Storage unit 211.When the processing unit 61 receives first power down notification signal Pd1, the processing unit 61 is also according to this
First power down notification signal Pd1 controls the first memory unit 211 and enters a battery saving mode.
As shown in fig.6, illustrating the timing of coherent signal when data storage determination device 1 operates.Parameter t0, t1, t2
For time point, parameter t3 is one section of predetermined time.
Time point t0 ~ time point t1: further regarding to shown in Fig. 1, Fig. 3 and Fig. 5, and the power supply module 22 is not by abnormal
Power-off and the computer system 2 and the data store determination device 1 and are activated and carry out the relevant operation of normal boot-strap.Because normal
The relevant operation of booting is to be familiar with known to the usual skill of the art, therefore do not repeat in this.It should be noted that herein
Stage, switching signal S1 are located at the low logic level, and the switch unit 52 is using the electric power adjustment signal Pa as second control
Signal C2 processed.The processing unit 61 detects that the memory module 21 includes the first memory unit 211 or this second is deposited
Storage unit obtains detecting result D2, so that the control unit 62 generates the delay selection signal according to detecting result D2
Ds(is relevant to for selecting when the power supply module 22 is by abnormal power-down, which can continue output should
The length of the time interval of equal voltage signals), and the switching circuit 533 is operated and is generated according to delay selection signal Ds
The postpones signal exports Do.For example, in this embodiment, which belongs to the first memory unit 211,
Detecting result D2 and delay selection signal Ds is located at the high logic level and (first deposits when the memory module 21 is not belonging to this
When storage unit 211, detecting result D2 and delay selection signal Ds are located at the low logic level), therefore, it is fixed by this
One postpones signal De1 as the postpones signal exports Do(that is, when the power supply module 22 is by abnormal power-down, the electric power tune
The time that whole unit 55 can continue to export the grade voltage signals is 600us).
Time point t1: the power supply module 22 suffers abnormal power-down, and notification signal D1 is converted into from the high logic level
The low logic level (that is, the power supply module 22 does not receive input electric power Vin and abnormal power-down).
Time point t1 ~ time point t2: at this point, the power supply module 22 can be remaining by having on its own internal circuit board
An at least element for electric power is discharged and persistently exports output power Vo.It is predetermined that first control signal C1 continues at the section
Time t3 is located at the high logic level, so that the switch module 4 continues at this section of predetermined time t3 and exports the first electric power V1
Enable first flip-flop 513, so that first flip-flop 513 generates pulse wave signal Ps, and pulse wave signal Ps is low from this
Logic level is converted into the upper limb triggering of the high logic level, and switching signal S1 can be promoted also and then to turn from the low logic level
Change the high logic level into, so that the switch unit 52 is using output power Vo as second control signal C2, and the triggering
Signal Ts is converted into the low logic level (that is, the signal generator module 5 responds the first electric power V1 and should from the high logic level
Output power Vo and continued operation).In this way, which the control unit 62 learns that the power supply supplies mould according to trigger signal Ts
Block 22 suffers abnormal power-down, and generates control signal output Cout and first power down notification signal Pd1, so that the processing unit
61, which control the first memory unit 211 according to the first power down notification signal Pd1, enters the battery saving mode, and first storage
Device unit 21 exports Cout by delay selection signal Ds enable, and according to the control signal come by its internal volatile storage
The data that device is currently received is stored into its internal non-volatility memorizer.
It should be noted that when the power supply module 22 does not suffer abnormal power-down (that is, what the power supply module 22 was exported
Notification signal D1 is located at the high logic level), and the computer system 2 is 61 meeting of processing unit when carrying out normal shutdown
First receive a shutdown command and notify the control unit 62 so that the control unit 62 first by first control signal C1 from this
High logic level is converted into the low logic level, thus the switch module 4 stop output first electric power V1 come enable this first
Flip-flop 513.In this way, which trigger signal Ts caused by the signal generator module 5 will not be converted from the high logic level
At the low logic level, and then it can avoid the control module 6 and generate control signal output Cout.
Second embodiment:
As shown in fig.7, the second state sample implementation of present invention data storage determination device 1 is similar to first state sample implementation,
The two the difference is that: the memory module 21 include the second memory unit 212；It should caused by the processing unit 61
Detecting result D2 indicates that the memory module 21 is the second memory unit 212；The control unit 62 does not generate the control
Signal exports Cout；When the power supply module 22 is by abnormal power-down, which responds second control signal C2
And continued operation, and one second power down notification signal Pd2 is generated according to detecting result D2 and trigger signal Ts, and by this
Two power down notification signal Pd2 are transmitted to the processing unit 61, so that the processing unit 61 is according to the second power down notification signal Pd2
Control signal output Cout is generated, and control signal output Cout is transmitted to the second memory unit 212, so that should
The data that second memory unit 212 exports Cout according to the control signal and currently received it is stored to the one of its inside
In non-volatility memorizer (not shown).In this embodiment, which is Apache Pass storage
Device unit.
In conclusion the switch module 4 and the signal generator module 5 are implemented with the framework of hardware circuit, by the electricity
Switch module 4 and the signal generator module 5 of notification instruction D1 provided by source supply module 22 and the present embodiment match
Close may replace a complexity that known techniques are mentioned can program logic device, and the power supply module 22, the switch module 4 and should
Total manufacturing cost of signal generator module 5 be only the complexity can program logic device half, in this way, according to the present embodiment
The data storage determination device 1 composed by the computer system 2 compared to existing computer system have lower cost.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (8)
1. a kind of data stores determination device, it is suitable for a computer system, which includes first and the
Both two memory cells one of them memory module and one according to one exchange input electric power generate a direct current output
The power supply module of electric power, the power supply module are also used to generate an instruction whether its own receives the input electric power
Notification signal, when the power supply module suffers abnormal power-down, which is located at one and indicates that the power supply module does not connect
The low logic level of the input electric power is received, and data storage determination device is generated according to the output power and the notification signal
One control signal output is to control how the memory module stores its data currently received, which is characterized in that the data
Storage determination device includes:
One switch module receives a first control signal, and is used to be electrically connected the power supply module to receive the output power,
When the power supply module abnormal power-down, which is controlled by the first control signal and continues at one section of predetermined time
The output power is exported as one first electric power；
One signal generator module is electrically connected the switch module and the power supply module, to receive being somebody's turn to do from the switch module
First electric power, and the output power and the notification signal from the power supply module, when the power supply module is extremely disconnected
When electric, which responds first electric power and the output power and continued operation, and according to the notification signal and should
Output power generates a trigger signal for being relevant to the notification signal, and generates a second control signal；And
One control module for generating the first control signal, and is connected electrically in the signal generator module and the memory module
Between, detecting the memory module includes the first memory unit or the second memory unit to obtain a detecting knot
Fruit, and the trigger signal and the second control signal from the signal generator module are received, and according to the detecting result and be somebody's turn to do
Trigger signal generates control signal output, and control signal output is transmitted to the memory module.
2. data storage determination device according to claim 1, which is characterized in that the memory module includes that this first is deposited
Storage unit, the control module include:
One processing unit, for being electrically connected and detecting the type of the memory module, to generate the detecting result, the detecting result
Indicate that the memory module includes the first memory unit；And
One control unit for generating the first control signal, and is electrically connected the processing unit and the signal generator module, receives
The detecting result from the processing unit, and the trigger signal and the second control signal from the signal generator module,
When the power supply module abnormal power-down, which responds the second control signal and continued operation, and is detectd according to this
It surveys result and the trigger signal generates one first power down notification signal and control signal output, and first power down notification is believed
Number and the control signal output be transmitted separately to the processing unit and the first memory unit；
When the processing unit receives the first power down notification signal, the processing unit is also according to the first power down notification signal
The first memory unit is controlled into a battery saving mode.
3. data storage determination device according to claim 1, which is characterized in that the memory module includes that this second is deposited
Storage unit, the control module include:
One processing unit, for being electrically connected and detecting the type of the memory module, to generate the detecting result, the detecting result
Indicate that the memory module includes the second memory unit；And
One control unit for generating the first control signal, and is electrically connected the processing unit and the signal generator module, receives
The detecting result from the processing unit, and the trigger signal and the second control signal from the signal generator module,
When the power supply module abnormal power-down, which responds the second control signal and continued operation, and is detectd according to this
It surveys result and the trigger signal generates one second power down notification signal, and the second power down notification signal is transmitted to the processing list
Member exports so that the processing unit generates the control signal according to the second power down notification signal, and the control signal is exported
It is transmitted to the second memory unit.
4. data storage determination device according to claim 1, which is characterized in that the control module is also according to the detecting knot
Fruit generates a delay selection signal, and the delay selection signal is exported to the signal generator module, the signal generator module packet
It includes:
One signal generation unit is electrically connected the power supply module and the switch module, receives from the power supply module
The output power and the notification signal, and first electric power from the switch module is received, when power supply module exception
When power-off, which responds first electric power and the output power and continued operation, and according to the output power and
The notification signal generates the trigger signal and a switching signal, and the reverse-phase of the switching signal is in the phase of the notification signal；
One delay cell is electrically connected the control module and the power supply module to receive the delay selection signal respectively and this is logical
Know signal, and postpones signal output is generated according to the notification signal and the delay selection signal；
One logic gate unit is electrically connected the delay cell and the power supply module to receive postpones signal output respectively and be somebody's turn to do
Notification signal, and an output signal is generated according to postpones signal output and the notification signal；
One electric power adjustment unit is electrically connected the logic gate unit and the power supply module to receive the output signal respectively and be somebody's turn to do
Output power, and an electric power adjustment signal is generated according to the output power and the output signal；And
One switch unit is electrically connected the electric power adjustment unit, the signal generation unit and the power supply module to receive respectively
The electric power adjustment signal, the switching signal and the output power, and generate the second control signal accordingly, the switch unit according to
The switching signal operates, and when the power supply module abnormal power-down, the output power is as the second control signal, when this
When the non-abnormal power-down of power supply module, the electric power adjustment signal is as the second control signal.
5. data storage determination device according to claim 4, which is characterized in that the delay cell includes:
One first delay circuit is electrically connected the detecting module to receive the notification signal, and the notification signal is postponed one first
Time and generate one first postpones signal；
One second delay circuit is electrically connected the detecting module to receive the notification signal, and the notification signal is postponed one second
Time and generate one second postpones signal；And
One switching circuit is electrically connected the control module and the grade first and second delay circuit, receives respectively from the control mould
Block and this etc. the delay selection signal of first and second delay circuit and this etc. first and second postpones signal, and generate accordingly
Postpones signal output, the switching circuit are operated according to the delay selection signal, are patrolled when the delay selection signal is located at a height
When collecting level, which exports as the postpones signal, when the delay selection signal is located at a low logic level,
Second postpones signal is exported as the postpones signal.
6. data storage determination device according to claim 4, which is characterized in that the logic gate unit is an anti-lock list
Member.
7. data storage determination device according to claim 4, which is characterized in that the signal generation unit includes:
One first phase inverter is electrically connected the power supply module to receive the notification signal, and generate one according to the notification signal
Inversion signal, the reverse-phase of the inversion signal is in the phase of the notification signal；
One first flip-flop, with one receive the output power data input end, one be electrically connected first phase inverter to receive
The clock input of the inversion signal, the electrical connection switch module are to receive the power input of first electric power and one non-anti-
Phase data output end, first flip-flop is according to the output power, the inversion signal and first electric power, in its noninverting money
Expect output end, generates a pulse wave signal；
One second phase inverter is electrically connected the noninverting data output end of first flip-flop to receive the pulse wave signal, and root
The trigger signal is generated according to the pulse wave signal, the reverse-phase of the trigger signal is in the phase of the pulse wave signal；And
One second flip-flop, have be electrically connected to each other and receive the output power a data input end and a power input,
One to be electrically connected the noninverting data output end of first flip-flop non-anti-with the clock input for receiving the pulse wave signal and one
Phase data output end, second flip-flop are produced according to the output power and the pulse wave signal in its noninverting data output end
The raw switching signal.
8. data storage determination device according to claim 7, which is characterized in that first and second equal flip-flop is respectively
For a D-type flip-flop.
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