CN110196678B - Data storage determining device - Google Patents
Data storage determining device Download PDFInfo
- Publication number
- CN110196678B CN110196678B CN201810155392.7A CN201810155392A CN110196678B CN 110196678 B CN110196678 B CN 110196678B CN 201810155392 A CN201810155392 A CN 201810155392A CN 110196678 B CN110196678 B CN 110196678B
- Authority
- CN
- China
- Prior art keywords
- signal
- power
- module
- output
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3212—Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Power Sources (AREA)
Abstract
The invention provides a data storage decision device, which comprises a switch module, a signal generation module and a control module. When a power supply module is abnormally powered off, the switch module is controlled by a first control signal and continuously outputs output power as first power for a preset period of time, the signal generation module responds to the first power and the output power to continuously operate and generates a trigger signal and a second control signal according to a notification signal and the output power, the control module is used for generating the first control signal and responds to the second control signal to continuously operate, and a detection result obtained by detecting a memory module and the trigger signal are used for generating a control signal output to control the memory module to store the currently received data.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to a device, and more particularly, to a data storage determining device.
[ background of the invention ]
The computer system comprises a power supply module, a Complex Programmable Logic Device (CPLD) electrically connected to the power supply module, a memory module having a volatile memory and a non-volatile memory, a control module electrically connected between the CPLD and the memory module, and other necessary components.
The power supply module is electrically connected to a power supply supplying an input power in a pluggable manner, and supplies power to all elements in the computer system according to the input power. The CPLD is used for detecting whether the power supply module receives the input power, generating a trigger signal according to the input power and transmitting the trigger signal to the control module. If the power supply module receives the input power (i.e., the power supply module is electrically connected to the power supply and can normally supply power), the trigger signal is at a high logic level (i.e., high potential); if the power supply module does not receive the input power (i.e., the power supply module is not electrically connected to the power supply and the power supply module is abnormally powered off), the trigger signal is at a low logic level (i.e., a low potential), and at this time, the control module generates a control signal output according to the trigger signal and transmits the control signal output to the memory module, so that the memory module stores the data currently received by the volatile memory (e.g., from a central processing unit in the computer system) into the non-volatile memory according to the control signal output.
In the above structure, the CPLD is manufactured by a developer of Intel (Intel) corporation writing a relevant program into a specific chip, and the cost and the selling cost of the CPLD are expensive, which results in a high cost of the existing computer system. Accordingly, there remains room for improvement in existing computer systems.
[ summary of the invention ]
The present invention provides a data storage determining device.
In order to solve the above technical problem, a data storage determining device is applicable to a computer system, the computer system comprises a memory module including one of a first memory unit and a second memory unit, and a power supply module generating a direct current output power according to an alternating current input power, the power supply module is further used for generating a notification signal indicating whether the power supply module receives the input power, when the power supply module is abnormally powered off, the notification signal is at a low logic level indicating that the power supply module does not receive the input power, and the data storage determining device generates a control signal output according to the output power and the notification signal to control how the memory module stores the currently received data. The data storage determining device comprises a switch module, a signal generating module and a control module.
The switch module receives a first control signal and is used for being electrically connected with the power supply module to receive the output power, and when the power supply module is abnormally powered off, the switch module is controlled by the first control signal and continuously outputs the output power as the first power for a preset period of time.
The signal generating module is electrically connected with the switch module and the power supply module to receive the first power from the switch module, the output power from the power supply module and the notification signal, and when the power supply module is abnormally powered off, the signal generating module responds to the first power and the output power to continuously operate, generates a trigger signal related to the notification signal according to the notification signal and the output power, and generates a second control signal.
The control module is used for generating the first control signal, is electrically connected between the signal generating module and the memory module, detects whether the memory module comprises the first memory unit or the second memory unit to obtain a detection result, receives the trigger signal and the second control signal from the signal generating module, responds to the second control signal to continuously operate when the power supply module is abnormally powered off, generates the control signal output according to the detection result and the trigger signal, and outputs and transmits the control signal output to the memory module.
Compared with the prior art, in the data storage decision device, the switch module and the signal generation module are implemented by a hardware circuit architecture, the power supply module, the switch module and the signal generation module can be matched to replace a complex programmable logic device provided by the prior art, and the total manufacturing cost of the power supply module, the switch module and the signal generation module is only half of that of the complex programmable logic device, so that the computer system formed by the data storage decision device has lower cost compared with the existing computer system.
[ description of the drawings ]
FIG. 1 is a block diagram illustrating a first implementation of a data storage determination apparatus according to an embodiment of the invention.
Fig. 2 is a circuit diagram illustrating a switch module according to the embodiment.
FIG. 3 is a circuit block diagram illustrating a signal generation module according to the embodiment.
Fig. 4 is a circuit diagram illustrating a second inverter of the signal generating module according to the embodiment.
Fig. 5 is a block diagram illustrating a delay unit of the signal generating module according to the embodiment.
Fig. 6 is a timing diagram illustrating the operation of the embodiment.
FIG. 7 is a block diagram illustrating a second aspect of the embodiment.
[ detailed description ] embodiments
The first embodiment:
referring to FIG. 1, an embodiment of a data storage determination device 1 is applied to a computer system 2 for determining how data is stored when the computer system 2 is powered off.
The computer system 2 includes a memory module 21 including one of a first memory unit 211 and a second memory unit (not shown), a power supply module 22 and other necessary components (not shown, and well known to those skilled in the art, and thus not described herein). In this embodiment, the Memory Module 21 includes the first Memory unit 211, and the first Memory unit 211 is a Non-Volatile Dual In-line Memory Module (NVDIMM). The first memory unit 211 has a volatile memory (not shown) and a non-volatile memory (not shown). When the power supply module 22 is not abnormally powered off (i.e., the power supply module 22 is electrically connected to a power source and can supply power normally) and the computer system 2 operates normally, the computer system 2 mainly stores data in the volatile memory of the first memory unit 211. The power supply module 22 is electrically connected to the power source (not shown) supplying an ac input power Vin in a pluggable manner, and generates a dc output power Vo according to the input power Vin. The power supply module 22 is also used to generate a notification signal D1 indicating whether it has received the input power Vin. When the power supply module 22 is abnormally powered off (i.e., the power supply module 22 is not electrically connected to the power source), the notification signal D1 indicates that the power supply module 22 does not receive the input power Vin (i.e., the notification signal D1 is at a low logic level (i.e., logic "" 0 ""), at this time, the power supply module 22 continuously generates the output power Vo according to the residual power of each element on its own internal circuit board, so that the data storage determination device 1 can generate a control signal output Cout according to the output power Vo and the notification signal D1 to control the first memory unit 211 to store the data currently received by the volatile memory thereof in the non-volatile memory of the first memory unit 211.
The data storage determining apparatus 1 of the present embodiment includes a switch module 4, a signal generating module 5 and a control module 6.
The switch module 4 receives a first control signal C1 and is electrically connected to the power supply module 22 to receive the output power Vo. When the first control signal C1 is at a high logic level (i.e., logic level "" 1 ""), the switch module 4 is controlled by the first control signal C1 to output the output power Vo as a first power V1. When the first control signal C1 is at the low logic level, the switch module 4 is controlled by the first control signal C1 to output the first power V1 as the output power Vo. In this embodiment, the implementation of the switch module 4 is shown in fig. 2.
The signal generating module 5 is electrically connected to the control module 6, the switch module 4, and the power supply module 22. When the signal generating module 5 receives the first power V1 from the switch module 4, the output power Vo from the power supply module 22 and the notification signal D1, the signal generating module 5 operates in response to the first power V1 and the output power Vo, and generates a trigger signal Ts related to the notification signal D1 and a second control signal C2 at least according to the notification signal D1 and the output power Vo. In addition, the signal generating module 5 also receives a delay selection signal Ds, and the memory module 21 is also controlled by the delay selection signal Ds.
As further shown in fig. 3, in this embodiment, the signal generating module 5 includes a signal generating unit 51, a switching unit 52, a delay unit 53, a logic gate unit 54, and a power adjusting unit 55.
The signal generating unit 51 is electrically connected to the power supply module 22 and the switch module 4. When the signal generating unit 51 receives the output power Vo and the notification signal D1 from the power supply module 22 and receives the first power V1 from the switch module 4, the signal generating unit 51 operates in response to the first power V1 and the output power Vo and generates the trigger signal Ts and a switching signal S1 according to the output power Vo and the notification signal D1. The phase of the switching signal S1 is opposite to the phase of the notification signal D1. In this embodiment, the signal generating unit 51 includes first and second inverters 511 and 512, and first and second flip- flops 513 and 514. The first and second flip- flops 513, 514 are each a D-type flip-flop.
The first inverter 511 is electrically connected to the power supply module 22 for receiving the notification signal D1 and generating an inverted signal Rs according to the notification signal D1. The phase of the inversion signal Rs is inverted with respect to the phase of the notification signal D1.
The first flip-flop 513 has a data input terminal D for receiving the output power Vo, a clock input terminal CLK electrically connected to the first inverter 511 for receiving the inverted signal Rs, a power input terminal VCC electrically connected to the switch module 4 for receiving the first power V1, and a non-inverted data output terminal Q. The first flip-flop 513 generates a pulse signal Ps at the non-inverted data output Q thereof according to the output power Vo, the inverted signal Rs and the first power V1.
The second inverter 512 is electrically connected to the non-inverted data output terminal Q of the first flip-flop 513 to receive the pulse signal Ps and generate the trigger signal Ts according to the pulse signal Ps, wherein the phase of the trigger signal Ts is inverted with respect to the phase of the pulse signal Ps. In this embodiment, the implementation of the second inverter 512 is shown in fig. 4, the trigger signal Ts includes a trigger signal portion Ts1, and an interrupt signal portion SMI, and the phase of the trigger signal portion Ts1 is the same as the phase of the interrupt signal portion SMI.
The second flip-flop 514 has a data input terminal D and a power input terminal VCC electrically connected to each other for receiving the output power Vo, a clock input terminal CLK electrically connected to the non-inverted data output terminal Q of the first flip-flop 513 for receiving the pulse signal Ps, and a non-inverted data output terminal Q. The second flip-flop 514 generates the switching signal S1 at the non-inverted data output Q according to the output power Vo and the pulse signal Ps.
The delay unit 53 receives the delay selection signal Ds, is electrically connected to the power supply module 22 to receive the notification signal D1, and generates a delay signal output Do according to the notification signal D1 and the delay selection signal Ds. Referring further to fig. 5, in this embodiment, the delay unit 53 includes first and second delay circuits 531 and 532, and a switching circuit 533.
The first delay circuit 531 is electrically connected to the power supply module 22 for receiving the notification signal D1 and delaying the notification signal D1 by a first time to generate a first delay signal De 1. The second delay circuit 532 is electrically connected to the power supply module 22 for receiving the notification signal D1 and delaying the notification signal D1 for a second time to generate a second delayed signal De 2. In this embodiment, the first time is 600us and the second time is 15 ms.
The switch circuit 533 receives the delay selection signal Ds, and is electrically connected to the first and second delay circuits 531, 532 to receive the first and second delay signals De1, De2, respectively, and accordingly generate the delay signal output Do. The switch circuit 533 operates according to the delay selection signal Ds, and the first delayed signal De1 is used as the delayed signal output Do when the delay selection signal Ds is at the high logic level, and the second delayed signal De2 is used as the delayed signal output Do when the delay selection signal Ds is at the low logic level.
The logic gate unit 54 is electrically connected to the delay unit 53 and the power supply module 22 for receiving the delay signal output Do and the notification signal D1, respectively, and generating an output signal Os according to the delay signal output Do and the notification signal D1. In this embodiment, the logic gate unit 54 is a back gate unit.
The power adjusting unit 55 is electrically connected to the power supply module 22 and the logic gate unit 54, receives the output power Vo and the output signal Os from the power supply module 22 and the logic gate unit 54, respectively, and generates the power adjusting signal Pa according to the output power Vo and the output signal Os. In this embodiment, the power adjustment unit 55 is a conventional component including a plurality of transformers connected in series in sequence, when the output signal Os is at the high logic level, the transformers respectively start to generate a plurality of voltage signals having different potentials from each other at different timings according to the output power Vo, and the voltage signal generated and outputted finally indicates that the power timing is completed and serves as the power adjustment signal Pa. When the output signal Os is at the low logic level, the transformers sequentially stop supplying the voltage signals to the related devices in the computer system 2 at different timings, respectively.
The switching unit 52 is electrically connected to the non-inverting data output Q of the second flip-flop 514, the power supply module 22 and the power adjusting unit 55 to receive the switching signal S1, the output power Vo and the power adjusting signal Pa, respectively, and accordingly generate the second control signal C2. The switching unit 52 operates according to the switching signal S1, when the switching signal S1 is at the high logic level (i.e., the power supply module 22 is abnormally powered off), the switching unit 52 outputs the output power Vo as the second control signal C2 according to the switching signal S1, and when the switching signal S1 is at the low logic level, the switching unit 52 outputs the power adjustment signal Pa as the second control signal C2 according to the switching signal S1.
The control module 6 is configured to generate and output the first control signal C1 to the switch module 4, and is electrically connected between the signal generating module 5 and the memory module 21, detect the memory module 21 to obtain a detection result D2 indicating whether the memory module 21 includes the first memory cell 211 or the second memory cell, and receive the trigger signal Ts and the second control signal C2 from the signal generating module 5. The control module 6 generates the delay selection signal Ds according to the detection result D2, and outputs the delay selection signal Ds to the switching circuit 533 of the delay unit 53 and the first memory unit 211. When the power supply module 22 is abnormally powered off, the control module 6 responds to the second control signal C2 to operate continuously, generates the control signal output Cout according to the detection result D2 and the trigger signal Ts, and transmits the control signal output Cout to the first memory unit 211, so that the first memory unit 211 stores the data currently received by the volatile memory therein into the non-volatile memory therein according to the control signal output Cout and the delay selection signal Ds. In this embodiment, the control module 6 includes a processing unit 61 and a control unit 62. The control unit 62 is implemented as a Platform Path Controller Hub (PCH).
The processing unit 61 is used to electrically connect the memory module 21, and when the computer system 2 is powered on, the processing unit 61 detects the type of the memory module 21 to generate the detection result D2. In this embodiment, the detection result D2 indicates that the memory module 21 includes the first memory cell 211.
The control unit 62 is electrically connected to the processing unit 61 and the signal generating module 5, and is configured to generate the first control signal C1 (when the computer system 2 is normally powered on, the control unit 62 generates the first control signal C1 with the high logic level according to a power-on signal (not shown) received by the control unit 62, and when the computer system 2 is normally powered off, the processing unit 61 notifies the control unit 62 to generate the first control signal C1 with the low logic level). When the control unit 62 receives the detection result D2 from the processing unit 61, the trigger signal Ts from the signal generating module 5, and the second control signal C2, the control unit 62 generates the delay selection signal Ds according to the detection result D2, and when the power supply module 22 is abnormally powered off, the control unit 62 continuously operates in response to the second control signal C2, generates a first power-down notification signal Pd1 and the control signal output Cout according to the detection result D2 and the trigger signal Ts, and transmits the first power-down notification signal Pd1 and the control signal output Cout to the processing unit 61 and the first memory unit 211, respectively. When the processing unit 61 receives the first power down notification signal Pd1, the processing unit 61 further controls the first memory unit 211 to enter a power saving mode according to the first power down notification signal Pd 1.
Referring to fig. 6, the timing of the relevant signals when the data storage determining apparatus 1 operates will be described. The parameters t0, t1 and t2 are time points, and the parameter t3 is a predetermined time.
Time t 0-time t 1: referring further to fig. 1, 3 and 5, the power supply module 22 is not abnormally powered off and the computer system 2 and the data storage determining device 1 are powered on and perform operations related to normal power-on. Since the operations related to normal booting are well known to those skilled in the art, they are not described herein. At this stage, the switching signal S1 is at the low logic level, and the switching unit 52 uses the power adjustment signal Pa as the second control signal C2. The processing unit 61 detects whether the memory module 21 includes the first memory unit 211 or the second memory unit to obtain the detection result D2, so that the control unit 62 generates the delay selection signal Ds (related to the length of the time interval for selecting the time interval during which the power adjusting unit 55 will continuously output the voltage signals when the power supply module 22 is abnormally powered off) according to the detection result D2, and the switching circuit 533 operates and generates the delay signal output Do according to the delay selection signal Ds. For example, in this embodiment, the memory module 21 belongs to the first memory cell 211, the detection result D2 and the delay selection signal Ds are at the high logic level (when the memory module 21 does not belong to the first memory cell 211, the detection result D2 and the delay selection signal Ds are at the low logic level), and therefore, the first delay signal De1 is fixed as the delay signal output Do (i.e., when the power supply module 22 is abnormally powered off, the power adjustment unit 55 continues to output the voltage signals for 600 us).
Time point t 1: when the power supply module 22 is abnormally powered down, the notification signal D1 is changed from the high logic level to the low logic level (i.e. the power supply module 22 does not receive the input power Vin and is abnormally powered down).
Time t 1-time t 2: at this time, the power supply module 22 is discharged by at least one component with residual power on its internal circuit board to continuously output the output power Vo. The first control signal C1 is at the high logic level for the predetermined period of time t3, so that the switch module 4 outputs the first power V1 to enable the first flip-flop 513 for the predetermined period of time t3, so that the first flip-flop 513 generates the pulse signal Ps, and the pulse signal Ps is triggered from the upper edge of the low logic level to the high logic level, which causes the switching signal S1 to also switch from the low logic level to the high logic level, so that the switching unit 52 switches the output power Vo as the second control signal C2, and the trigger signal Ts switches from the high logic level to the low logic level (i.e., the signal generating module 5 returns the first power V1 and the output power Vo to operate continuously). In this way, the control unit 62 knows that the power supply module 22 is abnormally powered off according to the trigger signal Ts, and generates the control signal output Cout and the first power down notification signal Pd1, so that the processing unit 61 controls the first memory unit 211 to enter the power saving mode according to the first power down notification signal Pd1, and the first memory unit 21 is enabled by the delay selection signal Ds, and stores the data currently received by the volatile memory therein into the nonvolatile memory therein according to the control signal output Cout.
It should be noted that, when the power supply module 22 is not abnormally powered off (i.e., the notification signal D1 output by the power supply module 22 is at the high logic level), and the computer system 2 is normally powered off, the processing unit 61 receives a power-off command and notifies the control unit 62, so that the control unit 62 converts the first control signal C1 from the high logic level to the low logic level, and the switch module 4 stops outputting the first power V1 to enable the first flip-flop 513. In this way, the trigger signal Ts generated by the signal generating module 5 will not be converted from the high logic level to the low logic level, and the control module 6 can be prevented from generating the control signal output Cout.
The second embodiment:
referring to fig. 7, a second embodiment of the data storage determining apparatus 1 of the present invention is similar to the first embodiment, except that: the memory module 21 includes the second memory unit 212; the detection result D2 generated by the processing unit 61 indicates that the memory module 21 is the second memory unit 212; the control unit 62 does not generate the control signal output Cout; when the power supply module 22 is abnormally powered off, the control unit 62 responds to the second control signal C2 to continuously operate, generates a second power-down notification signal Pd2 according to the detection result D2 and the trigger signal Ts, and transmits the second power-down notification signal Pd2 to the processing unit 61, so that the processing unit 61 generates the control signal output Cout according to the second power-down notification signal Pd2 and transmits the control signal output Cout to the second memory unit 212, so that the second memory unit 212 stores the currently received data in a non-volatile memory (not shown) therein according to the control signal output Cout. In this embodiment, the second memory cell 212 is an Apache Pass memory cell.
In summary, the switch module 4 and the signal generating module 5 are implemented by hardware circuits, the notification instruction D1 provided by the power supply module 22 and the switch module 4 and the signal generating module 5 of the present embodiment cooperate with each other to replace a complex programmable logic device provided by the prior art, and the total manufacturing cost of the power supply module 22, the switch module 4 and the signal generating module 5 is only half of the complex programmable logic device, so that the computer system 2 composed of the data storage determining device 1 according to the present embodiment has a lower cost compared to the existing computer system.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A data storage decision device, suitable for a computer system, the computer system includes a memory module including one of the first memory cell and the second memory cell, and a power supply module generating a DC output power according to an AC input power, the power supply module is also used to generate a notification signal indicating whether it receives the input power, when the power supply module is abnormally powered off, the notification signal is at a low logic level indicating that the power supply module does not receive the input power, and the data storage decision device generates a control signal output according to the output power and the notification signal to control the memory module to store the currently received data, the data storage decision device comprising:
the switch module receives a first control signal and is used for being electrically connected with the power supply module to receive the output power, and when the power supply module is abnormally powered off, the switch module is controlled by the first control signal and continuously outputs the output power for a preset time to be used as the first power;
a signal generating module electrically connected to the switch module and the power supply module for receiving the first power from the switch module, the output power from the power supply module and the notification signal, wherein when the power supply module is abnormally powered off, the signal generating module responds to the first power and the output power to continuously operate, generates a trigger signal related to the notification signal according to the notification signal and the output power, and generates a second control signal; and
a control module for receiving one of a power-on signal and a power-off command, generating the first control signal according to the received one of the power-on signal and the power-off command, electrically connected between the signal generation module and the memory module, detecting whether the memory module includes the first memory unit or the second memory unit to obtain a detection result, receiving the trigger signal and the second control signal from the signal generation module, generating the control signal output according to the detection result and the trigger signal, and transmitting the control signal output to the memory module.
2. The data storage determining apparatus of claim 1, wherein the memory module comprises the first memory unit, and the control module comprises:
a processing unit, for electrically connecting and detecting the type of the memory module to generate the detection result, wherein the detection result indicates that the memory module includes the first memory unit; and
a control unit for generating the first control signal, electrically connected to the processing unit and the signal generating module, receiving the detection result from the processing unit, and the trigger signal and the second control signal from the signal generating module, when the power supply module is abnormally powered off, the control unit responds to the second control signal to operate continuously, generates a first power down notification signal and the control signal output according to the detection result and the trigger signal, and transmits the first power down notification signal and the control signal output to the processing unit and the first memory unit, respectively;
when the processing unit receives the first power-down notification signal, the processing unit also controls the first memory unit to enter a power-saving mode according to the first power-down notification signal.
3. The data storage determination device of claim 1, wherein the memory module comprises the second memory unit, and the control module comprises:
a processing unit, for electrically connecting and detecting the type of the memory module to generate the detection result, wherein the detection result indicates that the memory module includes the second memory unit; and
and the control unit is used for generating the first control signal, is electrically connected with the processing unit and the signal generating module, receives the detection result from the processing unit, and the trigger signal and the second control signal from the signal generating module, responds to the second control signal to continuously operate when the power supply module is abnormally powered off, generates a second power-down notification signal according to the detection result and the trigger signal, and transmits the second power-down notification signal to the processing unit, so that the processing unit generates the control signal output according to the second power-down notification signal and transmits the control signal output to the second memory unit.
4. The data storage determining apparatus of claim 1, wherein the control module further generates a delay selection signal according to the detection result and outputs the delay selection signal to the signal generating module, the signal generating module comprising:
a signal generating unit electrically connected to the power supply module and the switch module, receiving the output power and the notification signal from the power supply module, and receiving the first power from the switch module, wherein when the power supply module is abnormally powered off, the signal generating unit responds to the first power and the output power to continuously operate, and generates the trigger signal and a switching signal according to the output power and the notification signal, and the phase of the switching signal is opposite to the phase of the notification signal;
a delay unit electrically connected with the control module and the power supply module to respectively receive the delay selection signal and the notification signal and generate a delay signal output according to the notification signal and the delay selection signal;
a logic gate unit electrically connected to the delay unit and the power supply module for receiving the delay signal output and the notification signal, respectively, and generating an output signal according to the delay signal output and the notification signal;
the power adjusting unit is electrically connected with the logic gate unit and the power supply module to respectively receive the output signal and the output power and generate a power adjusting signal according to the output power and the output signal; and
the switching unit is electrically connected with the power adjusting unit, the signal generating unit and the power supply module to respectively receive the power adjusting signal, the switching signal and the output power and generate the second control signal according to the switching signal.
5. The data storage determination device of claim 4, wherein the delay unit comprises:
a first delay circuit electrically connected to a detection module for receiving the notification signal and delaying the notification signal by a first time to generate a first delay signal;
the second delay circuit is electrically connected with the detection module to receive the notification signal and delay the notification signal for a second time to generate a second delay signal; and
a switching circuit electrically connected to the control module, the first delay circuit and the second delay circuit for receiving the delay selection signal and the first delay signal and the second delay signal from the control module and the first delay circuit and the second delay circuit, respectively, and generating the delay signal output accordingly, the switching circuit operating according to the delay selection signal, when the delay selection signal is at a high logic level, the first delay signal being output as the delay signal, and when the delay selection signal is at a low logic level, the second delay signal being output as the delay signal.
6. The data storage determination device of claim 4 wherein the logic gate unit is a back-gate unit.
7. The data storage determination device of claim 4, wherein the signal generation unit comprises:
the first inverter is electrically connected with the power supply module to receive the notification signal and generates an inverted signal according to the notification signal, and the phase of the inverted signal is inverted to that of the notification signal;
a first flip-flop having a data input terminal for receiving the output power, a clock input terminal electrically connected to the first inverter for receiving the inverted signal, a power input terminal electrically connected to the switch module for receiving the first power, and a non-inverted data output terminal, the first flip-flop generating a pulse signal at the non-inverted data output terminal according to the output power, the inverted signal, and the first power;
a second inverter electrically connected to the non-inverted data output terminal of the first flip-flop for receiving the pulse signal and generating the trigger signal according to the pulse signal, wherein the phase of the trigger signal is inverted with respect to the phase of the pulse signal; and
a second flip-flop having a data input terminal and a power input terminal electrically connected to each other and receiving the output power, a clock input terminal electrically connected to the non-inverted data output terminal of the first flip-flop to receive the pulse signal, and a non-inverted data output terminal, the second flip-flop generating the switching signal at the non-inverted data output terminal thereof according to the output power and the pulse signal.
8. The data storage determination device of claim 7 wherein the first flip-flop and the second flip-flop are each a D-type flip-flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810155392.7A CN110196678B (en) | 2018-02-23 | 2018-02-23 | Data storage determining device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810155392.7A CN110196678B (en) | 2018-02-23 | 2018-02-23 | Data storage determining device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110196678A CN110196678A (en) | 2019-09-03 |
| CN110196678B true CN110196678B (en) | 2022-09-30 |
Family
ID=67743939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810155392.7A Active CN110196678B (en) | 2018-02-23 | 2018-02-23 | Data storage determining device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110196678B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113707105B (en) * | 2021-08-18 | 2022-08-23 | Tcl华星光电技术有限公司 | Delay circuit and voltage control chip |
| CN117667534A (en) * | 2022-08-31 | 2024-03-08 | 深圳富联富桂精密工业有限公司 | Memory abnormality detection system, motherboard, electronic device and abnormality detection method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW553482U (en) * | 2002-12-18 | 2003-09-11 | Inventec Corp | Device to pre-detecting and handling the exhaust of battery power |
| CN1825248A (en) * | 2005-02-24 | 2006-08-30 | 英业达股份有限公司 | Power spare system for storage |
| US9588565B1 (en) * | 2013-06-28 | 2017-03-07 | EMC IP Holding Company LLC | Method and apparatus for data protection on embedded flash devices during power loss events |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101107152B1 (en) * | 2004-12-16 | 2012-02-06 | 삼성전자주식회사 | Memory storage apparatus for improvement in operation performance |
| TW200722997A (en) * | 2005-12-15 | 2007-06-16 | Inventec Corp | Method of protecting cache data of storage system |
| JP2008117000A (en) * | 2006-10-31 | 2008-05-22 | Nippon Digital Kenkyusho:Kk | Cache data protection apparatus and cache data protection method |
| WO2009107212A1 (en) * | 2008-02-28 | 2009-09-03 | 富士通株式会社 | Storage device, storage controller, and method for controlling storage |
| KR100963775B1 (en) * | 2008-08-01 | 2010-06-14 | 한양대학교 산학협력단 | Device and method for protecting data in non-volatile memory |
| US8468370B2 (en) * | 2009-09-16 | 2013-06-18 | Seagate Technology Llc | Systems, methods and devices for control of the operation of data storage devices using solid-state memory and monitoring energy used therein |
| CN103366815A (en) * | 2012-04-06 | 2013-10-23 | 鸿富锦精密工业（深圳）有限公司 | Power-off protection circuit and electronic device provided with same |
| CN203311406U (en) * | 2013-06-20 | 2013-11-27 | 瑞祺电通股份有限公司 | On-line synchronization backup device |
| CN104077246A (en) * | 2014-07-02 | 2014-10-01 | 浪潮(北京)电子信息产业有限公司 | Device for realizing volatile memory backup |
| US9437298B1 (en) * | 2015-03-25 | 2016-09-06 | Intel Corporation | Self-storing and self-restoring non-volatile static random access memory |
| US20180011714A1 (en) * | 2016-07-08 | 2018-01-11 | Super Micro Computer, Inc. | Graceful shutdown with asynchronous dram refresh of non-volatile dual in-line memory module |
| CN106708429B (en) * | 2016-11-24 | 2019-12-24 | 英业达科技有限公司 | Detection circuit |
-
2018
- 2018-02-23 CN CN201810155392.7A patent/CN110196678B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW553482U (en) * | 2002-12-18 | 2003-09-11 | Inventec Corp | Device to pre-detecting and handling the exhaust of battery power |
| CN1825248A (en) * | 2005-02-24 | 2006-08-30 | 英业达股份有限公司 | Power spare system for storage |
| US9588565B1 (en) * | 2013-06-28 | 2017-03-07 | EMC IP Holding Company LLC | Method and apparatus for data protection on embedded flash devices during power loss events |
Non-Patent Citations (3)
| Title |
|---|
| Data recovery from sudden power-off in mobile devices;Dongwook Kim等;《2012 IEEE 1st Global Conference on Consumer Electronics (GCCE 2012)》;20121231;全文 * |
| NVDIMM在分布式存储数据保护中的应用研究;惠润海;《中国优秀硕士学位论文全文数据库 信息科技辑》;20171031;第I137-8页 * |
| UPS注重降低成本延长供电时间;林芳明;《世界电子元器件》;19971115(第11期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110196678A (en) | 2019-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102030706B1 (en) | Dynamic Adaptive Voltage-Frequency Guardband Control Circuit | |
| US5336939A (en) | Stable internal clock generation for an integrated circuit | |
| US8912778B1 (en) | Switching voltage regulator employing current pre-adjust based on power mode | |
| US9329210B1 (en) | Voltage monitoring circuit | |
| US8593013B2 (en) | Switching control method capable of continuously providing power and related apparatus and power supply system | |
| KR20120095901A (en) | Clock turn-on strategy for power management | |
| KR20150116816A (en) | Pulse width modulation load share bus | |
| CN107799139B (en) | Duty ratio correction device and semiconductor device including the same | |
| CN110196678B (en) | Data storage determining device | |
| TWI668563B (en) | Data storage determining device | |
| CN109669524B (en) | Power-on reset circuit of chip | |
| US9501113B2 (en) | Voltage detection system and controlling method of the same | |
| US20130145193A1 (en) | Data processing device and data processing system | |
| US10664033B2 (en) | Power supply circuit | |
| CN107645288B (en) | Electronic circuit, method and electronic device for generating pulses | |
| US10033355B2 (en) | Electric power supply device and semiconductor device | |
| EP2847868A1 (en) | Inverter-and-switched-capacitor-based squelch detector apparatus and method | |
| CN109818411B (en) | Power switch circuit, chip and power supply system suitable for power supply sudden change | |
| US6870353B2 (en) | Power supply control circuit and LSI using the same | |
| US8402288B2 (en) | Apparatus and method for controlling voltage and frequency using multiple reference circuits | |
| CN110690689B (en) | Overcurrent protection device and method | |
| CN109765954B (en) | Method for controlling current flowing into circuit module and related chip | |
| US6888418B2 (en) | Control circuit and method for a crystal oscillator using a timer | |
| KR20160113396A (en) | Voltage Generating Circuit, Semiconductor Memory Apparatus Having the Same and Operating Method | |
| KR102548611B1 (en) | voltage detection system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |