CN104238627A - Method for realizing server power-on/off sequential control by using hardware circuit - Google Patents
Method for realizing server power-on/off sequential control by using hardware circuit Download PDFInfo
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- CN104238627A CN104238627A CN201410450751.3A CN201410450751A CN104238627A CN 104238627 A CN104238627 A CN 104238627A CN 201410450751 A CN201410450751 A CN 201410450751A CN 104238627 A CN104238627 A CN 104238627A
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Abstract
The invention discloses a method for realizing server power-on/off sequential control by using a hardware circuit. The method comprises the following steps: performing power-on sequential control: using a powerOK signal of a previous sequential power supply or a signal sent from PCH for controlling a POWERnable signal of each set of power supply, adding a set of RC delay circuit between the set of power-on power supply and the previous sequential power supply or the PCH, and sending a sequential signal to the CPU or PCH; performing power-off sequential control: adding two MOSFETs to a power-off circuit for forming a discharging circuit, pulling down a powerenable signal and sending the sequential signal to the CPU or PCH, thereby realizing the inverse power-off timing sequence and power-on timing sequence. Compared with the prior art, the method for realizing the server power-on/off sequential control by using the hardware circuit utilizes an IC and RC delay circuit to realize the accurate control on the power-on timing sequence. A discharging circuit is used for realizing the power-off sequential control, so that the cost and manpower time are saved.
Description
Technical field
The present invention relates to computer server technical field, specifically a kind of practical, use hardware circuit to realize the method for server power-on and power-off sequential control.
Background technology
Along with the maturation of computer server hardware design, while taking into account designing quality, also pursue and use the hardware circuit design more optimized to reduce costs.The power-on and power-off timing Design of traditional server is all realize in conjunction with CPLD chip, each important clock signal is (as RSM_RST#, SLP_S3#, PWROK etc.) and the POWER Enable signal of each group vital power supply and POWER OK signal all can be connected to CPLD, the sequential chart simultaneously just defined according to design writes the internal processes of CPLD chip, control the sequentially-operating that these signals require according to us from face, thus realize the power-on and power-off sequential of server design requirement.
This method for designing make hardware circuit design get up comparatively succinctly to facilitate.But CPLD chip price is expensive, CPLD program is complicated, and the people being ignorant of program language can not understand the design of sequential very soon, increases burden and the complexity of debugging and debug.And write and debug CPLD degree and also need to spend manpower extra in a large number and time.
Now because the large designer trends of server one are low costs, low-power consumption.CPU platform vendor, as the power frameworks such as Intel, ARM are succinct all gradually, timing Design is also relatively simple.
Based on this, now providing a kind of uses pure hardware circuit to realize the method for server power-on and power-off sequential control, the method can abandon the sequential that CPLD chip realizes CPU requirement, without the need to writing code, all kinds of basic electronic component of simple use controls the POWER Enable signal of each group of power supply signal relevant with sequential with other with POWER OK signal, realizes the normal electrifying timing sequence of server.
Summary of the invention
Technical assignment of the present invention is for above weak point, provide a kind of practical, use hardware circuit to realize the method for server power-on and power-off sequential control.
Use hardware circuit to realize a method for server power-on and power-off sequential control, its specific implementation process is:
Electrifying timing sequence controls: often organize the signal control that power supply POWER Enable signal uses the power OK signal of last order power supply or PCH to send, when this group power on power supply use last order power supply power OK signal control time, this group power on power supply and last order power supply between add one group of RC delay circuit, and send to CPU or PCH clock signal; When this group power on signal that power supply uses the PCH of last order to send control time, this group is powered on and is directly connected between power supply and the PCH of last order or is connected by one group of RC delay circuit, and sends to CPU or PCH clock signal;
Shutdown sequential control: increase by two field effect transistor M OS pipe composition discharge lines on power down circuit, to leave behind each group of power enable signal and send to CPU or PCH clock signal, realize power-off sequential contrary with electrifying timing sequence, namely the signal giving PCH and CPU first powers on and falls afterwards, after power on first fall.
The signal that in described electrifying timing sequence rate-determining steps, PCH sends comprises SLP_S5#, SLP_S3#; The clock signal of CPU and PCH is sent to comprise RSM_RST, SYS_PWROK, PWROK.
Described RC delay circuit is specially: at last order power supply or PCH and this resistance powered between power supply, the output terminal of this resistance is divided into two circuits, and one directly connects the power supply that powers on, and another is ground connection after electric capacity.
Described RC delay circuit is specially: the power supply output line on rear side of last order power supply or PCH is divided into three-line: one directly connects the power supply that powers on, and Article 2 exports through resistance, and Article 3 is ground connection after electric capacity.
Described discharge line is specially: signal input part connects the grid of metal-oxide-semiconductor Q1, the source ground of this metal-oxide-semiconductor Q1, and drain electrode is divided into three-line: one exports after resistance R1; , a ground connection after electric capacity C; Article one, connect the grid of metal-oxide-semiconductor Q2,
The source ground of this metal-oxide-semiconductor Q2, drain electrode is divided into two circuits: one exports through resistance R2, a connection signal output terminal.
A kind of method using hardware circuit to realize server power-on and power-off sequential control of the present invention, has the following advantages:
A kind of method using hardware circuit to realize server power-on and power-off sequential control of this invention uses time delay IC and the accurate control of RC delay circuit realization to electrifying timing sequence.Discharge line is used to realize the control of power-off sequential, cost and human time can be saved, abandon the sequential that CPLD chip realizes CPU requirement, without the need to writing code, all kinds of basic electronic component of simple use controls the POWER Enable signal of each group of power supply signal relevant with sequential with other with POWER OK signal, realizes the normal electrifying timing sequence of server; Practical, applied widely, be easy to promote.
Accompanying drawing explanation
Accompanying drawing 1 is that the signal that the power supply that powers on of the present invention is sent by last order power supply controls schematic diagram.
Accompanying drawing 2 is that the signal that the power supply that powers on of the present invention is sent by last order PCH controls schematic diagram.
Accompanying drawing 3 is the circuit diagram of delay line 1 in accompanying drawing 1 of the present invention.
Accompanying drawing 4 is the circuit diagram of delay line 2 in accompanying drawing 1 of the present invention.
Accompanying drawing 5 is lower electric sequential control schematic diagram of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
The invention provides a kind of method using hardware circuit to realize server power-on and power-off sequential control, as shown in accompanying drawing 1, Fig. 2, its specific implementation process is:
Electrifying timing sequence controls: often organize powering on of Power: the signal that the POWER Enable signal often organizing power supply can use the power OK signal of last order power supply or PCH to send controls.If there is the requirement of delay time, then add one group of RC delay circuit between the signals, the value of regulating resistance and electric capacity carrys out definition signal delay time.
Sending to the important clock signal of CPU and PCH, is also in reference signal, add suitable RC delay circuit or time delay IC according to the time of sequential chart definition.
Shutdown sequential control: Power off timing requirements is little, but in general requires that power-off sequential will turn around with electrifying timing sequence, will first power on to fall afterwards for the signal and part power giving PCH and CPU, after power on first fall.The delay circuit used when powering on can not meet this requirement completely, so power down needs other one group of hardware control lines to solve.
Power down circuit increases by two field effect transistor M OS pipe composition discharge lines, to leave behind each group of power enable signal and send to CPU or PCH clock signal, realize power-off sequential contrary with electrifying timing sequence, the signal namely giving PCH and CPU first powers on and falls afterwards, after power on first fall.
The realization of CPLD sequential function mainly by programming make signal realize time delay, non-, with etc. conversion, make from face signal below can make with reference to signal above the action meeting sequential chart, realize sequential control.
When realizing with hardware, non-, with or etc. can select suitable for door, or door, the little chip such as not gate realizes.And delay function can be realized by delay circuit.Delay time is short, and as several milliseconds, Microsecond grade can pass through RC delay circuit.Delay time hundreds of millisecond can select special time delay IC or reset IC.
Above-mentioned transistor, resistance, the chip price of electric capacity and simple function is cheap.Very simply, debugging is convenient, and need not manpower dedicated programmed for the RC delay circuit combined and discharge line design.Compared with use CPLD chip, cost significantly reduces, and saves human time.
The signal that in described electrifying timing sequence rate-determining steps, PCH sends comprises SLP_S5#, SLP_S3#; The clock signal of CPU and PCH is sent to comprise RSM_RST, SYS_PWROK, PWROK.
As shown in Figure 3, the first embodiment of described RC delay circuit is: at last order power supply or PCH and this resistance powered between power supply, the output terminal of this resistance is divided into two circuits, and one directly connects the power supply that powers on, and another is ground connection after electric capacity.
As shown in Figure 4, the second embodiment of described RC delay circuit is: the power supply output line on rear side of last order power supply or PCH is divided into three-line: one directly connects the power supply that powers on, and Article 2 exports through resistance, and Article 3 is ground connection after electric capacity.
As shown in Figure 5, described discharge line is specially: signal input part connects the grid of metal-oxide-semiconductor Q1, the source ground of this metal-oxide-semiconductor Q1, and drain electrode is divided into three-line: one exports after resistance R1; , a ground connection after electric capacity C; Article one, connect the grid of metal-oxide-semiconductor Q2,
The source ground of this metal-oxide-semiconductor Q2, drain electrode is divided into two circuits: one exports through resistance R2, a connection signal output terminal.
Above-mentioned embodiment is only concrete case of the present invention; scope of patent protection of the present invention includes but not limited to above-mentioned embodiment; any according to the invention a kind of use hardware circuit to realize claims of the method for server power-on and power-off sequential control and any person of an ordinary skill in the technical field to its suitable change done or replacement, all should fall into scope of patent protection of the present invention.
Claims (5)
1. use hardware circuit to realize a method for server power-on and power-off sequential control, it is characterized in that its specific implementation process is:
Electrifying timing sequence controls: often organize the signal control that power supply POWER Enable signal uses the power OK signal of last order power supply or PCH to send, when this group power on power supply use last order power supply power OK signal control time, this group power on power supply and last order power supply between add one group of RC delay circuit, and send to CPU or PCH clock signal; When this group power on signal that power supply uses the PCH of last order to send control time, this group is powered on and is directly connected between power supply and the PCH of last order or is connected by one group of RC delay circuit, and sends to CPU or PCH clock signal;
Shutdown sequential control: increase by two field effect transistor M OS pipe composition discharge lines on power down circuit, to leave behind each group of power enable signal and send to CPU or PCH clock signal, realize power-off sequential contrary with electrifying timing sequence, namely the signal giving PCH and CPU first powers on and falls afterwards, after power on first fall.
2. a kind of method using hardware circuit to realize server power-on and power-off sequential control according to claim 1, is characterized in that: the signal that in described electrifying timing sequence rate-determining steps, PCH sends comprises SLP_S5#, SLP_S3#; The clock signal of CPU and PCH is sent to comprise RSM_RST, SYS_PWROK, PWROK.
3. a kind of method using hardware circuit to realize server power-on and power-off sequential control according to claim 2, it is characterized in that: described RC delay circuit is specially: at last order power supply or PCH and this resistance powered between power supply, the output terminal of this resistance is divided into two circuits, article one, directly connect the power supply that powers on, another is ground connection after electric capacity.
4. a kind of method using hardware circuit to realize server power-on and power-off sequential control according to claim 2, it is characterized in that: described RC delay circuit is specially: the power supply output line on rear side of last order power supply or PCH is divided into three-line: one directly connects the power supply that powers on, Article 2 exports through resistance, and Article 3 is ground connection after electric capacity.
5. a kind of method using hardware circuit to realize server power-on and power-off sequential control according to claim 2, it is characterized in that: described discharge line is specially: signal input part connects the grid of metal-oxide-semiconductor Q1, the source ground of this metal-oxide-semiconductor Q1, drain electrode is divided into three-line: one exports after resistance R1; , a ground connection after electric capacity C; Article one, connect the grid of metal-oxide-semiconductor Q2,
The source ground of this metal-oxide-semiconductor Q2, drain electrode is divided into two circuits: one exports through resistance R2, a connection signal output terminal.
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Cited By (9)
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| WO2018045922A1 (en) * | 2016-09-07 | 2018-03-15 | 华为技术有限公司 | Backup power method and apparatus |
| CN109004923A (en) * | 2018-08-28 | 2018-12-14 | 深圳市新国都技术股份有限公司 | Sequential control circuit |
| CN110231862A (en) * | 2018-03-06 | 2019-09-13 | 佛山市顺德区顺达电脑厂有限公司 | Server system and its method with power-down protection |
| CN110660370A (en) * | 2019-09-16 | 2020-01-07 | 昆山龙腾光电股份有限公司 | Signal adjusting circuit and display device |
| CN110708172A (en) * | 2019-09-29 | 2020-01-17 | 杭州迪普科技股份有限公司 | Chip power-on sequence control method and device and electronic equipment |
| CN110781501A (en) * | 2019-10-10 | 2020-02-11 | 苏州浪潮智能科技有限公司 | Control circuit and server |
| CN111443788A (en) * | 2020-03-25 | 2020-07-24 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
| CN112421576A (en) * | 2020-10-30 | 2021-02-26 | 南京甄视智能科技有限公司 | Reverse connection prevention circuit of power supply |
| CN113241043A (en) * | 2021-05-08 | 2021-08-10 | 深圳市华星光电半导体显示技术有限公司 | Common voltage adjusting device and electronic equipment |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018045922A1 (en) * | 2016-09-07 | 2018-03-15 | 华为技术有限公司 | Backup power method and apparatus |
| CN110231862A (en) * | 2018-03-06 | 2019-09-13 | 佛山市顺德区顺达电脑厂有限公司 | Server system and its method with power-down protection |
| CN110231862B (en) * | 2018-03-06 | 2022-10-28 | 佛山市顺德区顺达电脑厂有限公司 | Server system with power failure protection function and method thereof |
| CN109004923A (en) * | 2018-08-28 | 2018-12-14 | 深圳市新国都技术股份有限公司 | Sequential control circuit |
| CN110660370A (en) * | 2019-09-16 | 2020-01-07 | 昆山龙腾光电股份有限公司 | Signal adjusting circuit and display device |
| CN110708172A (en) * | 2019-09-29 | 2020-01-17 | 杭州迪普科技股份有限公司 | Chip power-on sequence control method and device and electronic equipment |
| CN110781501A (en) * | 2019-10-10 | 2020-02-11 | 苏州浪潮智能科技有限公司 | Control circuit and server |
| CN111443788A (en) * | 2020-03-25 | 2020-07-24 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
| CN111443788B (en) * | 2020-03-25 | 2022-02-18 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
| CN112421576A (en) * | 2020-10-30 | 2021-02-26 | 南京甄视智能科技有限公司 | Reverse connection prevention circuit of power supply |
| CN113241043A (en) * | 2021-05-08 | 2021-08-10 | 深圳市华星光电半导体显示技术有限公司 | Common voltage adjusting device and electronic equipment |
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