CN110708172A - Chip power-on sequence control method and device and electronic equipment - Google Patents
Chip power-on sequence control method and device and electronic equipment Download PDFInfo
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Abstract
The application provides a chip power-on sequence control method and device, electronic equipment and a machine-readable storage medium. In the present application, a total power-on signal indicating the start of the network device is received; and responding to the total power-on signal, and sequentially controlling the specified power chips in the plurality of power chips to be powered on sequentially. Sequentially controlling the power-on and power-off of a specified power chip based on the logic hardware integrated by the network equipment; on one hand, the protection of the chip is improved, and the chip damage caused by the backward flow of current due to the fault of the power supply chip is prevented; on the other hand, the working state of the power supply chip is flexibly and conveniently displayed at low cost, and the efficiency of fault location is improved.
Description
Technical Field
The present application relates to the field of communications technologies and hardware technologies, and in particular, to a chip power-on sequence control method and apparatus, an electronic device, and a machine-readable storage medium.
Background
With the popularization of the internet and the mobile internet, the scale of the service data is larger and larger, and the network equipment for bearing the service data is more and more complex.
Generally, a network device may integrate a plurality of service boards, thereby implementing high-speed forwarding of network traffic; each service board is usually integrated with a service chip, such as: CPU, internal memory, clock chip, forwarding chip, etc. In addition, each service single board may also integrate an SoC (System-on-a-Chip) Chip; wherein, a plurality of chips are also integrated in the SoC chip.
In practical applications, in order to ensure that a plurality of service chips in a service single board or an SoC chip normally operate, power chips with different voltages deployed in network equipment are required to respectively supply power to the service single board or the SoC chip; each power supply chip needs to meet the voltage parameters of a plurality of service chips and also needs to meet the requirements of the power-on sequence of the service chips, so that adverse consequences of reverse current flowing, chip burning and the like caused by disorder of the power-on sequence are avoided.
Disclosure of Invention
The application provides a chip power-on sequence control method, which is applied to logic hardware integrated by network equipment, wherein the network equipment is also integrated with a plurality of service chips and a plurality of power chips for respectively supplying power to the service chips; the logic hardware and the power chips are connected and communicated on the basis of a hardware bus, and the method comprises the following steps:
receiving a total power-on signal indicating the network device is started;
and responding to the total power-on signal, and sequentially controlling the specified power chips in the plurality of power chips to be powered on sequentially.
Optionally, the power chips are power chips supporting power supply state feedback, and sequentially controlling designated power chips in the power chips to be sequentially powered on includes:
sending power-on enabling signals to the appointed power supply chip one by one so as to enable the appointed power supply chip to supply power;
receiving power supply state feedback signals sent by the appointed power supply chips one by one;
checking whether the power supply state feedback signals are normal one by one; and if the power supply state feedback signal is normal, sending a power-on enabling signal to the power supply chip corresponding to the next power-on sequence of the specified power supply chip until the power supply chips are powered on.
Optionally, the method further includes:
if the power supply state feedback signal is abnormal, sending a power-off enabling signal to the specified power supply chip so as to power off the specified power supply chip;
and sequentially sending power-down enabling signals to the power-up power chips in the appointed power chips one by one until all the power chips are powered off.
Optionally, the method further includes:
and indicating the corresponding working state of the specified power supply chip based on a preset indicator lamp.
The application also provides a chip power-on sequence control device, which is applied to logic hardware integrated by network equipment, and the network equipment also integrates a plurality of service chips and a plurality of power chips for respectively supplying power to the service chips; wherein, logic hardware and a plurality of power chips link to each other based on the hardware bus and communicate, the device includes:
a receiving module, which receives a total power-on signal indicating the start of the network equipment;
and the control module responds to the total power-on signal and sequentially controls the specified power chips in the plurality of power chips to be powered on sequentially.
Optionally, the power chips support power supply state feedback, and the control module further:
sending power-on enabling signals to the appointed power supply chip one by one so as to enable the appointed power supply chip to supply power;
receiving power supply state feedback signals sent by the appointed power supply chips one by one;
checking whether the power supply state feedback signals are normal one by one; and if the power supply state feedback signal is normal, sending a power-on enabling signal to the power supply chip corresponding to the next power-on sequence of the specified power supply chip until the power supply chips are powered on.
Optionally, the control module further:
if the power supply state feedback signal is abnormal, sending a power-off enabling signal to the specified power supply chip so as to power off the specified power supply chip;
and sequentially sending power-down enabling signals to the power-up power chips in the appointed power chips one by one until all the power chips are powered off.
Optionally, the method further includes:
and the diagnosis module is used for indicating the working state corresponding to the specified power supply chip based on a preset indicator lamp.
The application also provides an electronic device, which comprises a communication interface, a processor, a memory and a bus, wherein the communication interface, the processor and the memory are mutually connected through the bus;
the memory stores machine-readable instructions, and the processor executes the method by calling the machine-readable instructions.
The present application also provides a machine-readable storage medium having stored thereon machine-readable instructions which, when invoked and executed by a processor, implement the above-described method.
Through the embodiment, the appointed power supply chip is sequentially controlled to be powered on and powered off based on the logic hardware integrated by the network equipment; on one hand, the protection of the chip is improved, and the chip damage caused by the backward flow of current due to the fault of the power supply chip is prevented; on the other hand, the working state of the power supply chip is flexibly and conveniently displayed at low cost, and the efficiency of fault location is improved.
Drawings
FIG. 1 is a system architecture diagram of a network device provided by an exemplary embodiment;
FIG. 2 is a flowchart of a method for power-on sequence control on a chip according to an exemplary embodiment;
FIG. 3 is a schematic diagram of a power-on sequence control process on a chip provided by an exemplary embodiment;
FIG. 4 is a block diagram of an on-chip power-on sequence control apparatus provided in an exemplary embodiment;
fig. 5 is a hardware block diagram of an electronic device according to an exemplary embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
In order to make those skilled in the art better understand the technical solution in the embodiment of the present application, a brief description will be given below to the related technology of the chip power-on sequence control generation related to the embodiment of the present application.
Referring to fig. 1, fig. 1 is a system architecture diagram of a network device according to an embodiment of the present disclosure.
The network device shown in fig. 1 is integrated with logic hardware, a plurality of service chips (service chip 1, service chip 2, service chip 3), and a plurality of power supply chips (voltage chip 1, voltage chip 2, voltage chip 3) for respectively supplying power to the plurality of service chips; the logic hardware and the power chips are connected and communicated on the basis of a hardware bus.
On the basis of the system architecture of the network equipment, the technical scheme is used for sequentially controlling the power supply chips to be powered on based on the logic hardware sequence.
In the implementation process, the network equipment is integrated with logic hardware, and the network equipment is also integrated with a plurality of service chips and a plurality of power supply chips for respectively supplying power to the service chips; the logic hardware and the power chips are connected and communicated on the basis of a hardware bus.
Further, the logic hardware receives a total power-up signal indicating the network device is powered up; and responding to the total power-on signal, and sequentially controlling the specified power chips in the plurality of power chips to be powered on sequentially.
In the scheme, the appointed power supply chip is sequentially controlled to be powered on and powered off based on the logic hardware integrated by the network equipment; on one hand, the protection of the chip is improved, and the chip damage caused by the backward flow of current due to the fault of the power supply chip is prevented; on the other hand, the working state of the power supply chip is flexibly and conveniently displayed at low cost, and the efficiency of fault location is improved.
The present application is described below with reference to specific embodiments and specific application scenarios.
Referring to fig. 2, fig. 2 is a flowchart of a method for controlling a power-on sequence of a chip according to an embodiment of the present application, where the method is applied to logic hardware integrated by a network device, and the network device further integrates a plurality of service chips and a plurality of power chips for respectively supplying power to the plurality of service chips; the logic hardware and the power chips are connected and communicated based on a hardware bus, and the method comprises the following steps:
And 204, responding to the total power-on signal, and sequentially controlling the specified power chips in the plurality of power chips to be powered on sequentially.
In this specification, the logic hardware may include any form of programmable logic device.
For example, in practical applications, the logic hardware may include a CPLD (Complex Programmable logic device), an FPGA (Field Programmable Gate Array), and the like.
In this specification, the network device may include any form of network device integrated with the logic hardware.
For example, in practical applications, the network device may include a switch, a router, a firewall, and the like, which are integrated with the logic hardware.
In this specification, the service chips may include a plurality of chips for any service purpose integrated on the network device.
For example, in practical applications, the service chips may include a CPU, a memory, a clock chip, a forwarding chip, and the like integrated on the network device; the service chips may further include an SoC chip integrated with the network device.
In this specification, the plurality of power chips may include a plurality of power chips for respectively supplying power to the plurality of service chips.
For example, in practical applications, the power chips are a plurality of chips integrated inside a CPU, a memory, a clock chip, a forwarding chip, an SoC chip, and the power chips are used for supplying power respectively.
In this specification, the power chips may output different voltage parameters.
For example, in practical applications, the power chips may output 12 volts, 5 volts, 3 volts, 1.5 volts, and so on.
In this specification, the network device integrates the plurality of service chips and the plurality of power chips in addition to the logic hardware;
the logic hardware and the power chips are connected and communicated based on a hardware bus.
For example, please refer to fig. 1 for an example of the system architecture of the network device, which has been described in detail above and is not described herein again.
In this specification, when the network device is powered on and started, the network device may trigger a total power-on signal indicating the start of the network device;
the total power-on signal may be one or more hardware signals that may be output by the network device.
For example, in practical applications, when the network device starts to power up when the network device is powered on, the network device may output the total power-up signal indicating the start of the network device when the network device starts to power up.
Referring to fig. 3, fig. 3 is a schematic diagram of a process for controlling a power-on sequence of a chip according to an embodiment of the present disclosure.
As shown in fig. 3, the logic hardware is connected to a plurality of power chips (power chip 1, power chip 2, power chip 3,.. and power chip N) through hardware buses respectively;
wherein, EN1, EN2, EN3, EN (n is a natural number) are power-on enable signals for the logic hardware to output to a plurality of power supply chips; when the power chip receives the power-on enabling signal, power can be supplied to the corresponding service chip.
PG1, PG2, PG3, and PGn (n is a natural number) are power supply state feedback signals output by a plurality of power supply chips to logic hardware.
For convenience of understanding, the power supply state feedback signal, also referred to in the industry as the PowerGood signal, is introduced here first, and may be used to indicate whether the output voltage of the power supply chip is within the rated operating range; if so, the power supply chip can output a Powergood normal signal indicating that the output voltage of the power supply chip is normal and has a high level; otherwise, the power supply chip may output a low-level PowerGood fault signal indicating that the output voltage of the power supply chip is abnormal.
As shown in fig. 3, the power chip 0 is a power chip for supplying power to the logic hardware, the indicator light 1 and the indicator light 2; the indicator light 1 and the indicator light 2 are connected with the logic hardware, and can be controlled by the logic hardware to execute state indication including light-on, light-off, flashing according to preset frequency and the like.
In this specification, the designated power chip refers to a power chip having a power-on sequence requirement among the plurality of power chips.
For example, referring to fig. 3, the power supply chip may include a power supply chip 1, a power supply chip 2, a power supply chip 3, · and a power supply chip N; the power-on sequence of the power chip 1 to the power chip N is required to be from first to last.
For another example, as shown in fig. 3, the power supply chip may include a power supply chip 3, a power supply chip 2, and a power supply chip 1; the power-on sequence from the power chip 3 to the power chip 1 is required to be from first to last; and the power-on sequence requirements of the power chips 4 to N can be simultaneous or out of order.
In this specification, the logic hardware receives a signal indicative of the overall power-up; and responding to the total power-on signal, and sequentially controlling the specified power chips in the plurality of power chips to be powered on sequentially.
In one embodiment, the power chips are power chips supporting power supply state feedback.
For example, referring to fig. 3, the power chips shown in fig. 3 support power chips with power supply state feedback; the power supply state feedback signals (PG1, PG2, PG3, PGn) output by the power supply chips to the logic hardware; the power supply state feedback signal may be a PowerGood normal signal indicating that the output voltage of the power supply chip is at a normal high level or a PowerGood fault signal indicating that the output voltage of the power supply chip is at an abnormal low level.
In this specification, in a process in which the logic hardware sequentially controls the designated power source chips to be sequentially powered on, the logic hardware sends power-on enable signals to the designated power source chips one by one, so that the designated power source chips supply power.
For example, referring to fig. 3, the designated power chips may include a power chip 1, a power chip 2, a power chip 3, · and a power chip N; the power-on sequence of the power chip 1 to the power chip N is required to be from first to last. The logic hardware firstly sends a power-on enabling signal EN1 to the power chip 1; so that the power chip 1 supplies power to the corresponding service chip.
In this specification, the logic hardware may further receive power supply state feedback signals sent by the designated power supply chip one by one.
Continuing the example following the above example, the above logic hardware receives the power supply state feedback signal PG1 sent by the power chip 1; the power supply state feedback signal PG1 may be a PowerGood normal signal or a PowerGood fault signal.
In this specification, the logic hardware may further check whether the power supply state feedback signal is normal one by one; and if the power supply state feedback signal is normal, sending a power-on enabling signal to the power supply chip corresponding to the next power-on sequence of the specified power supply chip until the power supply chips are powered on.
Continuing the example following the above example, the above logic hardware checks whether the power supply state feedback signal PG1 of the power chip 1 is normal; if the power supply state feedback signal PG1 is a PowerGood normal signal, a power-on enable signal EN2 is sent to the power chip 1 corresponding to the power chip 2 in the next power-on sequence, so that the power chip 2 supplies power to the corresponding service chip, and so on until the power chip N is powered on.
In an embodiment shown in the above, in the process of sequentially controlling the power-on of the designated power chips by the logic hardware, if the power supply state feedback signal is abnormal, a power-off enable signal is sent to the designated power chip to power off the designated power chip.
Continuing with the above example, the above-mentioned designated power chips include power chip 1, power chip 2, power chip 3. The power chip with the power-on appointed power chip comprises a power chip 1, a power chip 2 and a power chip 3; when the power supply state feedback signal PG3 received from the power supply chip 3 is a PowerGood abnormal signal, the logic hardware sends a power-off enable signal to the power supply chip 3, so that the power supply chip 3 is powered off.
In this specification, further, the logic hardware sequentially sends power-down enable signals to the power-up power chips in the designated power chips one by one until all the power chips are powered off.
Continuing the example from the above example, the logic hardware sequentially sends power-down enabling signals to the power chips 2 and 1 that have been powered up in the designated power chips one by one until all the power chips are powered off.
It should be noted that the power-down enable signal and the power-up enable signal sent by the logic hardware to the specific power supply chip may be signals with opposite levels, such as: the power-up enable signal is at a high level, and the power-down enable signal is at a low level. The logic hardware controls the sequence of the specified power supply chips to be powered off in sequence, and the sequence is opposite to the sequence of the logic hardware controlling the specified power supply chips to be powered on in sequence.
In this specification, the indicator light may include an indicator light controlled by logic hardware to perform status indication such as lighting, turning off the light, and flashing at a preset frequency.
For example, in practical applications, the indicator light may include at least five states: 1. normally bright; 2. normally going out; 3. flash at a frequency of 0.25HZ (once in 4 seconds); 4. blinking at a frequency of 1HZ (once in 1 second); 5. flicker at a frequency of 8HZ (once in 0.125 seconds).
In an embodiment shown, the logic hardware indicates a working state corresponding to the designated power chip based on presetting the indicator light;
continuing with the above example, referring to fig. 3, the logic hardware may communicate with indicator light 1 and indicator light 2 via a hardware bus; wherein, each indicator light comprises at least 5 states, and the two indicator lights can comprise 25 states; the above-mentioned logic hardware may use the 25 states to indicate that the corresponding operating states of the power chip 1, the power chip 2, the power chip 3.
Of course, in practical applications, if two indicator lights are not enough, the indicator lights can be further expanded, and the number of the indicator lights and the status indication type of the lights are not particularly limited in this specification.
In this specification, after the logic hardware indicates the operating state corresponding to the designated power chip based on the preset indicator lamp, a user can visually judge the power chip with a fault by observing the operating state of the indicator lamp, and the efficiency of locating the fault is improved.
For example, the two indicator lamps indicate the corresponding working states of the power supply chip, so that compared with the existing digital tubes (at least 2 × 7I/O signals need to be used) or the single digital indicator lamp (at least 25I/O signals need to be used), a large amount of I/O resources are saved, and the hardware design space is saved.
In the technical scheme, the appointed power supply chip is sequentially controlled to be powered on and powered off based on the logic hardware integrated by the network equipment; on one hand, the protection of the chip is improved, and the chip damage caused by the backward flow of current due to the fault of the power supply chip is prevented; on the other hand, the working state of the power supply chip is flexibly and conveniently displayed at low cost, and the efficiency of fault location is improved.
Fig. 4 is a block diagram of an on-chip power-on sequence control apparatus according to an exemplary embodiment of the present application. Corresponding to the above method embodiments, the present application further provides an embodiment of a device for controlling a power-on sequence of a chip, where the device is applied to a logic hardware integrated by a network device, the network device further integrates a plurality of service chips and a plurality of power chips for respectively supplying power to the plurality of service chips, please refer to an exemplary device 40 for controlling a power-on sequence of a chip illustrated in fig. 4, and the device includes:
a receiving module 401, configured to receive a total power-on signal indicating that the network device is started;
the control module 402 sequentially controls specific power chips among the plurality of power chips to be sequentially powered on in response to the total power-on signal.
In this embodiment, the power chips are power chips supporting power supply state feedback, and the control module 402 further:
sending power-on enabling signals to the appointed power supply chip one by one so as to enable the appointed power supply chip to supply power;
receiving power supply state feedback signals sent by the appointed power supply chips one by one;
checking whether the power supply state feedback signals are normal one by one; and if the power supply state feedback signal is normal, sending a power-on enabling signal to the power supply chip corresponding to the next power-on sequence of the specified power supply chip until the power supply chips are powered on.
In this embodiment, the control module 402 further:
if the power supply state feedback signal is abnormal, sending a power-off enabling signal to the specified power supply chip so as to power off the specified power supply chip;
and sequentially sending power-down enabling signals to the power-up power chips in the appointed power chips one by one until all the power chips are powered off.
In this embodiment, the method further includes:
and the diagnosis module 403 indicates the corresponding working state of the specified power supply chip based on a preset indicator lamp.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, wherein the modules described as separate parts may or may not be physically separate, and the parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The systems, devices, modules or modules illustrated in the above embodiments may be implemented by a computer chip or an entity, or by an article of manufacture with certain functionality. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.
The embodiment of the device for controlling the power-on sequence of the chip in the present application can be applied to the electronic device shown in fig. 5. The device embodiments may be implemented by software, or by hardware, or by a combination of hardware and software. Taking a software implementation as an example, as a logical device, the device is a machine executable instruction formed by reading a corresponding computer program instruction in a machine readable storage medium through a processor of the electronic device where the device is located and then running the computer program instruction. In terms of hardware, as shown in fig. 5, a hardware structure diagram of an electronic device where a chip power-on sequence control apparatus of the present application is located is shown, except for the processor, the communication interface, the bus, and the machine-readable storage medium shown in fig. 5, the electronic device where the apparatus is located in the embodiment may also include other hardware according to the actual function of the electronic device, which is not described again.
Correspondingly, an embodiment of the present application further provides a hardware structure of an electronic device of the apparatus shown in fig. 4, please refer to fig. 5, and fig. 5 is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. The apparatus comprises: a communication interface 501, a processor 502, a machine-readable storage medium 503, and a bus 504; the communication interface 501, the processor 502 and the machine-readable storage medium 503 are configured to communicate with each other via a bus 504. The communication interface 501 is used for performing network communication. The processor 502 may be a Central Processing Unit (CPU), and the processor 502 may execute machine-readable instructions stored in the machine-readable storage medium 503 to implement the methods described above.
The machine-readable storage medium 503 referred to herein may be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, and the like. For example, the machine-readable storage medium may be: volatile memory, non-volatile memory, or similar storage media. In particular, the machine-readable storage medium 503 may be a RAM (random Access Memory), a flash Memory, a storage drive (e.g., a hard disk drive), a solid state disk, any type of storage disk (e.g., a compact disk, a DVD, etc.), or similar storage medium, or a combination thereof.
To this end, the description of the hardware configuration shown in fig. 5 is completed.
Furthermore, the present application also provides a machine-readable storage medium, such as machine-readable storage medium 503 in fig. 5, including machine-executable instructions, which can be executed by processor 502 in the data processing apparatus to implement the data processing method described above.
The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (10)
1. A chip power-on sequence control method is characterized in that the method is applied to logic hardware integrated by network equipment, and the network equipment is also integrated with a plurality of service chips and a plurality of power supply chips for respectively supplying power to the service chips; the logic hardware and the power chips are connected and communicated on the basis of a hardware bus, and the method comprises the following steps:
receiving a total power-on signal indicating the network device is started;
and responding to the total power-on signal, and sequentially controlling the specified power chips in the plurality of power chips to be powered on sequentially.
2. The method of claim 1, wherein the plurality of power chips are power chips supporting power supply state feedback, and the sequentially controlling power chips of the plurality of power chips to be sequentially powered up comprises:
sending power-on enabling signals to the appointed power supply chip one by one so as to enable the appointed power supply chip to supply power;
receiving power supply state feedback signals sent by the appointed power supply chips one by one;
checking whether the power supply state feedback signals are normal one by one; and if the power supply state feedback signal is normal, sending a power-on enabling signal to the power supply chip corresponding to the next power-on sequence of the specified power supply chip until the power supply chips are powered on.
3. The method of claim 2, further comprising:
if the power supply state feedback signal is abnormal, sending a power-off enabling signal to the specified power supply chip so as to power off the specified power supply chip;
and sequentially sending power-down enabling signals to the power-up power chips in the appointed power chips one by one until all the power chips are powered off.
4. The method of claim 3, further comprising:
and indicating the corresponding working state of the specified power supply chip based on a preset indicator lamp.
5. The device is applied to logic hardware integrated by network equipment, and the network equipment is also integrated with a plurality of service chips and a plurality of power supply chips for respectively supplying power to the service chips; wherein, logic hardware and a plurality of power chips link to each other based on the hardware bus and communicate, the device includes:
a receiving module, which receives a total power-on signal indicating the start of the network equipment;
and the control module responds to the total power-on signal and sequentially controls the specified power chips in the plurality of power chips to be powered on sequentially.
6. The apparatus of claim 5, wherein the power chips are power chips that support power state feedback, and wherein the control module is further to:
sending power-on enabling signals to the appointed power supply chip one by one so as to enable the appointed power supply chip to supply power;
receiving power supply state feedback signals sent by the appointed power supply chips one by one;
checking whether the power supply state feedback signals are normal one by one; and if the power supply state feedback signal is normal, sending a power-on enabling signal to the power supply chip corresponding to the next power-on sequence of the specified power supply chip until the power supply chips are powered on.
7. The apparatus of claim 6, wherein the control module is further to:
if the power supply state feedback signal is abnormal, sending a power-off enabling signal to the specified power supply chip so as to power off the specified power supply chip;
and sequentially sending power-down enabling signals to the power-up power chips in the appointed power chips one by one until all the power chips are powered off.
8. The apparatus of claim 7, further comprising:
and the diagnosis module is used for indicating the working state corresponding to the specified power supply chip based on a preset indicator lamp.
9. An electronic device is characterized by comprising a communication interface, a processor, a memory and a bus, wherein the communication interface, the processor and the memory are connected with each other through the bus;
the memory has stored therein machine-readable instructions, the processor executing the method of any of claims 1 to 4 by calling the machine-readable instructions.
10. A machine-readable storage medium having stored thereon machine-readable instructions which, when invoked and executed by a processor, carry out the method of any of claims 1 to 4.
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| CN201910935307.3A CN110708172A (en) | 2019-09-29 | 2019-09-29 | Chip power-on sequence control method and device and electronic equipment |
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| CN201910935307.3A CN110708172A (en) | 2019-09-29 | 2019-09-29 | Chip power-on sequence control method and device and electronic equipment |
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Cited By (7)
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| CN112152736A (en) * | 2020-09-22 | 2020-12-29 | Oppo（重庆）智能科技有限公司 | Client front-end device, failure detection method for client front-end device, and storage medium |
| CN112286333A (en) * | 2020-10-16 | 2021-01-29 | 锐捷网络股份有限公司 | Power supply control method and device |
| CN112558742A (en) * | 2020-12-15 | 2021-03-26 | 深兰人工智能(深圳)有限公司 | Power-on control method, programmable logic device and power-on control system |
| CN112925380A (en) * | 2021-02-04 | 2021-06-08 | 烽火通信科技股份有限公司 | Complex communication equipment control method, device, equipment and storage medium |
| CN113114413A (en) * | 2021-03-03 | 2021-07-13 | 杭州迪普科技股份有限公司 | Indicator lamp control method and device |
| CN113341827A (en) * | 2021-06-18 | 2021-09-03 | 南昌华勤电子科技有限公司 | Control method and device of power supply chip |
| CN113923457A (en) * | 2021-08-27 | 2022-01-11 | 苏州浪潮智能科技有限公司 | System and method for off-peak power-up of video transcoding card |
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| CN113114413A (en) * | 2021-03-03 | 2021-07-13 | 杭州迪普科技股份有限公司 | Indicator lamp control method and device |
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| CN113923457A (en) * | 2021-08-27 | 2022-01-11 | 苏州浪潮智能科技有限公司 | System and method for off-peak power-up of video transcoding card |
| CN113923457B (en) * | 2021-08-27 | 2023-07-14 | 苏州浪潮智能科技有限公司 | System and method for video transcoding card peak staggering power-on |
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