CN112558742A - Power-on control method, programmable logic device and power-on control system - Google Patents
Power-on control method, programmable logic device and power-on control system Download PDFInfo
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Abstract
The application provides a power-on control method, a programmable logic device and a power-on control system, which are suitable for power-on control of a power supply device comprising at least two power supply chips, wherein an enabling signal is output to any power supply chip with power-on priority in the power supply device to be powered on; then receiving a feedback signal of the power chip with any power-on priority based on the enabling signal; and finally, if the received feedback signal is determined to be normal, outputting an enabling signal to a power chip of the next power-on priority of any power-on priority. Therefore, the power supply chips of each power-on priority in the power supply device can be sequentially controlled and judged to accurately control the starting time sequence of the power supply chips of each power-on priority, the starting of the power supply chips under various complex environments can meet the time sequence requirement, and the system where the power supply device is located can be normally started and operated.
Description
Technical Field
The present disclosure relates to the field of control circuits, and in particular, to a power-on control method, a programmable logic device, and a power-on control system.
Background
The cards designed according to the large-scale integrated circuits including CPUs and the like generally include a plurality of power chips. In the card board, not only are strict requirements on parameters such as voltage of the power supply chips, but also strict requirements on power-up and power-down timing sequences among the power supply chips are often required, namely, the power supply chips are controlled to be powered up and powered down according to a specific sequence.
When the cardboard needs to be debugged, the problems such as hot plug and the like are inevitably encountered. When the card board is inserted into a certain slot position of the target equipment, the power-on process among all power chips on the card board is controllable. The power supply chip is controlled by a resistance-capacitance (RC) delay circuit most often, the enabling signals of the power supply chip are controlled by using different resistance-capacitance values and different delay times, the first-stage power supply chip is smaller in capacitance value and preferentially enables power-on, the second-stage power supply chip is increased in capacitance value, and the enabling signals have delay compared with the first-stage power supply chip so as to achieve different power-on time sequences. This control method is low in cost and simple to use, but the logic threshold of the enable pin may have a large difference due to voltage and temperature. Furthermore, the delay in the voltage ramp depends on the resistance and capacitance values and tolerances. The typical range of capacitance temperature varies by about 20%, which makes the timing control inaccurate, resulting in inaccurate and sometimes unreliable control results.
Disclosure of Invention
The application provides a power-on control method, a programmable logic device and a power-on control system, which are used for accurately controlling the starting time sequence of each power chip with power-on priority, and the starting of the power chips under various complex environments can meet the time sequence requirement, so that the system where a power supply device is located can be normally started and operated.
The application provides a power-on control method, which is suitable for power-on control of a power supply device comprising at least two power supply chips, and comprises the following steps:
outputting an enabling signal to a power chip with any power-on priority in a power device to be powered on, wherein any power-on priority does not include the lowest power-on priority;
receiving a feedback signal of the power chip with any power-on priority based on the enabling signal;
and if the received feedback signal is determined to be normal, outputting an enabling signal to a power chip of the next power-on priority of any power-on priority.
According to the present application, a power-on control method is provided, which further includes:
outputting an enabling signal to a power supply chip in the power supply device step by step according to the sequence from the highest power-on priority to the lowest power-on priority;
receiving feedback signals of the power chips of the power-on priorities based on the enabling signals;
and if the feedback signals corresponding to all the power chips in the power supply device are determined to be normal, outputting a reset signal to a system where the power supply device is located, and electrifying the system.
According to a power-on control method provided by the present application, after receiving a feedback signal of the power chip of any power-on priority based on the enable signal, the method further includes: and if the received feedback signal is abnormal, alarming and prompting.
According to a power-on control method provided by the present application, the outputting an enable signal to any power chip with a power-on priority in a power device to be powered on further includes: and judging whether the received feedback signal is normal or not based on a preset standard feedback signal of the power supply chip with any power-on priority.
According to the power-on control method provided by the application, the judging whether the received feedback signal is normal or not based on the preset standard feedback signal of the power chip with any power-on priority comprises the following specific steps:
if the received feedback signal is consistent with the power-on feedback signal in the standard feedback signal, judging that the received feedback signal is normal;
otherwise, judging that the received feedback signal is abnormal.
The present application further provides a power-on control unit, adapted to power-on control of a power supply device including at least two power chips, including: the device comprises an output module and a receiving module. Wherein the content of the first and second substances,
the output module is used for outputting an enabling signal to any power chip with a power-on priority in the power supply device to be powered on, wherein any power-on priority does not include the lowest power-on priority;
the receiving module is used for receiving a feedback signal of any power chip with the power-on priority based on the enabling signal;
and the output module is further used for outputting an enabling signal to a power chip of a next power-on priority of any power-on priority if the received feedback signal is determined to be normal.
According to the power-on control unit provided by the application, the output module is further configured to: outputting an enabling signal to a power supply chip in the power supply device step by step according to the sequence from the highest power-on priority to the lowest power-on priority;
the receiving module is further configured to: receiving feedback signals of the power chips of the power-on priorities based on the enabling signals;
correspondingly, the power-on control unit further comprises a power-on module, configured to:
and if the feedback signals corresponding to all the power chips in the power supply device are determined to be normal, outputting a reset signal to a system where the power supply device is located, and electrifying the system.
According to the application, the power-on control unit further comprises an alarm prompting module, which is used for:
and if the received feedback signal is abnormal, alarming and prompting.
According to the present application, a power-on control unit further includes a determining module, configured to:
and judging whether the received feedback signal is normal or not based on a preset standard feedback signal of the power supply chip with any power-on priority.
According to the power-on control unit provided by the application, the judging module is specifically configured to:
if the received feedback signal is consistent with the power-on feedback signal in the standard feedback signal, judging that the received feedback signal is normal;
otherwise, judging that the received feedback signal is abnormal.
The present application also provides a programmable logic device, comprising: the power-on control unit comprises a power-on control unit, a plurality of enabling pins and receiving pins corresponding to the enabling pins, wherein the power-on control unit is respectively connected with the enabling pins and the receiving pins;
each enable pin corresponds to one power chip in the power device to be powered on.
The present application further provides a power-on control system, including: the programmable logic device is respectively connected with each power chip with power-on priority in the power device to be powered on and the power module; the power supply module is used for supplying power to the programmable logic device and the power supply chip.
The present application further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any of the power-on control methods described above when executing the computer program.
The present application also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the power-on control method as in any one of the above.
The power-on control method, the programmable logic device and the power-on control system are suitable for power-on control of a power supply device comprising at least two power supply chips, and are characterized in that an enabling signal is output to any power supply chip with a power-on priority in the power supply device to be powered on, wherein any power-on priority does not comprise the lowest power-on priority; then receiving a feedback signal of the power chip with any power-on priority based on the enabling signal; and finally, if the received feedback signal is determined to be normal, outputting an enabling signal to a power chip of the next power-on priority of any power-on priority. Therefore, the power supply chips of each power-on priority in the power supply device can be sequentially controlled and judged to accurately control the starting time sequence of the power supply chips of each power-on priority, the starting of the power supply chips under various complex environments can meet the time sequence requirement, and the system where the power supply device is located can be normally started and operated.
Drawings
In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram of a power-on control method provided in the present application;
FIG. 2 is a schematic flow chart diagram of a power-on control method provided in the present application;
FIG. 3 is a schematic flow chart diagram of a power-on control method provided in the present application;
FIG. 4 is a schematic flow chart diagram illustrating a power-up control method provided herein;
FIG. 5 is a schematic structural diagram of a power-on control unit provided in the present application;
FIG. 6 is a schematic structural diagram of a power-on control unit provided in the present application;
FIG. 7 is a schematic structural diagram of a power-on control unit provided in the present application;
FIG. 8 is a schematic structural diagram of a power-on control unit provided in the present application;
FIG. 9 is a schematic diagram of a programmable logic device provided herein;
FIG. 10 is a schematic diagram of a programmable logic device provided herein;
FIG. 11 is a schematic structural diagram of a power-on control system provided herein;
fig. 12 is a schematic structural diagram of an electronic device provided in the present application.
Detailed Description
To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic flow chart of a power-on control method provided in an embodiment of the present application, and as shown in fig. 1, the method includes:
s1, outputting an enabling signal to any power chip with power-on priority in the power device to be powered on, wherein any power-on priority does not include the lowest power-on priority;
s2, receiving a feedback signal of the power chip with any power-on priority based on the enabling signal;
and S3, if the received feedback signal is determined to be normal, outputting an enabling signal to a power chip of the next power-on priority of any power-on priority.
Specifically, an execution main body of the power-on control method provided in the embodiment of the present application is an editable Logic device, which may specifically be a cpld (complex Programmable Logic device), an fpga (field Programmable Gate array), or another type of Programmable Logic device, and this is not specifically limited in the embodiment of the present application.
Step S1 is performed first, before which the power-on priority of the power chip in the power supply apparatus to be powered on may be configured in the editable logic device, where differentiation may be achieved by identifying different power-on priorities. When only the power supply chip with the first-level power-on priority exists in the power supply device to be powered on, the power-on priority of the power supply chip does not need to be identified. When at least two power supply chips with power-on priorities exist in the power supply device to be powered on, the power-on priorities can be identified according to the power-on sequence of the power supply chips. For example, the power-on priority may be identified by using numbers from small to large according to the power-on sequence of the power chip, or by using numbers from large to small according to the power-on sequence of the power chip, which is not specifically limited in this embodiment of the present application. When the power-on priorities of the power chips are configured in the editable logic device, the power-on priorities of the power chips in the power device to be powered on are determined according to the control sequence of the main chip in the system where the power device to be powered on is located, and then the determined power-on priorities are configured in the editable logic device.
The programmable logic device outputs the enable signal to any power chip with power-on priority in the power supply device to be powered on, specifically, the enable signal may be output to all power chips with any power-on priority in the power supply device in sequence. Wherein any power-on priority is other than the lowest power-on priority because there is no next power-on priority to the lowest power-on priority. The programmable logic device can be configured with power-on time sequences of different power chips in the power supply device, and power-on control of the power chips is realized by outputting an enable signal to each power chip. The power supply device includes a plurality of power supply chips, different power supply chips have the same or different power-on priorities, and the power-on priorities of the power supply chips may be set according to services, which is not specifically limited in this embodiment of the present application. The power chips in the same power-on priority receive the enable signal output by the editable logic device at the same time. The power supply chip with higher power-on priority receives the enabling signal output by the editable logic device before the power supply chip with lower power-on priority.
Because each power chip has a work enabling end and an output end, the power chip can be powered on to start work when the received enabling signal is at a high level or a low level by receiving the enabling signal through the work enabling end. The output end is used for outputting a feedback signal, and the feedback signal is used for indicating whether the power supply chip is successfully electrified or not. For example, when the feedback signal is pulled up to a high level, it indicates that the power supply chip is successfully powered on, and the power supply chip can be normally started and powered on. The programmable logic device may assign different enable pins to different power chips for outputting enable signals.
Then, step S2 is executed to receive a feedback signal of any power chip with power-on priority based on the enable signal, which may be a feedback signal of all power chips with any power-on priority. The feedback signal is triggered by each power supply chip after receiving the enabling signal and is output through the output end of the power supply chip. The programmable logic device may also assign different receive pins for different power chips to receive the feedback signal.
Finally, step S3 is executed, where the programmable logic device determines whether the received feedback signals are normal, specifically, the programmable logic device determines whether all the received feedback signals are normal, that is, determines whether all the received feedback signals are feedback signals when the corresponding power chips are normally powered on. If the received feedback signal is normal, all the power chips of the power-on priority are normally powered on, and at the moment, the enable signals are output to all the power chips of the next power-on priority of the power-on priority. For example, if any power chip with the power-on priority is the first-level power chip, the next power chip with the power-on priority is the second-level power chip, and the power-on priority of the second-level power chip is lower than that of the first-level power chip.
The power-on control method provided in the embodiment of the application is suitable for power-on control of a power supply device comprising at least two power supply chips, and firstly, an enabling signal is output to any power supply chip with a power-on priority in the power supply device to be powered on, wherein any power-on priority does not comprise the lowest power-on priority; then receiving a feedback signal of the power chip with any power-on priority based on the enabling signal; and finally, outputting an enabling signal to a power chip of the next power-on priority of any power-on priority if the received feedback signal is determined to be normal. Therefore, the power supply chips of each power-on priority in the power supply device can be sequentially controlled and judged to accurately control the starting time sequence of the power supply chips of each power-on priority, the starting of the power supply chips under various complex environments can meet the time sequence requirement, and the system where the power supply device is located can be normally started and operated.
As shown in fig. 2, on the basis of the foregoing embodiment, the power-on control method provided in this embodiment further includes:
s4, outputting enabling signals to the power supply chip in the power supply device step by step according to the sequence from the highest power-on priority to the lowest power-on priority;
s5, receiving feedback signals of the power chips with the power-on priorities based on the enabling signals;
and S6, if the feedback signals corresponding to all the power chips in the power supply device are determined to be normal, outputting a reset signal to a system where the power supply device is located, and powering on the system.
Specifically, in this embodiment of the application, the editable logic device may perform step S4, that is, output the enable signal to the power chip in the power supply device step by step from the highest power-on priority until finally outputting the enable signal to the power chip with the lowest power-on priority in the power supply device; the editable logic device may execute step S5, receiving a feedback signal of each power chip with the power-on priority based on the enable signal; and finally, executing a step S6, determining whether the feedback signals corresponding to all the power chips in the power device are normal, if so, indicating that all the power chips are successfully powered on and meet the timing requirement, and if the power device is successfully powered on, outputting a reset signal to the system where the power device is located by the programmable logic device, and performing power-on control on the system through the reset signal to start the system.
It should be noted that, in this application, the outputting of the enable signal to the power chip with a certain power-on priority in step S4 and the receiving of the feedback signal of the power chip with the power-on priority in step S5 are necessarily performed in sequence, but the outputting of the enable signal to the power chip with a certain power-on priority in step S4 and the receiving of the feedback signal of the power chip with another power-on priority in step S5 are independent from each other, and there is no definite sequence between them, that is, each power chip sends a feedback signal to the editable logic device after receiving the enable signal, and the programmable logic device detects that the feedback signal is received, and does not need to receive the feedback signal after outputting the enable signal to all the power chips with power-on priorities in step S4.
According to the power-on control method provided in the embodiment of the application, when the feedback signals corresponding to all the power chips in the power supply device are normal, the reset signal is output to the system where the power supply device is located, and the system is powered on, so that the system where the power supply device is located can be started and operated normally.
As shown in fig. 3, on the basis of the foregoing embodiment, the power-on control method provided in this embodiment of the present application, after receiving a feedback signal of the power chip of any power-on priority based on the enable signal, further includes:
and S7, if the received feedback signal is abnormal, giving an alarm.
Specifically, if the received feedback signals are abnormal, that is, at least one feedback signal is abnormal in all the received feedback signals, an alarm prompt is performed. The form of the alarm prompt includes but is not limited to setting a buzzer, an indicator light and the like.
In the embodiment of the application, when the feedback signal is abnormal, the alarm prompt is carried out, so that the staff can be ensured to find and solve the problem in time.
As shown in fig. 4, on the basis of the above embodiments, the power-on control method provided in this embodiment of the present application, before outputting an enable signal to a power chip with a power-on priority in a power device to be powered on, further includes:
and S0, judging whether the received feedback signal is normal or not based on the preset standard feedback signal of the power chip with any power-on priority.
Specifically, the editable logic device locally stores a standard feedback signal of each power supply chip, and the standard feedback signal includes a power-on feedback signal and a non-power-on feedback signal when the corresponding power supply chip is normally powered on. After receiving all the feedback signals, the editable logic device compares each received feedback signal with the corresponding standard feedback signal, and further determines whether the corresponding feedback signal is normal.
On the basis of the foregoing embodiment, in the power-on control method provided in this embodiment of the present application, the determining, based on a preset standard feedback signal of the power chip of any power-on priority, whether the received feedback signal is normal specifically includes:
if the received feedback signal is consistent with the power-on feedback signal in the standard feedback signal, judging that the received feedback signal is normal;
otherwise, judging that the received feedback signal is abnormal.
Specifically, the editable logic device determines whether each received feedback signal is consistent with the corresponding power-on feedback signal, and if so, it indicates that the corresponding feedback signal is normal and the corresponding power chip is powered on normally. Otherwise, if each received feedback signal is consistent with the corresponding non-powered feedback signal, the received feedback signal is abnormal.
As shown in fig. 5, on the basis of the above embodiments, an embodiment of the present application provides a power-on control unit, which is adapted to control power-on of a power supply device including at least two power supply chips, and includes: an output module 21 and a receiving module 22. Wherein the content of the first and second substances,
the output module 21 is configured to output an enable signal to a power chip of any power-on priority in a power supply device to be powered on, where the power-on priority does not include a lowest power-on priority;
the receiving module 22 is configured to receive a feedback signal of the power chip of any power-on priority based on the enable signal;
the output module 21 is further configured to determine that the received feedback signal is normal, and output an enable signal to a power chip of a power-on priority next to any power-on priority.
As shown in fig. 6, based on the above embodiment, in the power-on control unit provided in this embodiment of the present application, the output module 21 is further configured to output an enable signal to the power chip in the power supply device step by step according to an order from a highest power-on priority to a lowest power-on priority;
the receiving module 22 is further configured to receive a feedback signal of each power chip with a power-on priority based on the enable signal;
correspondingly, the power-on control unit further comprises a power-on module 23 configured to:
and if the feedback signals corresponding to all the power chips in the power supply device are determined to be normal, outputting a reset signal to a system where the power supply device is located, and electrifying the system.
As shown in fig. 7, on the basis of the above embodiment, the power-on control unit provided in the embodiment of the present application further includes an alarm prompting module 24, configured to:
and if the received feedback signal is abnormal, alarming and prompting.
As shown in fig. 8, on the basis of the foregoing embodiment, the power-on control unit provided in this embodiment further includes a determining module 25, configured to:
and judging whether the received feedback signal is normal or not based on a preset standard feedback signal of the power supply chip with any power-on priority.
On the basis of the foregoing embodiment, in the power-on control unit provided in this embodiment of the present application, the determining module is specifically configured to:
if the received feedback signal is consistent with the power-on feedback signal in the standard feedback signal, judging that the received feedback signal is normal;
otherwise, judging that the received feedback signal is abnormal.
Specifically, the power-on control unit provided in the embodiment of the present application is configured to execute the power-on control method, and a specific implementation manner of the power-on control unit is consistent with that of the power-on control method provided in the embodiment of the present application, and the same beneficial effects can be achieved, and details are not repeated here.
As shown in fig. 9, on the basis of the above embodiments, an embodiment of the present application provides a programmable logic device, including: a power-on control unit 90, a plurality of enable pins 91, and a receive pin 92 corresponding to each enable pin;
each of the enable pins 91 corresponds to one power chip in the power supply apparatus to be powered on.
Specifically, as shown in fig. 10, the model of the programmable logic device may be EPM570T100I 5. The editable logic device comprises 51 pins, the pin 28 may be configured to output an enable signal to the power chip with the first power-on priority, which is labeled CORE _ EN, and the pin 29 may be configured to receive a feedback signal of the power chip with the first power-on priority, which is labeled CORE _ GOOD. Pin 1, pin 5, pin 17, and pin 41 may be respectively configured to output an enable signal to the first, second, third, and fourth power-on priority power chips, which are respectively labeled as PS _ DDR _ EN, VCCPLL _ EN, VCCAUX _ EN, and PL _ DDR _ EN. Pin 2, pin 6, pin 18, and pin 42 may be used to receive feedback signals of the first, second, third, and fourth power-on priority power chips, which are respectively labeled as PS _ DDR _ GD, VCCPLL _ PG, VCCAUX _ GD, and PL _ DDR _ GD. Pin 33, pin 34, and pin 36 may be used to output enable signals, labeled MGTVCCAUX _ EN, MGTAVTT _ EN, and MGTAVCC _ EN, respectively, to the fifth second power-up priority power chip. Pin 35 may be used to receive a feedback signal, labeled MGT _ GOOD, from a fifth second power-on priority power chip. Pins 20 and 21 may be used to output enable signals, labeled VCC33_ EN and VCC18_ EN, respectively, to the first and second power chips with the third power-on priority. Pins 26 and 27 may be used to receive feedback signals from the first and second third power-on priority power chips, respectively, and are labeled VCC33_ GD and VCC18_ GD, respectively. Pin 51 may be used to output a reset signal, labeled RST, to the system in which the power supply device is located.
Fig. 11 is a power-on control system provided in an embodiment of the present application, including: the power module 111 and the programmable logic device 112 provided in the above embodiment, the programmable logic device 112 is respectively connected to each power chip with power-on priority in the power device 113 to be powered on and the power module 111; the power module 111 is used for supplying power to the programmable logic device 112 and the power chip. The editable logic device 112 is used to perform power-on control on each power chip with power-on priority in the power supply apparatus 113 one by one.
Fig. 12 illustrates a physical structure diagram of an electronic device, which may include, as shown in fig. 12: a processor (processor)121, a communication Interface (communication Interface)122, a memory (memory)123 and a communication bus 124, wherein the processor 121, the communication Interface 122 and the memory 123 complete communication with each other through the communication bus 124. Processor 121 may invoke logic instructions in memory 123 to perform a power-on control method suitable for power-on control of a power device comprising at least two power chips, comprising: outputting an enabling signal to a power chip with any power-on priority in a power device to be powered on, wherein any power-on priority does not include the lowest power-on priority; receiving a feedback signal of the power chip with any power-on priority based on the enabling signal; and if the received feedback signal is determined to be normal, outputting an enabling signal to a power chip of the next power-on priority of any power-on priority.
In addition, the logic instructions in the memory 123 may be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The processor 121 in the electronic device provided in the embodiment of the present application may call a logic instruction in the memory 123 to implement the power-on control method, and a specific implementation manner of the power-on control method is consistent with that of the power-on control method provided in the embodiment of the present application, and the same beneficial effects may be achieved, and details are not described here.
In another aspect, the present application also provides a computer program product, including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, which when executed by a computer, enable the computer to perform the power-on control method provided by the above methods, the method including: the power-on control of a power supply device comprising at least two power supply chips is applicable, and comprises the following steps: outputting an enabling signal to a power chip with any power-on priority in a power device to be powered on, wherein any power-on priority does not include the lowest power-on priority; receiving a feedback signal of the power chip with any power-on priority based on the enabling signal; and if the received feedback signal is determined to be normal, outputting an enabling signal to a power chip of the next power-on priority of any power-on priority.
When the computer program product provided in the embodiment of the present application is executed, the power-on control method is implemented, and the implementation manners of the power-on control method provided in the embodiment of the present application are consistent, and the same beneficial effects can be achieved, which is not described herein again.
In yet another aspect, the present application further provides a non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor is implemented to perform the power-on control method provided above, the method including: the power-on control of a power supply device comprising at least two power supply chips is applicable, and comprises the following steps: outputting an enabling signal to a power chip with any power-on priority in a power device to be powered on, wherein any power-on priority does not include the lowest power-on priority; receiving a feedback signal of the power chip with any power-on priority based on the enabling signal; and if the received feedback signal is determined to be normal, outputting an enabling signal to a power chip of the next power-on priority of any power-on priority.
When a computer program stored on a non-transitory computer readable storage medium provided in the embodiments of the present application is executed, the power-on control method is implemented, and embodiments of the power-on control method provided in the embodiments of the present application are consistent and can achieve the same beneficial effects, which are not described herein again.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (14)
1. A power-on control method is suitable for power-on control of a power supply device comprising at least two power supply chips, and comprises the following steps:
outputting an enabling signal to a power chip with any power-on priority in a power device to be powered on, wherein any power-on priority does not include the lowest power-on priority;
receiving a feedback signal of the power chip with any power-on priority based on the enabling signal;
and if the received feedback signal is determined to be normal, outputting an enabling signal to a power chip of the next power-on priority of any power-on priority.
2. The power-on control method according to claim 1, further comprising:
outputting an enabling signal to a power supply chip in the power supply device step by step according to the sequence from the highest power-on priority to the lowest power-on priority;
receiving feedback signals of the power chips of the power-on priorities based on the enabling signals;
and if the feedback signals corresponding to all the power chips in the power supply device are determined to be normal, outputting a reset signal to a system where the power supply device is located, and electrifying the system.
3. The power-on control method according to claim 1, wherein after receiving the feedback signal of the power chip of any power-on priority based on the enable signal, the method further comprises: and if the received feedback signal is abnormal, alarming and prompting.
4. The power-on control method according to any one of claims 1 to 3, wherein the outputting the enable signal to the power chip of any power-on priority in the power device to be powered on further comprises: and judging whether the received feedback signal is normal or not based on a preset standard feedback signal of the power supply chip with any power-on priority.
5. The power-on control method according to claim 4, wherein the determining whether the received feedback signal is normal based on a preset standard feedback signal of the power chip with any power-on priority includes:
if the received feedback signal is consistent with the power-on feedback signal in the standard feedback signal, judging that the received feedback signal is normal;
otherwise, judging that the received feedback signal is abnormal.
6. A power-on control unit adapted to control power-on of a power supply device including at least two power supply chips, comprising:
the output module is used for outputting an enabling signal to any power chip with a power-on priority in the power supply device to be powered on, wherein any power-on priority does not include the lowest power-on priority;
the receiving module is used for receiving a feedback signal of the power chip with any power-on priority based on the enabling signal;
and the output module is further configured to output an enable signal to a power chip of a next power-on priority of any power-on priority if it is determined that the received feedback signal is normal.
7. The power-on control unit of claim 6, wherein the output module is further configured to: outputting an enabling signal to a power supply chip in the power supply device step by step according to the sequence from the highest power-on priority to the lowest power-on priority;
the receiving module is further configured to: receiving feedback signals of the power chips of the power-on priorities based on the enabling signals;
correspondingly, the power-on control unit further comprises a power-on module, configured to:
and if the feedback signals corresponding to all the power chips in the power supply device are determined to be normal, outputting a reset signal to a system where the power supply device is located, and electrifying the system.
8. The power-on control unit of claim 6, further comprising an alarm prompt module configured to:
and if the received feedback signal is abnormal, alarming and prompting.
9. The power-on control unit according to any one of claims 6 to 8, further comprising a determining module configured to:
and judging whether the received feedback signal is normal or not based on a preset standard feedback signal of the power supply chip with any power-on priority.
10. The power-on control unit according to claim 9, wherein the determining module is specifically configured to:
if the received feedback signal is consistent with the power-on feedback signal in the standard feedback signal, judging that the received feedback signal is normal;
otherwise, judging that the received feedback signal is abnormal.
11. A programmable logic device, comprising: the power-on control unit of any one of claims 6-10, a plurality of enable pins, and a receive pin corresponding to each enable pin, the power-on control unit being connected to the enable pins and the receive pins, respectively;
each enable pin corresponds to one power chip in the power device to be powered on.
12. A power-on control system, comprising: the power module and the programmable logic device as claimed in claim 11, wherein the programmable logic device is respectively connected with the power chip of each power-on priority in the power device to be powered on and the power module; the power supply module is used for supplying power to the programmable logic device and the power supply chip.
13. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the steps of the power-on control method according to any one of claims 1 to 5 are implemented when the program is executed by the processor.
14. A non-transitory computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the power-on control method according to any one of claims 1 to 5.
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