CN112487738B - Signal control method, system, terminal and storage medium in board design stage - Google Patents
Signal control method, system, terminal and storage medium in board design stage Download PDFInfo
- Publication number
- CN112487738B CN112487738B CN202011301757.6A CN202011301757A CN112487738B CN 112487738 B CN112487738 B CN 112487738B CN 202011301757 A CN202011301757 A CN 202011301757A CN 112487738 B CN112487738 B CN 112487738B
- Authority
- CN
- China
- Prior art keywords
- input signal
- version
- signal
- flag
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000013461 design Methods 0.000 title claims abstract description 21
- 238000013486 operation strategy Methods 0.000 claims abstract description 28
- 238000012216 screening Methods 0.000 claims abstract description 5
- 238000004590 computer program Methods 0.000 claims description 3
- RVCKCEDKBVEEHL-UHFFFAOYSA-N 2,3,4,5,6-pentachlorobenzyl alcohol Chemical compound OCC1=C(Cl)C(Cl)=C(Cl)C(Cl)=C1Cl RVCKCEDKBVEEHL-UHFFFAOYSA-N 0.000 abstract description 22
- 238000010586 diagram Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009131 signaling function Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Abstract
The invention provides a method, a system, a terminal and a storage medium for controlling signals in a card design stage, wherein the method comprises the following steps: setting flag values and operation strategies corresponding to various signals under different versions according to signal information adopted by various versions of the board card; collecting the current version of the board card; screening a flag value and an operation strategy corresponding to the input signal according to the current version and the type of the received input signal, and calculating the input signal according to the corresponding flag value and the operation strategy: and outputting the operation result of the input signal, and if the operation result is still the input signal, indicating that the input signal is enabled. The invention ensures that the PCBA version of the chip circuit of the board card is developed at different stages without repeatedly modifying the signal wire of the circuit all the time, and the use of the signal can be started or closed only by connecting the signal which is possibly used in the future to the CPLD in advance, thereby being very convenient for the PCBA circuit design of the board card.
Description
Technical Field
The invention relates to the technical field of printed circuit board design, in particular to a method, a system, a terminal and a storage medium for controlling signals in a board design stage.
Background
Generally, when a PCBA circuit board is developed, there are several opportunities for board version modification, and circuit designs of the PCBA board at different stages may be different. Chip signals on some boards may be still used in a previous version of the PCBA board, and a next version of the PCBA board may not be used, and if the design is not made through the CPLD on the board at this time, circuits on the chip signals may need to be reconnected and modified frequently. This places a significant burden on developing PCBA board circuits. Therefore, the invention provides a method for controlling the signal functions of different board versions by using the CPLD to assist the design on the circuit board.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a method, a system, a terminal and a storage medium for controlling signals in a design stage of a card, so as to solve the above-mentioned technical problems.
In a first aspect, the present invention provides a method for controlling signals in a board design phase, including:
setting flag values and operation strategies corresponding to various signals under different versions according to signal information adopted by various versions of the board card;
collecting the current version of the board card;
screening a flag value and an operation strategy corresponding to the input signal according to the current version and the type of the received input signal, and calculating the input signal according to the corresponding flag value and the operation strategy;
and outputting the operation result of the input signal, and if the operation result is still the input signal, indicating that the input signal is enabled.
Further, the current version of the acquisition board card includes:
presetting complex programmable logic device pins corresponding to each version;
and acquiring the version number of the corresponding current version according to the pin potential state combination.
Further, the current version of the acquisition board card includes:
preselecting and writing identification signals of various versions into a register of the complex programmable logic device through an integrated circuit bus;
and the complex programmable logic device acquires a corresponding version as a current version according to the identification signal sent by the BMC.
Further, the setting of flag values and operation strategies corresponding to various signals under different versions according to signal information adopted by various versions of the board card includes:
for the input signal with effective low voltage, adopting an operation strategy of OR operation of the input signal, the corresponding output signal and a preset flag; setting the flag of the low-voltage effective signal which is not needed by each version to be 1, and setting the flag of the low-voltage effective signal which is needed by each version to be 0;
for the high-voltage effective input signal, adopting an operation strategy of AND operation of the input signal, the corresponding output signal and a preset flag; the flag of the high-voltage valid input signal required for each version is set to 1, and the flag of the high-voltage valid input signal not required for each version is set to 0.
In a second aspect, the present invention provides a signal control system in a board design stage, including:
the file configuration unit is used for setting flag values and operation strategies corresponding to various signals under different versions according to signal information adopted by various versions of the board card;
the version acquisition unit is configured for acquiring the current version of the board card;
a signal judgment unit configured to screen a flag value and an operation policy corresponding to the input signal according to the current version and the type of the received input signal, and calculate the input signal according to the corresponding flag value and operation policy;
and the result output unit is configured to output the operation result of the input signal, and if the operation result is still the input signal, the result output unit indicates that the input signal is enabled.
Further, the version collecting unit includes:
the pin setting module is configured for presetting the complex programmable logic device pins corresponding to each version;
and the pin acquisition module is configured to acquire the version number of the corresponding current version according to the pin potential state combination.
Further, the version collecting unit includes:
the identification setting module is configured for preselecting the identification signals of all versions to be written into a register of the complex programmable logic device through an integrated circuit bus;
and the signal identification module is configured for the complex programmable logic device to acquire a corresponding version as a current version according to the identification signal sent by the BMC.
Further, the file configuration unit includes:
the low-voltage setting module is configured for adopting an operation strategy of performing OR operation on the input signal, the corresponding output signal and a preset flag for the input signal with effective low voltage; setting the flag of the low-voltage effective signal which is not needed by each version to be 1, and setting the flag of the low-voltage effective signal which is needed by each version to be 0;
the high-voltage setting module is configured for carrying out AND operation on the input signal, the corresponding output signal and a preset flag for the high-voltage effective input signal; the flag of the high-voltage valid input signal required for each version is set to 1, and the flag of the high-voltage valid input signal not required for each version is set to 0.
In a third aspect, a terminal is provided, which includes:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer storage medium is provided, having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The beneficial effect of the invention is that,
the method, the system, the terminal and the storage medium for controlling the signals in the board design stage, provided by the invention, have the advantages that the signal information adopted by various versions is preset, and then the current board version is acquired, so that whether the input signals are available or not is automatically judged. The invention ensures that the PCBA version of the chip circuit of the board card is developed at different stages without repeatedly modifying the signal wire of the circuit all the time, and the use of the signal can be started or closed only by connecting the signal which is possibly used in the future to the CPLD in advance, thereby being very convenient for the PCBA circuit design of the board card.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
Fig. 2 is a schematic diagram of a method of one embodiment of the present invention.
FIG. 3 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following explains key terms appearing in the present invention.
BMC-Basebaard Management Controller mainboard Management Controller
Complex Programmable Logic Device of CPLD-Complex Programmable Logic Device
I2C-Inter-Integrated Circuit bus
PCBA-Printed Circuit Board Assembly Printed Circuit Board
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution body in fig. 1 may be a signal control system in a design stage of a board card.
As shown in fig. 1, the method includes:
Specifically, as shown in fig. 2, the method for controlling the signal at the board design stage includes:
s1, setting flag values and operation strategies corresponding to various signals under different versions according to signal information adopted by various versions of the board card.
When a PCBA circuit is typically designed, chips on different board versions will have different signals that may be used or removed at different stages of the board design. Therefore, in the embodiment, the signals with uncertain functions are connected to the CPLD first, and then the CPLD is used to determine the board stages of different PCBA boards, so that the signals are determined to be unnecessary to use.
For the input signal with effective low voltage, adopting an operation strategy of OR operation of the input signal, the corresponding output signal and a preset flag; setting the flag of the low-voltage effective signal which is not needed by each version to be 1, and setting the flag of the low-voltage effective signal which is needed by each version to be 0; for the high-voltage effective input signal, adopting an operation strategy of AND operation of the input signal, the corresponding output signal and a preset flag; the flag of the high-voltage valid input signal required for each version is set to 1, and the flag of the high-voltage valid input signal not required for each version is set to 0.
And S2, acquiring the current version of the board card.
There are two methods for version identification, specifically as follows:
in the development stage of the PCBA board, a plurality of CPLD chip pins on the board represent the version number of the PCBA. The voltage dividing resistor on the circuit is directly used to pull up or pull down the PLANAR _ ID signal to distinguish the version number, if PLANAR _ ID2 is pulled down, PLANAR _ ID1 is pulled down, PLANAR _ ID0 is pulled up, then the CPLD reads the binary digits in the sequence of 0,0 and 1, which represents that the PCBA is the PCBA version of the first version.
And writing registers representing different PCBA version numbers into the CPLD through the I2C BUS at the BMC end. The method for writing the I2C register by using the BMC is that when the board is designed, the PLANAR _ ID signal is written into the CPLD in a mode of I2C BUS, the BMC tells the CPLD to the PLANAR _ ID signal, if the BMC sends the PLANAR _ ID2, the PLANAR _ ID1 and the PLANAR _ ID0 to the CPLD through the I2C BUS, and if the CPLD sends the PLANAR _ ID2, the PLANAR _ ID1 and the PLANAR _ ID0 to the CPLD, the CPLD knows that the PCBA is the PCBA version of the first version from the register of the I2C.
S3, screening a flag value and an operation strategy corresponding to the input signal according to the current version and the type of the received input signal, and calculating the input signal according to the corresponding flag value and the operation strategy; and outputting the operation result of the input signal, and if the operation result is still the input signal, indicating that the input signal is enabled.
When the input signal a or the output signal B connected to the CPLD is not needed in this version of the PCBA, and the signals a, B are low voltage valid, the flag P corresponding to the signals a, B is 1, and the signals a, B and the corresponding flag P are or operated inside the CPLD, as shown in table one, the a, B signals that are low voltage valid, whether 1 or 0, and the result of the or operation of the last a, B and P is 1. When the operation result of the input signal a is all 1, it indicates that the input signal a and the corresponding output signal B are turned off.
If the flag P corresponding to the input signal A is 0, the OR operation of A, B and P is the same as A, B, i.e. the operation result is still the input signal, indicating that the input signal A and the corresponding output signal B are enabled.
The method can achieve the effect of low voltage signal A, B using flag P to control the timing of its use.
Watch 1
For the input signals a, B that are active at high voltage, if the signals a, B are not needed in the PCBA version, the flag P corresponding to the signals a, B is 0, and the signals a, B and the flag P are and, as shown in table two, the result of and operation for the signals a, B and the flag P is zero, i.e., the input signal a and the output signal B are turned off.
If the signals A, B are required in this version of PCBA, and their corresponding flags P are 1, the AND operation of A, B and flags P is the same as A, B, i.e., the input signal A and output signal B are enabled.
The method can achieve high voltage effective signals A, B, and use the flag P to control the using time.
Watch two
As shown in fig. 3, the system 300 includes:
the file configuration unit 310 is configured to set flag values and operation strategies corresponding to various signals under different versions according to signal information adopted by various versions of the board card;
the version acquisition unit 320 is configured to acquire the current version of the board card;
a signal determining unit 330, configured to filter a flag value and an operation policy corresponding to the input signal according to the current version and the type of the received input signal, and calculate the input signal according to the corresponding flag value and operation policy:
a result output unit 340 configured to output an operation result of the input signal, and indicate that the input signal is enabled if the operation result is still the input signal.
Optionally, as an embodiment of the present invention, the version acquiring unit includes:
the pin setting module is configured for presetting the complex programmable logic device pins corresponding to each version;
and the pin acquisition module is configured to acquire the version number of the corresponding current version according to the pin potential state combination.
Optionally, as an embodiment of the present invention, the version acquiring unit includes:
the identification setting module is configured for preselecting the identification signals of all versions to be written into a register of the complex programmable logic device through an integrated circuit bus;
and the signal identification module is configured for the complex programmable logic device to acquire a corresponding version as a current version according to the identification signal sent by the BMC.
Optionally, as an embodiment of the present invention, the file configuration unit includes:
the low-voltage setting module is configured for adopting an operation strategy of performing OR operation on the input signal, the corresponding output signal and a preset flag for the input signal with effective low voltage; setting the flag of the low-voltage effective signal which is not needed by each version to be 1, and setting the flag of the low-voltage effective signal which is needed by each version to be 0;
the high-voltage setting module is configured for carrying out AND operation on the input signal, the corresponding output signal and a preset flag for the high-voltage effective input signal; the flag of the high-voltage valid input signal required for each version is set to 1, and the flag of the high-voltage valid input signal not required for each version is set to 0.
Fig. 4 is a schematic structural diagram of a terminal 400 according to an embodiment of the present invention, where the terminal 400 may be used to execute a board design stage signal control method according to the embodiment of the present invention.
Among them, the terminal 400 may include: a processor 410, a memory 420, and a communication unit 430. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 420 may be used for storing instructions executed by the processor 410, and the memory 420 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 420, when executed by processor 410, enable terminal 400 to perform some or all of the steps in the method embodiments described below.
The processor 410 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 420 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 410 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 430, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the invention presets the signal information adopted by various versions, and then collects the current board card version, thereby realizing the automatic judgment of whether the input signal is available. The invention ensures that the PCBA version of the chip circuit of the board card is developed at different stages without repeatedly modifying the signal wire of the circuit all the time, and the use of the signal can be turned on or off only by connecting the signal which is possibly used in the future to the CPLD in advance.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be substantially or partially embodied in the form of a software product, the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and various media capable of storing program codes include several instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail in connection with the preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A method for controlling signals in a design stage of a card is characterized by comprising the following steps:
setting flag values and operation strategies corresponding to various signals under different versions according to signal information adopted by various versions of the board card;
collecting the current version of the board card;
screening a flag value and an operation strategy corresponding to the input signal according to the current version and the type of the received input signal, and calculating the input signal according to the corresponding flag value and the operation strategy:
outputting the operation result of the input signal, and if the operation result is still the input signal, indicating that the input signal is enabled;
the method further comprises the following steps:
for the input signal with effective low voltage, adopting an operation strategy of OR operation of the input signal, the corresponding output signal and a preset flag; setting the flag of the low-voltage effective signal which is not needed by each version to be 1, and setting the flag of the low-voltage effective signal which is needed by each version to be 0;
for the high-voltage effective input signals, an operation strategy of AND operation of the input signals, the corresponding output signals and a preset flag is adopted; the flag of the high-voltage valid input signal required for each version is set to 1, and the flag of the high-voltage valid input signal not required for each version is set to 0.
2. The method of claim 1, wherein acquiring the current version of the board card comprises:
presetting complex programmable logic device pins corresponding to each version;
and acquiring the version number of the corresponding current version according to the pin potential state combination.
3. The method of claim 1, wherein acquiring the current version of the board card comprises:
preselecting and writing the identification signals of each version into a register of the complex programmable logic device through an integrated circuit bus;
and the complex programmable logic device acquires a corresponding version as a current version according to the identification signal sent by the BMC.
4. A card design phase signal control system is characterized by comprising:
the file configuration unit is used for setting flag values and operation strategies corresponding to various signals under different versions according to signal information adopted by various versions of the board card;
the version acquisition unit is configured for acquiring the current version of the board card;
a signal determining unit configured to screen a flag value and an operation policy corresponding to the input signal according to the current version and the type of the received input signal, and calculate the input signal according to the corresponding flag value and operation policy:
the result output unit is configured to output the operation result of the input signal, and if the operation result is still the input signal, the result output unit indicates that the input signal is enabled;
the file configuration unit includes:
the low-voltage setting module is configured for adopting an operation strategy of performing OR operation on the input signal, the corresponding output signal and a preset flag for the input signal with effective low voltage; setting the flag of the low-voltage effective signal which is not needed by each version to be 1, and setting the flag of the low-voltage effective signal which is needed by each version to be 0;
the high-voltage setting module is configured for carrying out AND operation on the input signal, the corresponding output signal and a preset flag for the high-voltage effective input signal; the flag of the high-voltage valid input signal required for each version is set to 1, and the flag of the high-voltage valid input signal not required for each version is set to 0.
5. The system of claim 4, wherein the version acquisition unit comprises:
the pin setting module is configured for presetting the complex programmable logic device pins corresponding to each version;
and the pin acquisition module is configured to acquire the version number of the corresponding current version according to the pin potential state combination.
6. The system of claim 4, wherein the version acquisition unit comprises:
the identification setting module is configured for preselecting the identification signals of all versions to be written into a register of the complex programmable logic device through an integrated circuit bus;
and the signal identification module is configured for acquiring a corresponding version as the current version according to the identification signal sent by the BMC by the complex programmable logic device.
7. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any one of claims 1-3.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011301757.6A CN112487738B (en) | 2020-11-19 | 2020-11-19 | Signal control method, system, terminal and storage medium in board design stage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011301757.6A CN112487738B (en) | 2020-11-19 | 2020-11-19 | Signal control method, system, terminal and storage medium in board design stage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112487738A CN112487738A (en) | 2021-03-12 |
| CN112487738B true CN112487738B (en) | 2022-10-18 |
Family
ID=74931946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011301757.6A Active CN112487738B (en) | 2020-11-19 | 2020-11-19 | Signal control method, system, terminal and storage medium in board design stage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112487738B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102486766A (en) * | 2010-12-01 | 2012-06-06 | 北京旋极信息技术股份有限公司 | Board configuration method and board configuration device |
| CN104123381A (en) * | 2014-08-01 | 2014-10-29 | 武汉邮电科学研究院 | Automatic matching method of hardware board card |
| CN110515865A (en) * | 2019-08-30 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of board type judgment method, device, equipment and storage medium |
-
2020
- 2020-11-19 CN CN202011301757.6A patent/CN112487738B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102486766A (en) * | 2010-12-01 | 2012-06-06 | 北京旋极信息技术股份有限公司 | Board configuration method and board configuration device |
| CN104123381A (en) * | 2014-08-01 | 2014-10-29 | 武汉邮电科学研究院 | Automatic matching method of hardware board card |
| CN110515865A (en) * | 2019-08-30 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of board type judgment method, device, equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112487738A (en) | 2021-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110162435B (en) | Method, system, terminal and storage medium for starting and testing PXE of server | |
| DE102007009300B4 (en) | Computer system and method for operating a computer system | |
| CN109445690B (en) | RAID card performance optimization method, device, terminal and storage medium | |
| US6751740B1 (en) | Method and system for using a combined power detect and presence detect signal to determine if a memory module is connected and receiving power | |
| CN111262753A (en) | Method, system, terminal and storage medium for automatically configuring number of NUMA nodes | |
| CN112487738B (en) | Signal control method, system, terminal and storage medium in board design stage | |
| CN109117406B (en) | PCIE hot plug test method, device, terminal and storage medium | |
| CN110798370A (en) | Bus protocol debugging method and device based on universal interface and terminal equipment | |
| CN108491299A (en) | A kind of signal detection board and the mainboard for signal detection | |
| CN112003730A (en) | Method, system, terminal and storage medium for rapid cluster deployment | |
| CN112835564A (en) | Code generation method and device | |
| CN115878327A (en) | Bus reservation method, device, server, electronic equipment and storage medium | |
| CN108710508B (en) | Processing method and device and electronic equipment | |
| CN113760800A (en) | Serial port path selection method, system, terminal and storage medium based on BMC | |
| US6865693B1 (en) | System and method for debugging multiprocessor systems | |
| CN113064771B (en) | I2C link checking method, system, terminal and storage medium | |
| CN110865932A (en) | Program internal interface testing method, system, terminal and storage medium | |
| CN111240775A (en) | BIOS Setup interface control method, system, terminal and storage medium | |
| CN112988250B (en) | Multi-mainboard USB service configuration method, system, terminal and storage medium | |
| CN109739565A (en) | A kind of method, apparatus, computer equipment and storage medium for guaranteeing Bootrom and operating normally | |
| CN110645131B (en) | Vehicle control method, vehicle switch identification method and device | |
| CN114003516B (en) | Method, system, equipment and storage medium for setting BIOS as default value | |
| CN112486578B (en) | Method, system, terminal and storage medium for dynamically loading BMC (baseboard management controller) with sensor | |
| CN115718633A (en) | Screen printing updating method, device, terminal and medium for multi-configuration machine type chassis | |
| US6360319B1 (en) | Method and apparatus for storing and retrieving system revision information |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |