CN108491299A - A kind of signal detection board and the mainboard for signal detection - Google Patents
A kind of signal detection board and the mainboard for signal detection Download PDFInfo
- Publication number
- CN108491299A CN108491299A CN201810296795.3A CN201810296795A CN108491299A CN 108491299 A CN108491299 A CN 108491299A CN 201810296795 A CN201810296795 A CN 201810296795A CN 108491299 A CN108491299 A CN 108491299A
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- Prior art keywords
- signal
- mainboard
- information
- detected
- fpga
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
Abstract
This application provides a kind of signal detection boards, including：On-site programmable gate array FPGA, the FPGA is used to obtain the first information of mainboard by I2C buses, wherein, the first information includes the identification information of the mainboard, the identification information of signal to be detected and the corresponding pin information of the signal to be detected, the FPGA are additionally operable to detect the signal to be detected；Real-time clock RTC block, the RTC block are used to provide current time information to the FPGA；Storage card, the storage card are used to store the signal to be detected according to the first information, and acquisition time when detection is signal to be detected.Therefore, the embodiment of the present application provides a kind of board of signal detection, can detect the signal to be detected of mainboard, and can store the relevant information correspondence of mainboard where the signal to be detected, be conducive to improve the flexibility of fault detect, and advantageously reduce cost.
Description
Technical field
This application involves computer realms, and are examined more particularly, to a kind of signal detection board and for signal
The mainboard of survey.
Background technology
During the debugging of server and use, sometimes because of the problems such as failure generates shutdown, delay machine.In order to investigate
These problems, commissioning staff it should be understood that when failure occurs each signal state.
The prior art has a kind of integrated signal monitoring unit, monitoring system key signal on the server, and is stored
To the design method of the storage devices such as SD card.However, the signal monitoring unit generally all integrates in the motherboard.In this way, whenever setting
When counting other server products, it is required for redesigning signal monitoring unit.If the design of signal monitoring unit goes wrong,
When changing the unit, need to do printed circuit board (English on entire mainboard：Printed Circuit Board, letter
It writes：PCB it) changes, cost is larger.
Invention content
The application provides a kind of signal detection board and the mainboard for signal detection, can be flexibly to the letter on mainboard
It number is detected.
On the one hand, a kind of signal detection board is provided, including：On-site programmable gate array FPGA, the FPGA are used for
The first information of mainboard is obtained by I2C buses, wherein the first information includes the identification information of the mainboard, to be detected
The identification information of signal and the corresponding pin information of the signal to be detected, the FPGA are additionally operable to detect the letter to be detected
Number；Real-time clock RTC block, the RTC block are used to provide current time information to the FPGA；Storage card, the storage
Card according to the first information for storing the signal to be detected, and acquisition time when detection is signal to be detected.
With reference to first aspect, in the first possible realization method of first aspect, the signal to be detected passes through institute
The skip signal of mainboard acquisition is stated, the signal saltus step includes that high level signal becomes low level signal, low level signal becomes
High level signal.
Second aspect provides a kind of mainboard for signal detection, including：Electrically Erasable Programmable Read-Only Memory
EEPROM, the EEPROM are for storing the first information, wherein the first information includes the identification information of the mainboard, is waited for
Detect the identification information and the corresponding pin information of the signal to be detected of signal；Baseboard controller BMC, arbitration chip, wherein
Institute's baseboard controller reads the first information in the EEPROM, the EEPROM, the BMC and institute by the arbitration chip
It states and is connected by I2C buses between arbitrating core, the BMC is additionally operable to monitor board, the arbitration by I2C bus connection signals
Chip is used to connect the signal monitoring board by I2C buses.
In conjunction with second aspect, in the first possible realization method of second aspect, the mainboard is additionally operable to be described
Signal monitoring board is powered.
In conjunction with second aspect, in second of possible realization method of second aspect, the arbitration chip is PCA9541
Chip or PCA9641 chips.
Therefore, the embodiment of the present application provides a kind of board of signal detection, can detect the signal to be detected of mainboard, and
The relevant information correspondence of mainboard where the signal to be detected can be stored, be conducive to the flexibility for improving fault detect,
And advantageously reduce cost.
Description of the drawings
Fig. 1 shows the schematic diagram of the signal detection board of the application one embodiment.
Fig. 2 shows the mainboard schematic diagrames for signal detection of the application one embodiment.
Fig. 3 shows the schematic block diagram of the interconnection architecture of the application one embodiment board and mainboard.
Specific implementation mode
Below in conjunction with attached drawing, the technical solution in the application is described.
It is essentially identical to the functional requirement of signal monitoring unit in different server product, the letter only monitored
Number difference.Can be considered when being designed design one in the form of independent board existing for general signal monitoring unit,
The connector for connection signal monitoring board is placed on mainboard.Motherboard design space can be saved in this way and is kept away
Exempt from repeated work, saves design cost.
In view of this, the embodiment of the present application proposes that a kind of signal detection board, Fig. 1 show the application one embodiment
The schematic diagram of signal detection board, as shown in Figure 1, the board includes：Field programmable gate array (English：Field programmable gate
Array is write a Chinese character in simplified form：FPGA), the FPGA is used for through integrated circuit (English：Integrated Circuit Inter, write a Chinese character in simplified form：
I2C) bus obtains the first information of mainboard, wherein the first information includes the identification information of the mainboard, signal to be detected
Identification information and the corresponding pin information of the signal to be detected, the FPGA be additionally operable to detect the signal to be detected；It is real
Shi Shizhong (English：Real-Time Clock, write a Chinese character in simplified form：RTC) module, when the RTC block is used to provide current to the FPGA
Between information；Storage card, the storage card is used to store the signal to be detected according to the first information, and detection is to be checked
Survey acquisition time when signal.
Specifically, wherein FPGA is the main body of board, is responsible for acquisition signal condition to be monitored, and store and arrive storage card
In.RTC block is responsible for providing the current time to FPGA, and the signal condition of the time and monitoring stores together, convenient for debugging people
Member's reference.FPGA is connected with RTC block, storage card.
Optionally, the skip signal obtained by the mainboard as the application one embodiment, the signal to be detected,
The signal saltus step includes that high level signal becomes low level signal, low level signal becomes high level signal.
Therefore, the embodiment of the present application provides a kind of board of signal detection, can detect the signal to be detected of mainboard, and
The relevant information correspondence of mainboard where the signal to be detected can be stored, be conducive to the flexibility for improving fault detect,
And advantageously reduce cost.
Fig. 2 shows the mainboard schematic diagrames for signal detection of the application one embodiment, including：Electric erazable programmable
Read-only memory EEPROM, the EEPROM are for storing the first information, wherein the first information includes the mark of the mainboard
Know information, the identification information of signal to be detected and the corresponding pin information of the signal to be detected；Baseboard controller BMC, arbitration
Chip, wherein institute's baseboard controller reads the first information in the EEPROM by the arbitration chip, the EEPROM,
It is connected by I2C buses between the BMC and the arbitration core, the BMC is additionally operable to through I2C bus connection signal monitor boards
Card, the arbitration chip are used to connect the signal monitoring board by I2C buses.
Specifically, on mainboard, signal to be monitored is connected and gives signal monitoring board.EEPROM is integrated on mainboard, is deposited
Store up the unique mark of mainboard and the title of signal to be monitored and the pin serial number list being signally attached to.These information are logical
Cross BMC write-ins.Information as CPU_PWRGD signals is corresponded to for example, reading EEPROM and can obtain pin 1.
It should be understood that can also include other information in the first information, the application does not limit, in this way, on server is each
When electric, the unique identifier of mainboard can be all read and stored.It is used on a mainboard in signal monitoring board in this way
Later, it data scrubbing need not be carried out can take to be continuing on another mainboard, and not will produce data corruption
Problem.Corresponding, signal detection board increases identification mainboard and needs the signal name monitored, and will believe according to corresponding title
The storage of number state is to the mechanism in storage card.The legibility of storage signal condition is ensured.
BMC is integrated on mainboard, and the FPGA of board is monitored by I2C bus connection signals.BMC can pass through this I2C
Bus enables FPGA change current RTC time setting.
Optionally, as the application one embodiment, the mainboard is additionally operable to power for the signal monitoring board.
That is, mainboard provides power supply for signal monitoring board.It should be understood that other are unrelated with this patent content on mainboard
Part do not draw.Mainboard is connected using conventional scheme by connector with signal monitoring board, for brevity, in figure
It is not drawn into.
Optionally, as the application one embodiment, the arbitration chip is PCA9541 chips or PCA9641 chips.
Therefore, in the prior art, server signal monitoring unit generally all integrates in the motherboard, design cost can be brought to increase
Add, the design of the problem of flexibility difference.Therefore, in the embodiment of the present application, server signal monitoring unit is fabricated to individually
Board, realizing a board can apply in multiple projects, reduce design cost, increase design flexibility.
Fig. 3 shows the schematic block diagram of the interconnection architecture of the application one embodiment board and mainboard.
Server signal monitoring unit is designed to an independent board, such as right part in figure.Wherein FPGA is plate
The main body of card is responsible for acquisition signal condition to be monitored, and is stored into SD card.RTC block be responsible for providing the current time to
The signal condition of FPGA, the time and monitoring stores together, is referred to convenient for commissioning staff.FPGA is connected with RTC block, SD card
It connects.
On mainboard, signal to be monitored is connected and gives signal monitoring board.EEPROM is integrated on mainboard, stores mainboard
Unique mark and the title of signal to be monitored and the pin serial number list being signally attached to.These information are write by BMC
Enter.Information as CPU_PWRGD signals is corresponded to for example, reading EEPROM and can obtain pin 1.
BMC is integrated on mainboard, and the FPGA of board is monitored by I2C bus connection signals.BMC can pass through this I2C
Bus enables FPGA change current RTC time setting.
In addition, FPGA and BMC arbitrates chip PCA9541 (can also be PCA9641) by I2C is connected to EEPROM, two
Person can read the information in EEPROM.
Mainboard provides power supply for signal monitoring board.When system electrification, FPGA is read by I2C buses in EEPROM first
Information, and establish new txt file stored waveform information in SD card, the newly-built text be written into the unique identification information of board
In part.The signal condition of primary each monitoring signal pin, and the corresponding letter of pin read from EEPROM are acquired simultaneously
Number title, reads current time, and store signal condition, signal name, signal acquisition time from RTC block.
Then, FPGA monitors the saltus step of all signals, and when signal saltus step, acquisition and storage signal condition, letter
Number title, signal acquisition time.
When server fail, SD card can be removed, will be analyzed in the data copy to PC of storage, failure
Investigation.
In the prior art, server signal monitoring unit generally all integrates in the motherboard, design cost can be brought to increase, spirit
The design of the problem of poor activity.Therefore, in the embodiment of the present application, server signal monitoring unit is fabricated to individual plate
Card, realizing a board can apply in multiple projects, reduce design cost, increase design flexibility.
And after signal monitoring unit is fabricated to individual board, increases identification mainboard and need the signal name monitored
Claim, and stores signal condition to the mechanism in SD card according to corresponding title.The legibility of storage signal condition is ensured.
When server powers on every time, the unique identifier of mainboard can be all read and stored.In this way in signal monitoring
Board need not carry out data scrubbing and can take to be continuing on another mainboard on a mainboard after use, and
And the problem of not will produce data corruption.
Those of ordinary skill in the art may realize that lists described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, depends on the specific application and design constraint of technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The scope of the present invention.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of division of logic function, formula that in actual implementation, there may be another division manner, such as multiple units or component
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be the indirect coupling by some interfaces, device or unit
It closes or communicates to connect, can be electrical, machinery or other forms.
The unit illustrated as separating component may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple
In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it can also
It is that each unit physically exists alone, it can also be during two or more units be integrated in one unit.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in a computer read/write memory medium.Based on this understanding, technical scheme of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be expressed in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be
People's computer, server or the second equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes：USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic disc or CD.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. a kind of signal detection board, which is characterized in that including：
On-site programmable gate array FPGA, the FPGA are used to obtain the first information of mainboard by I2C buses, wherein described
The first information includes the identification information of the mainboard, the identification information of signal to be detected and the corresponding pin of the signal to be detected
Information, the FPGA are additionally operable to detect the signal to be detected；
Real-time clock RTC block, the RTC block are used to provide current time information to the FPGA；
Storage card, the storage card is used to store the signal to be detected according to the first information, and detection is to be detected
Acquisition time when signal.
2. according to the method described in claim 1, it is characterized in that, the saltus step that the signal to be detected is obtained by the mainboard
Signal, the signal saltus step include that high level signal becomes low level signal, low level signal becomes high level signal.
3. a kind of mainboard for signal detection, which is characterized in that including：
Electrically Erasable Programmable Read-Only Memory EEPROM, the EEPROM are for storing the first information, wherein the first information
Include the identification information of the mainboard, the identification information of signal to be detected and the corresponding pin information of the signal to be detected；
Baseboard controller BMC, arbitration chip, wherein institute's baseboard controller is read by the arbitration chip in the EEPROM
The first information, connected by I2C buses between the EEPROM, the BMC and the arbitration core, the BMC is additionally operable to lead to
Cross I2C bus connection signals monitoring board, the arbitration chip is used to connect the signal monitoring board by I2C buses.
4. mainboard according to claim 3, which is characterized in that the mainboard is additionally operable to supply for the signal monitoring board
Electricity.
5. mainboard according to claim 3 or 4, which is characterized in that the arbitration chip be PCA9541 chips or
PCA9641 chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810296795.3A CN108491299A (en) | 2018-04-03 | 2018-04-03 | A kind of signal detection board and the mainboard for signal detection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810296795.3A CN108491299A (en) | 2018-04-03 | 2018-04-03 | A kind of signal detection board and the mainboard for signal detection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108491299A true CN108491299A (en) | 2018-09-04 |
Family
ID=63318167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810296795.3A Pending CN108491299A (en) | 2018-04-03 | 2018-04-03 | A kind of signal detection board and the mainboard for signal detection |
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Cited By (3)
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| CN110261761A (en) * | 2019-06-06 | 2019-09-20 | 福建星网智慧科技股份有限公司 | A kind of mainboard self-checking unit and method based on the detection of FPGA electric signal |
| CN111175636A (en) * | 2020-01-02 | 2020-05-19 | 广东科学技术职业学院 | Bonding detection circuit and bonding detection device |
| CN113760058A (en) * | 2021-07-29 | 2021-12-07 | 苏州浪潮智能科技有限公司 | System and method for adapting to mainboards with different requirements through independent board cards |
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Application publication date: 20180904 |
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