CN113760058A - System and method for adapting to mainboards with different requirements through independent board cards - Google Patents
System and method for adapting to mainboards with different requirements through independent board cards Download PDFInfo
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- CN113760058A CN113760058A CN202110866413.8A CN202110866413A CN113760058A CN 113760058 A CN113760058 A CN 113760058A CN 202110866413 A CN202110866413 A CN 202110866413A CN 113760058 A CN113760058 A CN 113760058A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/184—Mounting of motherboards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
- H01R12/712—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit
- H01R12/716—Coupling device provided on the PCB
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
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- H—ELECTRICITY
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- H01R24/00—Two-part coupling devices, or either of their cooperating parts, characterised by their overall structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R2201/00—Connectors or connections adapted for particular applications
- H01R2201/06—Connectors or connections adapted for particular applications for computer periphery
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a system and a method for adapting to mainboards with different requirements through independent board cards, wherein the system comprises the independent board cards and the mainboards; the independent board card is provided with a first interface; a second interface, a PCH and a BMC are arranged on the mainboard; the first interface is inserted with the second interface, and the second interface is connected with both the PCH and the BMC; the first interface and the second interface are respectively provided with an item number, a SKU number and a BIOS/BMC version pin group; each pin group is connected with the PCH and the BMC through a corresponding line row; each pin group is respectively connected with a corresponding upper pull-down resistor row. According to the invention, through the design of the pull-up resistor and the pull-down resistor of the independent board card, the item number, the SKU number and the version number are selected, so that the requirements of different items are met, the waste of human resources is reduced, the reusability of the mainboard is improved, and the design consistency of the server mainboard is ensured.
Description
Technical Field
The invention belongs to the technical field of mainboard design, and particularly relates to a system and a method for adapting to mainboards with different requirements through independent board cards.
Background
With the continuous updating and upgrading of the x86 architecture of the Intel, the placement positions of the key devices such as the CPU, the memory, the PCH and the like in the server are gradually solidified under the suggestion of the Intel, and all server design manufacturers basically modify the key devices partially according to the reference design of the Intel so as to adapt to the requirements of each family. However, under the condition that the size of the mechanism shell of the server is basically set, the sizes of main boards such as a main board and the like which need to be placed inside are limited within a certain range, so that the occupied space of the main board is limited, and the size of the board is required. Under the condition that the functions of the servers are gradually the same, after the server requirements provided by manufacturers are received, the occupied space of the main board is firstly evaluated, and then the design of the public board is carried out, so that the design of each family is compatible, and the manpower cost and the material cost brought by each project for independently designing the main board for each client can be reduced by using the main board as the public board.
However, the design of the bus board needs to be customized, developed and set according to the requirements of each client, different clients need to maintain a plurality of main board BOMs according to different requirements, and need to arrange manpower of different projects to maintain the main board BOMs, which causes manpower waste, and because the materials are various, mistakes are easy to occur.
Therefore, it is very necessary to provide a system and a method for adapting motherboards with different requirements by using independent boards, which are not enough in the prior art.
Disclosure of Invention
Aiming at the defects that in the prior art, the design of the mainboard as a public board needs to maintain a plurality of mainboard BOMs, the labor is wasted, and errors are easy to occur due to various materials, the invention provides a system and a method for adapting to the mainboards with different requirements through independent board cards, so as to solve the technical problems.
In a first aspect, the present invention provides a system for adapting motherboards with different requirements through independent boards, including an independent board and a motherboard;
the independent board card is provided with a first interface;
a second interface, a PCH and a BMC are arranged on the mainboard;
the first interface and the second interface can be matched, and the second interface is connected with both the PCH and the BMC;
and the independent board card is provided with a selection module, and the selection module is used for distinguishing the mainboards with different requirements.
Further, a project number pin group, a SKU number pin group and a BIOS/BMC version pin group are arranged on the first interface and the second interface;
the project number pin group of the second interface is connected with the PCH and the BMC through a project number line bank, the SKU number pin group of the second interface is connected with the PCH and the BMC through a SKU number line bank, and the BIOS/BMC version pin group of the second interface is connected with the PCH and the BMC through a version number group line bank;
the selection module comprises an item number pull-up and pull-down resistor bank, an SKU number pull-up and pull-down resistor bank and a version number pull-up and pull-down resistor bank; the project number pin group of the first interface is connected with the project number up-down pull resistor row, the SKU number pin group of the first interface is connected with the SKU number up-down pull resistor row, and the BIOS/BMC version pin group of the first interface is connected with the version number up-down pull resistor row.
Furthermore, independent board card on-site signal pins, power supply pins and grounding pins are arranged on the first interface and the second interface;
an on-position signal pin of an independent board card of the second interface is connected with a first end of an on-position pull-up resistor, the on-position signal pin is connected with both the PCH and the BMC, a second end of the on-position pull-up resistor is connected with a 3.3V bypass power supply of the mainboard, the on-position signal pin of the independent board card of the first interface is connected with a first end of an on-position pull-down resistor, and a second end of the on-position pull-down resistor is grounded; the power supply pin of the second interface is connected with a 3.3V bypass power supply of the mainboard, and the grounding pin of the second interface is grounded;
the independent board card of the first interface is inserted with the independent board card of the second interface at the position signal pin, the power supply pin of the first interface is inserted with the power supply pin of the second interface, and the grounding pin of the first interface is inserted with the grounding pin of the second interface. The independent board card on-position signal pin is used for indicating whether the independent board card is on position or not.
Further, the item number pin group of the first independent board card interface comprises a plurality of item number pins;
the project number pull-up and pull-down resistor bank comprises a plurality of project number resistor branches connected in parallel, and each project number resistor branch is provided with a project number pull-up resistor or a project number pull-down resistor;
each item number pin of the first interface is connected with an item number pull-up resistor or an item number pull-down resistor of the corresponding item number resistor branch, each item number pull-up resistor is connected with a power supply pin of the first interface, and each item number pull-down resistor is grounded;
the SKU number pin group of the first interface comprises a plurality of SKU number pins;
the SKU number pull-up and pull-down resistor bank comprises a plurality of SKU number resistor branches connected in parallel, and each SKU number resistor branch is provided with a SKU number pull-up resistor or a SKU number pull-down resistor;
each SKU number pin of the first interface is connected with a SKU number pull-up resistor or a SKU number pull-down resistor of the corresponding SKU number resistor branch circuit, each SKU number pull-up resistor is connected with a power supply pin of the first interface, and each SKU number pull-down resistor is grounded;
the BIOS/BMC version pin group of the first interface comprises a plurality of BIOS/BMC version pins;
the version number pull-up and pull-down resistor bank comprises a plurality of parallel version number resistor branches, and each version number resistor branch is provided with a version number pull-up resistor or a version number pull-down resistor;
each BIOS/BMC version pin of the first interface is connected with a version number pull-up resistor or a version number pull-down resistor of the corresponding version number resistor branch, each version number pull-up resistor is connected with a power supply pin of the first interface, and each version number pull-down resistor is grounded. The item number pin group is used for indicating an item number, the SKU number pin group is used for indicating package refinement in an item, and the BIOS/BMC version pin group is used for indicating different BIOS/BMC versions.
Furthermore, the number of the item number pins in the item number pin group of the first interface is eight;
the number of the SKU number pins in the SKU number pin group of the first interface is three;
the number of the BIOS/BMC version pins in the BIOS/BMC version pin group of the first interface is three.
Furthermore, the item number pin group of the first interface is inserted with the item number pin group of the second interface;
the SKU number pin group of the first interface is spliced with the SKU number pin group of the second interface;
the BIOS/BMC version pin group of the first interface is spliced with the BIOS/BMC version pin group of the second interface. The first interface and the second interface are connected in an inserting mode, and upper and lower resistor banks used for distinguishing different items are separated from the main board.
Furthermore, the first interface and the second interface are both provided with reserved pins. Reserved pins can be used for function expansion
In a second aspect, the present invention provides a method for adapting motherboards with different requirements through independent boards based on the first aspect, including the following steps:
s1, distinguishing each mainboard project according to different project requirements, and establishing a true numbering table for each mainboard project;
s2, selecting a pull-up resistor or a pull-down resistor for the resistor branch corresponding to each resistor row on the independent board card according to the truth table of the serial number of each mainboard item;
and S3, inserting the first interface on the independent board card into the second interface of the mainboard.
Further, the step S1 specifically includes the following steps:
s11, distinguishing each mainboard item according to different item requirements, generating item numbers according to different items, generating SKU numbers according to different item packages, and generating version numbers according to different BIOS/BMC versions;
s12, generating different numbers for corresponding main board items according to the item numbers, the SKU numbers and the version numbers of the main board items;
and S13, converting the serial numbers of the mainboard items into binary systems, and generating a true serial number table. The numbering truth table is used for distinguishing different items according to different requirements.
Further, the binary digit number is equal to the sum of the number of the item number pin, the number of the SKU number pin and the BIOS/BMC version pin, and each binary digit corresponds to one pin. Converted to binary, thereby facilitating selection of either a pull-up or pull-down resistor, the pull-up resistor being selected to represent a1 and the pull-down resistor being selected to represent a 0.
Further, the step S2 specifically includes the following steps:
s21, obtaining the value of each binary system in the truth-value table of the serial number and the corresponding pin;
s22, positioning a pin;
s23, acquiring a binary value of the positioning pin, and judging whether the binary value of the positioning pin is 1;
if yes, go to step S24;
if not, go to step S25;
s24, setting a positioning pin corresponding to a resistance branch to connect with a pull-up resistor, setting the pull-up resistor to be connected with a 3.3V bypass power supply of the mainboard, and entering step S26;
s25, setting a positioning pin corresponding to the resistance branch to be connected with a pull-down resistor, setting the pull-down resistor to be grounded, and entering the step S26;
s26, judging whether each pin is positioned;
if yes, go to step S3;
if not, the next pin is located, and the process returns to step S23. And selecting upper and lower resistances according to the median value of the specific truth table, thereby realizing the distinction of different items.
Further, the step S3 specifically includes the following steps:
s31, the independent board card is plugged with the main board through the plugging of the first interface and the second interface;
s32, powering on a 3.3V bypass power supply of the mainboard;
and S33, acquiring the positions of the independent boards by the BMC and the PCH through the position signal pins of the independent boards of the first interface and the second interface, and distinguishing different mainboard items. And providing a signal whether the independent board card is in place for the BMC and the PCH through the in-place signal pin of the independent board card.
The beneficial effect of the invention is that,
according to the system and the method for adapting to the mainboards with different requirements through the independent board cards, the project numbers, the SKU numbers and the version numbers are selected through the design of the pull-up resistors and the pull-down resistors of the independent board cards, so that the different project requirements are met, the waste of human resources is reduced, the reusability of the mainboards is improved, and the design consistency of the mainboards of the server is ensured.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of three pin sets of a system for adapting motherboards with different requirements by using independent boards according to the present invention.
Fig. 2 is a schematic diagram of the system independent board on-site signal pin plugging for adapting to the main boards with different requirements through the independent board.
Fig. 3 is a schematic diagram of a circuit for connecting a system item number pin group of a mainboard with different requirements to an item number pull-down resistor bank of an independent board card through the independent board card.
Fig. 4 is a schematic structural diagram of a first interface and a second interface of a system for adapting to motherboards with different requirements through independent boards according to the present invention.
Fig. 5 is a schematic diagram showing names of pins of the first interface and the second interface of the system for adapting to motherboards with different requirements through independent boards.
FIG. 6 is a schematic diagram of a truth table corresponding to each pin in a group of project number pins of a system first interface for adapting to motherboards with different requirements by using an independent board card.
Fig. 7 is a first flowchart illustrating a method for adapting motherboards with different requirements by using independent boards according to the present invention.
Fig. 8 is a second flowchart illustrating a method for adapting motherboards with different requirements by using independent boards according to the present invention.
In the figure, 1 is an independent board card; 2, a main board; 3-a first interface; 4-a second interface; 5-PCH; 6-BMC; a0-project number pin group; A1-SKU numbering pin group; A2-BIOS/BMC version pin group; p 1-Power Pin; p 2-independent board on-position signal pin; p 3-ground pin; a P3V3_ STBY-3.3V bypass power supply; r0-pull down resistor in place; r100-pull up resistor in place; board ID0-7, eight item number pins; SKU ID0-2, three SKU number pins; FW Ver0-2, three BIOS/BMC version pins; reserved0-2, three Reserved pins; r1 — first resistance; r2 — second resistance; r3 — third resistance; r4-fourth resistor; r5-fifth resistor; r6-sixth resistance; r7 — seventh resistor; r8 — eighth resistance; r9 — ninth resistor; r10 — tenth resistance; r11 — eleventh resistor; r12 — twelfth resistor; r13 — thirteenth resistor; r14-fourteenth resistance; r15-fifteenth resistance; r16 — sixteenth resistance.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
BMC is a substrate management Controller, an acronym for Basebaard Manager Controller.
PCH is the short name of Platform Controller Hub, the integrated south bridge of intel corporation.
Example 1:
as shown in fig. 1, the present invention provides a system for adapting motherboards with different requirements through independent boards, which includes an independent board 1 and a motherboard 2;
the independent board card 1 is provided with a first interface 3;
a second interface 4, a PCH 5 and a BMC 6 are arranged on the mainboard 2;
the first interface 3 and the second interface 4 can be matched, and the second interface 4 is connected with the PCH 5 and the BMC 6;
the independent board card 1 is provided with a selection module, and the selection module is used for distinguishing the mainboards with different requirements. The independent board cards adopt SKU boards, SKU is short for Stock Keeping units, and is an inventory Unit, namely, a basic Unit for inventory in and out measurement, which can be a member, a box, a tray and the like. The server product SKU number is used for distinguishing different packages and refining requirements of respective projects.
Example 2:
as shown in fig. 1 and fig. 2, the present invention provides a system for adapting motherboards with different requirements through independent boards, which includes an independent board 1 and a motherboard 2;
the independent board card 1 is provided with a first interface 3;
a second interface 4, a PCH 5 and a BMC 6 are arranged on the mainboard 2;
the first interface 3 and the second interface 4 can be matched, and the second interface 4 is connected with the PCH 5 and the BMC 6;
the independent board card 1 is provided with a selection module, and the selection module is used for distinguishing the mainboards with different requirements;
the first interface 3 and the second interface 4 are respectively provided with a project number pin group A0, a SKU number pin group A1 and a BIOS/BMC version pin group A2;
the project number pin group A0 of the second interface 3 is connected with the PCH 5 and the BMC 6 through a project number line row, the SKU number pin group A1 of the second interface 4 is connected with the PCH 5 and the BMC 6 through a SKU number line row, and the BIOS/BMC version pin group A2 of the second interface 4 is connected with the PCH 5 and the BMC 6 through a version number group line row;
the selection module comprises an item number pull-up and pull-down resistor bank, an SKU number pull-up and pull-down resistor bank and a version number pull-up and pull-down resistor bank; the project number pin group A0 of the first interface 3 is connected with the project number up-down pull resistor row, the SKU number pin group A1 of the first interface 3 is connected with the SKU number up-down pull resistor row, and the BIOS/BMC version pin group A2 of the first interface 3 is connected with the version number up-down pull resistor row;
the first interface 3 and the second interface 4 are respectively provided with an on-position signal pin p2, a power supply pin p1 and a grounding pin p3 which are independently board-clamped;
an independent board card of the second interface 4 is connected to a first end of an on-position pull-up resistor R100 through an on-position signal pin P2, the on-position signal pin P2 is connected with both PCH 5 and BMC 6, a second end of the on-position pull-up resistor R100 is connected with a 3.3V bypass power supply P3V3_ STBY of a mainboard, an independent board card of the first interface 3 is connected to a first end of an on-position pull-down resistor R0 through an on-position signal pin P2, and a second end of an on-position pull-down resistor R0 is grounded;
a power supply pin P1 of the second interface 4 is connected with a 3.3V bypass power supply P3V3_ STBY of the mainboard, and a grounding pin P3 of the second interface 4 is grounded;
an independent board card of the first interface 3 is plugged with an on-position signal pin p2 of the second interface 4, an independent board card of the first interface 3 is plugged with an on-position signal pin p2 of the second interface 4, a power supply pin p1 of the first interface 3 is plugged with a power supply pin p1 of the second interface 4, and a ground pin p3 of the first interface 3 is plugged with a ground pin p3 of the second interface 4;
the item number pin group a0 of the first interface 3 includes a plurality of item number pins;
the project number pull-up and pull-down resistor bank comprises a plurality of project number resistor branches connected in parallel, and each project number resistor branch is provided with a project number pull-up resistor or a project number pull-down resistor;
each item number pin of the first interface 3 is connected with an item number pull-up resistor or an item number pull-down resistor of the corresponding item number resistor branch, each item number pull-up resistor is connected with the power supply pin p1 of the first interface 3, and each item number pull-down resistor is grounded;
the SKU number pin group a1 of the first interface 3 includes a plurality of SKU number pins;
the SKU number pull-up and pull-down resistor bank comprises a plurality of SKU number resistor branches connected in parallel, and each SKU number resistor branch is provided with a SKU number pull-up resistor or a SKU number pull-down resistor;
each SKU number pin of the first interface 3 is connected with a SKU number pull-up resistor or a SKU number pull-down resistor of the corresponding SKU number resistor branch circuit, each SKU number pull-up resistor is connected with a power supply pin p1 of the first interface 3, and each SKU number pull-down resistor is grounded;
the BIOS/BMC version pin group A2 of the first interface 3 comprises a plurality of BIOS/BMC version pins;
the version number pull-up and pull-down resistor bank comprises a plurality of parallel version number resistor branches, and each version number resistor branch is provided with a version number pull-up resistor or a version number pull-down resistor;
each BIOS/BMC version pin of the first interface 3 is connected with a version number pull-up resistor or a version number pull-down resistor of the corresponding version number resistor branch, each version number pull-up resistor is connected with a power supply pin p1 of the first interface 3, and each version number pull-down resistor is grounded;
the project number pin group A0 of the first interface 3 is spliced with the project number pin group A0 of the second interface 4;
the SKU number pin group A1 of the first interface 3 is spliced with the SKU number pin group A1 of the second interface 4;
the BIOS/BMC version pin group A2 of the first interface 3 is spliced with the BIOS/BMC version pin group A2 of the second interface 4;
reserved pins are arranged on the first interface 3 and the second interface 4.
Example 3:
as shown in fig. 1 and fig. 2, the present invention provides a system for adapting motherboards with different requirements through independent boards, which includes an independent board 1 and a motherboard 2;
the independent board card 1 is provided with a first interface 3;
a second interface 4, a PCH 5 and a BMC 6 are arranged on the mainboard 2;
the first interface 3 and the second interface 4 can be matched, and the second interface 4 is connected with the PCH 5 and the BMC 6;
the independent board card 1 is provided with a selection module, and the selection module is used for distinguishing the mainboards with different requirements;
the first interface 3 and the second interface 4 are respectively provided with a project number pin group A0, a SKU number pin group A1 and a BIOS/BMC version pin group A2;
the project number pin group A0 of the second interface 3 is connected with the PCH 5 and the BMC 6 through a project number line row, the SKU number pin group A1 of the second interface 4 is connected with the PCH 5 and the BMC 6 through a SKU number line row, and the BIOS/BMC version pin group A2 of the second interface 4 is connected with the PCH 5 and the BMC 6 through a version number group line row;
the selection module comprises an item number pull-up and pull-down resistor bank, an SKU number pull-up and pull-down resistor bank and a version number pull-up and pull-down resistor bank;
the project number pin group A0 of the first interface 3 is connected with a project number pull-up and pull-down resistor row, the SKU number pin group A1 of the first interface 3 is connected with a SKU number pull-up and pull-down resistor row, and the BIOS/BMC version pin group A2 of the first interface 3 is connected with a version number pull-up and pull-down resistor row;
the first interface 3 and the second interface 4 are respectively provided with an on-position signal pin p2, a power supply pin p1 and a grounding pin p3 which are independently board-clamped;
an independent board card of the second interface 4 is connected with a first end of an on-position pull-up resistor R100 on an on-position signal pin P2, the on-position signal pin P2 is connected with both PCH 5 and BMC 6, a second end of the on-position pull-up resistor R100 is connected with a 3.3V bypass power supply P3V3_ STBY of a mainboard, an independent board card of the first interface 3 is connected with a first end of an on-position pull-down resistor R0 on an on-position signal pin P2, and a second end of an on-position pull-down resistor R0 is grounded; the value of the in-place pull-down resistor R0 is 100 ohms, and the independent board is used for indicating that the independent board is in place through an in-place signal pin p 2;
a power supply pin P1 of the second interface 4 is connected with a 3.3V bypass power supply P3V3_ STBY of the mainboard, and a grounding pin P3 of the second interface 4 is grounded;
an independent board card of the first interface 3 is plugged with an on-position signal pin p2 of the second interface 4, an independent board card of the first interface 3 is plugged with an on-position signal pin p2 of the second interface 4, a power supply pin p1 of the first interface 3 is plugged with a power supply pin p1 of the second interface 4, and a ground pin p3 of the first interface 3 is plugged with a ground pin p3 of the second interface 4;
the item number pin group A0 of the first interface 3 includes eight item number pins Board ID 0-7;
the project number pull-up and pull-down resistor bank comprises eight project number resistor branches connected in parallel, and a project number pull-up resistor or a project number pull-down resistor is arranged on each project number resistor branch; each item number resistor branch can select one of an item number pull-up resistor and an item number pull-down resistor; the branch of the item number resistor corresponding to the item number pin BOARD ID0 is connected with a first resistor R1 or a second resistor R2, wherein the first resistor R1 is a pull-up resistor, the second resistor R2 is a pull-down resistor, and only one of the first resistor R1 and the second resistor R2 can be selected; the branch of the item number resistor corresponding to the item number pin BOARD ID1 is connected with a third resistor R3 or a fourth resistor R4, wherein the third resistor R3 is a pull-up resistor, the fourth resistor R4 is a pull-down resistor, and only one of the third resistor R3 and the fourth resistor R4 can be selected; a branch of the item number resistor corresponding to the item number pin BOARD ID2 is connected with a fifth resistor R5 or a sixth resistor R6, wherein the fifth resistor R5 is a pull-up resistor, the sixth resistor R6 is a pull-down resistor, and only one of the fifth resistor R5 and the sixth resistor R6 can be selected; a branch of the item number resistor corresponding to the item number pin BOARD ID3 is connected with a seventh resistor R7 or an eighth resistor R8, wherein the seventh resistor R7 is a pull-up resistor, the eighth resistor R8 is a pull-down resistor, and only one of the seventh resistor R7 and the eighth resistor R8 can be selected; the branch of the item number resistor corresponding to the item number pin BOARD ID4 is connected with a ninth resistor R9 or a tenth resistor R10, wherein the ninth resistor R9 is a pull-up resistor, the tenth resistor R10 is a pull-down resistor, and only one of the ninth resistor R9 and the tenth resistor R10 can be selected; the branch of the project number resistor corresponding to the project number pin BOARD ID5 is connected with an eleventh resistor R11 or a twelfth resistor R12, wherein the eleventh resistor R11 is a pull-up resistor, the twelfth resistor R12 is a pull-down resistor, and only one of the eleventh resistor R11 and the twelfth resistor R12 can be selected; a branch of the item number resistor corresponding to the item number pin BOARD ID6 is connected with a thirteenth resistor R13 or a fourteenth resistor R14, wherein the thirteenth resistor R13 is a pull-up resistor, the fourteenth resistor R14 is a pull-down resistor, and only one of the thirteenth resistor R13 and the fourteenth resistor R14 can be selected; a branch of the item number resistor corresponding to the item number pin BOARD ID7 is connected with a fifteenth resistor R15 or a sixteenth resistor R16, wherein the fifteenth resistor R15 is a pull-up resistor, the sixteenth resistor R16 is a pull-down resistor, and only one of the fifteenth resistor R15 and the sixteenth resistor R16 can be selected; the unselected resistor is identified by "CN" to indicate that no device is loaded, as shown in fig. 3, taking an item number pin Board _ ID0 as an example, the corresponding pull-up resistor is a first resistor R1, the pull-down resistor is a second resistor R2, wherein the second resistor R2 is identified by "CN", i.e., no device is loaded, and the first resistor R1 does not have an "CN", i.e., no device is loaded, so that Board _ ID0 is at a level of 3.3V, i.e., a high level, and after passing through the first interface 3 and the second interface 4, the PCH 5 and BMC 6 at the motherboard 2 end can be identified as "1"; when the first resistor R1 is not loaded and the second resistor R2 is loaded, the resistance is expressed as 0; specifically, the selection is carried out according to the corresponding value of the item number pin in the number truth table; FIG. 6 is a diagram illustrating the corresponding values of the item number pins in the truth table of the number of different items; the item column represents different items, namely an item A, an item B, an item C, an item D and the like, different items are set by maintaining the truth table, the setting of the pull-up and pull-down resistors of different independent boards is determined, and different items are represented by setting the sub-truth table; the truth table corresponding to the SKU number pin SKU ID0-2 is the same as the principle of the project number pin Board ID0-7, and the pull-up and pull-down mode is adopted to carry out pull-up and pull-down on the resistor according to different project package requirements; the corresponding truth table of the BIOS/BMC version pin FW Ver0-2 is the same as the principle of the SKU number pin SKU ID0-2, and is used for distinguishing different BIOS/BMC versions;
each item number pin of the first interface 3 is connected with an item number pull-up resistor or an item number pull-down resistor of the corresponding item number resistor branch, each item number pull-up resistor is connected with the power supply pin p1 of the first interface 3, and each item number pull-down resistor is grounded;
the SKU number pin group A1 of the first interface 3 includes three SKU number pins SKU ID 0-2;
the SKU number pull-up and pull-down resistor bank comprises three SKU number resistor branches connected in parallel, and a SKU number pull-up resistor or a SKU number pull-down resistor is arranged on each SKU number resistor branch;
each SKU number pin of the first interface 3 is connected with a SKU number pull-up resistor or a SKU number pull-down resistor of the corresponding SKU number resistor branch circuit, each SKU number pull-up resistor is connected with a power supply pin p1 of the first interface 3, and each SKU number pull-down resistor is grounded;
the BIOS/BMC version pin group A2 of the first interface 3 comprises three BIOS/BMC version pins FW Ver 0-2;
the version number pull-up and pull-down resistor bank comprises three parallel version number resistor branches, and each version number resistor branch is provided with a version number pull-up resistor or a version number pull-down resistor;
each BIOS/BMC version pin of the first interface 3 is connected with a version number pull-up resistor or a version number pull-down resistor of the corresponding version number resistor branch, each version number pull-up resistor is connected with a power supply pin p1 of the first interface 3, and each version number pull-down resistor is grounded;
the project number pin group A0 of the first interface 3 is spliced with the project number pin group A0 of the second interface 4;
the SKU number pin group A1 of the first interface 3 is spliced with the SKU number pin group A1 of the second interface 4;
the BIOS/BMC version pin group A2 of the first interface 3 is spliced with the BIOS/BMC version pin group A2 of the second interface 4;
the first interface 3 and the second interface 4 are shown in fig. 4;
three Reserved pins Reserved0-2 are further disposed on the first interface 3 and the second interface 4, and specific names and functions of the pins are shown in fig. 5.
Example 4:
as shown in fig. 7, the present invention provides a method for adapting motherboards with different requirements through independent boards according to embodiment 1, embodiment 2, or embodiment 3, including the following steps:
s1, distinguishing each mainboard project according to different project requirements, and establishing a true numbering table for each mainboard project;
s2, selecting a pull-up resistor or a pull-down resistor for the resistor branch corresponding to each resistor row on the independent board card according to the truth table of the serial number of each mainboard item;
and S3, inserting the first interface on the independent board card into the second interface of the mainboard.
Example 5:
as shown in fig. 8, the present invention provides a method for adapting motherboards with different requirements through independent boards, which includes the following steps:
s1, distinguishing each mainboard project according to different project requirements, and establishing a true numbering table for each mainboard project; the method comprises the following specific steps:
s11, distinguishing each mainboard item according to different item requirements, generating item numbers according to different items, generating SKU numbers according to different item packages, and generating version numbers according to different BIOS/BMC versions;
s12, generating different numbers for corresponding main board items according to the item numbers, the SKU numbers and the version numbers of the main board items;
s13, converting the serial numbers of all the mainboard items into binary systems, and generating a true serial number table; the binary digits and the sum of the number of the item number pins, the number of the SKU number pins and the number of the BIOS/BMC version pins, and each binary digit corresponds to one pin;
s2, selecting a pull-up resistor or a pull-down resistor for the resistor branch corresponding to each resistor row on the independent board card according to the truth table of the serial number of each mainboard item; the method comprises the following specific steps:
s21, obtaining the value of each binary system in the truth-value table of the serial number and the corresponding pin;
s22, positioning a pin;
s23, acquiring a binary value of the positioning pin, and judging whether the binary value of the positioning pin is 1;
if yes, go to step S24;
if not, go to step S25;
s24, setting a positioning pin corresponding to a resistance branch to connect with a pull-up resistor, setting the pull-up resistor to be connected with a 3.3V bypass power supply of the mainboard, and entering step S26;
s25, setting a positioning pin corresponding to the resistance branch to be connected with a pull-down resistor, setting the pull-down resistor to be grounded, and entering the step S26;
s26, judging whether each pin is positioned;
if yes, go to step S3;
if not, positioning the next pin and returning to the step S23;
s3, inserting a first interface on the independent board card into a second interface of the main board; the method comprises the following specific steps:
s31, the independent board card is plugged with the main board through the plugging of the first interface and the second interface;
s32, powering on a 3.3V bypass power supply of the mainboard;
and S33, acquiring the positions of the independent boards by the BMC and the PCH through the position signal pins of the independent boards of the first interface and the second interface, and distinguishing different mainboard items.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A system for adapting main boards with different requirements through independent board cards is characterized by comprising an independent board card (1) and a main board (2);
the independent board card (1) is provided with a first interface (3);
a second interface (4), a PCH (5) and a BMC (6) are arranged on the mainboard (2);
the first interface (3) and the second interface (4) can be matched, and the second interface (4) is connected with the PCH (5) and the BMC (6);
the independent board card (1) is provided with a selection module, and the selection module is used for distinguishing the mainboards with different requirements.
2. The system for adapting motherboards with different requirements by using independent boards as claimed in claim 1, wherein the first interface (3) and the second interface (4) are each provided with a project number pin group (a0), a SKU number pin group (a1) and a BIOS/BMC version pin group (a 2);
the project number pin group (A0) of the second interface (3) is connected with the PCH (5) and the BMC (6) through a project number line row, the SKU number pin group (A1) of the second interface (4) is connected with the PCH (5) and the BMC (6) through a SKU number line row, and the BIOS/BMC version pin group (A2) of the second interface (4) is connected with the PCH (5) and the BMC (6) through a version number group line row;
the selection module comprises an item number pull-up and pull-down resistor bank, an SKU number pull-up and pull-down resistor bank and a version number pull-up and pull-down resistor bank;
the project number pin group (A0) of the first interface (3) is connected with the project number up-down pull resistor row, the SKU number pin group (A1) of the first interface (3) is connected with the SKU number up-down pull resistor row, and the BIOS/BMC version pin group (A2) of the first interface (3) is connected with the version number up-down pull resistor row.
3. The system for adapting motherboards with different requirements by using independent boards as claimed in claim 1, wherein the first interface (3) and the second interface (4) are each provided with an independent board on-site signal pin (p2), a power supply pin (p1) and a ground pin (p 3);
an independent board card on-site signal pin (P2) of the second interface (4) is connected with a first end of an on-site pull-up resistor (R100), the on-site signal pin (P2) is connected with both the PCH (5) and the BMC (6), a second end of the on-site pull-up resistor (R100) is connected with a 3.3V bypass power supply (P3V3_ STBY) of the mainboard, an independent board card on-site signal pin (P2) of the first interface (3) is connected with a first end of an on-site pull-down resistor (R0), and a second end of the on-site pull-down resistor (R0) is grounded;
a power supply pin (P1) of the second interface (4) is connected with a 3.3V bypass power supply (P3V3_ STBY) of the mainboard, and a grounding pin (P3) of the second interface (4) is grounded;
an independent board card of the first interface (3) is plugged with an on-site signal pin (p2) of an independent board card of the second interface (4) in an on-site signal pin (p2), a power supply pin (p1) of the first interface (3) is plugged with a power supply pin (p1) of the second interface (4), and a ground pin (p3) of the first interface (3) is plugged with a ground pin (p3) of the second interface (4).
4. A system for adapting boards of different needs by means of separate boards according to claim 3, characterised in that the group of item number pins (a0) of the first interface (3) comprises several item number pins;
the project number pull-up and pull-down resistor bank comprises a plurality of project number resistor branches connected in parallel, and each project number resistor branch is provided with a project number pull-up resistor or a project number pull-down resistor;
each item number pin of the first interface (3) is connected with an item number pull-up resistor or an item number pull-down resistor of the corresponding item number resistor branch, each item number pull-up resistor is connected with a power supply pin (p1) of the first interface (3), and each item number pull-down resistor is grounded;
the SKU number pin group (A1) of the first interface (3) comprises a plurality of SKU number pins;
the SKU number pull-up and pull-down resistor bank comprises a plurality of SKU number resistor branches connected in parallel, and each SKU number resistor branch is provided with a SKU number pull-up resistor or a SKU number pull-down resistor;
each SKU number pin of the first interface (3) is connected with a SKU number pull-up resistor or a SKU number pull-down resistor of the corresponding SKU number resistor branch circuit, each SKU number pull-up resistor is connected with a power supply pin (p1) of the first interface (3), and each SKU number pull-down resistor is grounded;
the BIOS/BMC version pin group (A2) of the first interface (3) comprises a plurality of BIOS/BMC version pins;
the version number pull-up and pull-down resistor bank comprises a plurality of parallel version number resistor branches, and each version number resistor branch is provided with a version number pull-up resistor or a version number pull-down resistor;
each BIOS/BMC version pin of the first interface (3) is connected with a version number pull-up resistor or a version number pull-down resistor of the corresponding version number resistor branch, each version number pull-up resistor is connected with a power supply pin (p1) of the first interface (3), and each version number pull-down resistor is grounded.
5. System for adapting boards of different needs by means of separate boards according to claim 1, characterised in that the group of project number pins (a0) of the first interface (3) is plugged with the group of project number pins (a0) of the second interface (4);
the SKU number pin group (A1) of the first interface (3) is spliced with the SKU number pin group (A1) of the second interface (4);
the BIOS/BMC version pin group (A2) of the first interface (3) is plugged into the BIOS/BMC version pin group (A2) of the second interface (4).
6. A method for adapting boards with different requirements by independent boards according to any of the claims 1 to 5, comprising the following steps:
s1, distinguishing each mainboard project according to different project requirements, and establishing a true numbering table for each mainboard project;
s2, selecting a pull-up resistor or a pull-down resistor for the resistor branch corresponding to each resistor row on the independent board card according to the truth table of the serial number of each mainboard item;
and S3, inserting the first interface on the independent board card into the second interface of the mainboard.
7. The method for adapting motherboards with different requirements through independent boards as claimed in claim 6, wherein the step S1 comprises the following steps:
s11, distinguishing each mainboard item according to different item requirements, generating item numbers according to different items, generating SKU numbers according to different item packages, and generating version numbers according to different BIOS/BMC versions;
s12, generating different numbers for corresponding main board items according to the item numbers, the SKU numbers and the version numbers of the main board items;
and S13, converting the serial numbers of the mainboard items into binary systems, and generating a true serial number table.
8. The method of claim 7, wherein the binary number is the sum of the number of the item number pin and the SKU number pin and the BIOS/BMC version pin, and each binary number corresponds to one pin.
9. The method for adapting motherboards with different requirements through independent boards as claimed in claim 6, wherein the step S2 comprises the following steps:
s21, obtaining the value of each binary system in the truth-value table of the serial number and the corresponding pin;
s22, positioning a pin;
s23, acquiring a binary value of the positioning pin, and judging whether the binary value of the positioning pin is 1;
if yes, go to step S24;
if not, go to step S25;
s24, setting a positioning pin corresponding to a resistance branch to connect with a pull-up resistor, setting the pull-up resistor to be connected with a 3.3V bypass power supply of the mainboard, and entering step S26;
s25, setting a positioning pin corresponding to the resistance branch to be connected with a pull-down resistor, setting the pull-down resistor to be grounded, and entering the step S26;
s26, judging whether each pin is positioned;
if yes, go to step S3;
if not, the next pin is located, and the process returns to step S23.
10. The method for adapting motherboards with different requirements through independent boards as claimed in claim 6, wherein the step S3 comprises the following steps:
s31, the independent board card is plugged with the main board through the plugging of the first interface and the second interface;
s32, powering on a 3.3V bypass power supply of the mainboard;
and S33, acquiring the positions of the independent boards by the BMC and the PCH through the position signal pins of the independent boards of the first interface and the second interface, and distinguishing different mainboard items.
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| CN102880527A (en) * | 2011-07-13 | 2013-01-16 | 英业达股份有限公司 | Data recovery method of baseboard management controller |
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