CN113760058B - System and method for adapting to mainboards with different requirements through independent board cards - Google Patents
System and method for adapting to mainboards with different requirements through independent board cards Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/184—Mounting of motherboards
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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- H—ELECTRICITY
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- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
- H01R12/712—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit
- H01R12/716—Coupling device provided on the PCB
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
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- H01R24/00—Two-part coupling devices, or either of their cooperating parts, characterised by their overall structure
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- H—ELECTRICITY
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- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R2201/00—Connectors or connections adapted for particular applications
- H01R2201/06—Connectors or connections adapted for particular applications for computer periphery
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a system and a method for adapting to mainboards with different requirements through independent boards, wherein the system comprises the independent boards and the mainboards; the independent board card is provided with a first interface; the main board is provided with a second interface, PCH and BMC; the first interface is spliced with the second interface, and the second interface is connected with the PCH and the BMC; the first interface and the second interface are respectively provided with a project number, a SKU number and a BIOS/BMC version pin group; each pin group is connected with PCH and BMC through corresponding wire rows; each pin is respectively connected with a corresponding pull-up resistor row. According to the invention, through the design of the pull-up resistor and the pull-down resistor on the independent board card, the project number, the SKU number and the version number are selected, so that the requirements of different projects are met, the waste of human resources is reduced, the reusability of the main board is improved, and the consistency of the design of the main board of the server is ensured.
Description
Technical Field
The invention belongs to the technical field of motherboard design, and particularly relates to a system and a method for adapting to motherboards with different requirements through independent boards.
Background
Along with the continuous updating and upgrading of the Intel x86 architecture, the placement positions of key devices such as a CPU, a memory, a PCH and the like in the server are gradually solidified under the proposal of the Intel, and each server designer is basically partially modified according to the Intel reference design so as to adapt to the requirements of each family. However, with the basic sizing of the mechanism housing of the server, the main board card such as the motherboard to be placed inside is limited in a certain range, so that the occupied space of the motherboard is limited, that is, the board card size is required. Under the condition that the functions of the servers are gradually the same, after receiving the server requirements proposed by manufacturers, firstly, estimating the occupied space of the main board, and then designing the public board, so that the main board is compatible with the designs of various families, and the labor cost and the material cost brought by independently designing the main board for each customer by taking the main board as the public board can be reduced.
However, the design of the public board needs to be customized developed and set according to the needs of each customer, different customers need to maintain a plurality of main board BOMs according to different needs, and the main board BOMs need to be maintained by manpower of different projects, so that manpower waste is caused, and errors are easy to occur due to various materials.
It is therefore desirable to provide a system and method for adapting to different requirements of a motherboard by using an independent board card.
Disclosure of Invention
Aiming at the defects that the main board in the prior art is used as a male board design, a plurality of main boards BOM are required to be maintained, labor is wasted, and errors are easy to occur due to various materials, the invention provides a system and a method for adapting main boards with different requirements through independent board cards, and aims to solve the technical problems.
In a first aspect, the present invention provides a system for adapting to a motherboard with different requirements through an independent board, including the independent board and the motherboard;
the independent board card is provided with a first interface;
the main board is provided with a second interface, PCH and BMC;
the first interface and the second interface can be matched, and the second interface is connected with PCH and BMC;
and a selection module is arranged on the independent board card and used for realizing the distinction of the main boards with different requirements.
Further, the first interface and the second interface are respectively provided with a project number pin group, a SKU number pin group and a BIOS/BMC version pin group;
the item number pin group of the second interface is connected with the PCH and the BMC through the item number line bank, the SKU number pin group of the second interface is connected with the PCH and the BMC through the SKU number line bank, and the BIOS/BMC version pin group of the second interface is connected with the PCH and the BMC through the version number line bank;
the selection module comprises a project number pull-up and pull-down resistor bank, a SKU number pull-up and pull-down resistor bank and a version number pull-up and pull-down resistor bank; the item number pin group of the first interface is connected with the item number pull-up resistor bank, the SKU number pin group of the first interface is connected with the SKU number pull-up resistor bank, and the BIOS/BMC version pin group of the first interface is connected with the version number pull-up resistor bank.
Further, the first interface and the second interface are respectively provided with an independent board card in-place signal pin, a power pin and a grounding pin;
the independent board card of the second interface is connected with the first end of the on-site pull-up resistor through the on-site signal pin, and is connected with PCH and BMC, the second end of the on-site pull-up resistor is connected with the 3.3V bypass power supply of the main board, the independent board card of the first interface is connected with the first end of the on-site pull-down resistor through the on-site signal pin, and the second end of the on-site pull-down resistor is grounded; the power pin of the second interface is connected with a 3.3V bypass power supply of the main board, and the grounding pin of the second interface is grounded;
the independent board card of the first interface is inserted with the independent board card of the second interface, the power supply pin of the first interface is inserted with the power supply pin of the second interface, and the grounding pin of the first interface is inserted with the grounding pin of the second interface. The independent board card in-place signal pin is used for indicating whether the independent board card is in place or not.
Further, the project number pin group of the first independent board interface comprises a plurality of project number pins;
the project number pull-up resistor bank comprises a plurality of project number resistor branches connected in parallel, and each project number resistor branch is provided with a project number pull-up resistor or a project number pull-down resistor;
each item number pin of the first interface is connected with an item number pull-up resistor or an item number pull-down resistor of a corresponding item number resistor branch, each item number pull-up resistor is connected with a power pin of the first interface, and each item number pull-down resistor is grounded;
the SKU number pin group of the first interface comprises a plurality of SKU number pins;
the SKU number pull-up resistor bank comprises a plurality of SKU number resistor branches connected in parallel, and each SKU number resistor branch is provided with a SKU number pull-up resistor or a SKU number pull-down resistor;
each SKU number pin of the first interface is connected with a SKU number pull-up resistor or a SKU number pull-down resistor of a corresponding SKU number resistor branch, each SKU number pull-up resistor is connected with a power pin of the first interface, and each SKU number pull-down resistor is grounded;
the BIOS/BMC version pin group of the first interface comprises a plurality of BIOS/BMC version pins;
the version number pull-up resistor bank comprises a plurality of version number resistor branches connected in parallel, and each version number resistor branch is provided with a version number pull-up resistor or a version number pull-down resistor;
each BIOS/BMC version pin of the first interface is connected with a version number pull-up resistor or a version number pull-down resistor of a corresponding version number resistor branch, each version number pull-up resistor is connected with a power pin of the first interface, and each version number pull-down resistor is grounded. The project number pin set is used for indicating project numbers, the SKU number pin set is used for indicating package refinement in projects, and the BIOS/BMC version pin set is used for indicating different BIOS/BMC versions.
Further, the number of item number pins in the item number pin group of the first interface is eight;
the number of SKU number pins in the SKU number pin group of the first interface is three;
the number of BIOS/BMC version pins in the BIOS/BMC version pin group of the first interface is three.
Further, the project number pin group of the first interface is spliced with the project number pin group of the second interface;
the SKU number pin group of the first interface is spliced with the SKU number pin group of the second interface;
the BIOS/BMC version pin group of the first interface is spliced with the BIOS/BMC version pin group of the second interface. The first interface and the second interface are spliced to separate the upper resistor bank and the lower resistor bank for distinguishing different projects from the main board.
Further, reserved pins are arranged on the first interface and the second interface. Reserved pins can be used for function expansion
In a second aspect, the present invention provides a method for adapting to boards with different requirements through independent boards based on the first aspect, including the following steps:
s1, distinguishing each main board project according to project requirements, and establishing a numbering truth table for each main board project;
s2, selecting a pull-up resistor or a pull-down resistor for a resistor branch corresponding to each resistor bank on the independent board according to a numbering truth table of each main board item;
s3, plugging the first interface on the independent board card with the second interface of the main board.
Further, the specific steps of step S1 are as follows:
s11, dividing each main board project according to project requirements, generating project numbers according to project differences, generating SKU numbers according to project packages, and generating version numbers according to BIOS/BMC versions;
s12, generating different numbers for the corresponding main board items according to the item numbers, the SKU numbers and the version numbers of the main board items;
s13, converting numbers of all main board items into binary numbers, and generating a number truth table. The numbering truth table is used to distinguish different items according to different requirements.
Further, the binary digits sum to the project number pins and SKU number pins and BIOS/BMC version pins, and each binary digit corresponds to one pin. And converted to binary, thereby facilitating the selection of either a pull-up or a pull-down resistor, the selection of which is denoted as 1, and the selection of which is denoted as 0.
Further, the specific steps of step S2 are as follows:
s21, acquiring the values of each binary system in the numbering truth table and corresponding pins thereof;
s22, positioning a pin;
s23, acquiring a binary value of the positioning pin, and judging whether the binary value of the positioning pin is 1;
if yes, go to step S24;
if not, go to step S25;
s24, setting a resistor branch corresponding to a positioning pin to be connected with a pull-up resistor, setting the pull-up resistor to be connected with a 3.3V bypass power supply of the main board, and entering step S26;
s25, setting a resistor branch corresponding to the positioning pin to be connected with a pull-down resistor, setting the pull-down resistor to be grounded, and entering step S26;
s26, judging whether all pins are positioned;
if yes, enter step S3;
if not, the next pin is located, and the process returns to step S23. And selecting upper and lower resistors according to the values in the specific truth table, so that the distinction of different items is realized.
Further, the specific steps of step S3 are as follows:
s31, through the plug-in connection of the first interface and the second interface, the plug-in connection of the independent board card and the main board is realized;
s32, powering on a 3.3V bypass power supply of the main board;
s33, the BMC and the PCH acquire the positions of the independent boards through independent board in-position signal pins of the first interface and the second interface, and the distinction of different mainboard projects is realized. And providing a signal whether the independent board card is in place or not to the BMC and the PCH through the independent board card in-place signal pin.
The invention has the advantages that,
according to the system and the method for adapting to the mainboards with different requirements through the independent board, provided by the invention, project numbers, SKU numbers and version numbers are selected through the design of the pull-up resistor and the pull-down resistor on the independent board, so that the requirements of different projects are met, the manpower resource waste is reduced, the reusability of the mainboards is improved, and the consistency of the design of the mainboards of the server is ensured.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
It can be seen that the present invention has outstanding substantial features and significant advances over the prior art, as well as the benefits of its implementation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic diagram of plugging three pin groups of a system for adapting to different-demand mainboards through independent boards.
Fig. 2 is a schematic diagram of plugging in signal pins of a system independent board card adapted to different requirement motherboards through the independent board card.
FIG. 3 is a schematic diagram of a system project number pin set adapted to different requirement motherboards by an independent board card in a circuit for connecting the independent board card with a project number pull-up resistor bank.
Fig. 4 is a schematic diagram of a system first interface and a system second interface structure for adapting to different requirement mainboards through independent boards according to the present invention.
Fig. 5 is a schematic diagram of pin names of a first interface and a second interface of a system adapted to different requirement motherboards through an independent board card according to the present invention.
FIG. 6 is a diagram showing the true value representing intent of each pin in the project number pin set of the first interface of the system adapted to different requirement motherboards by the independent board card according to the present invention.
Fig. 7 is a flowchart of a method for adapting to different-demand motherboards by using an independent board card according to the present invention.
Fig. 8 is a second flowchart of a method for adapting to different-demand motherboards by using an independent board card according to the present invention.
In the figure, 1-independent board card; 2-a main board; 3-a first interface; 4-a second interface; 5-PCH;6-BMC; a0-item number pin set; A1-SKU number pin group; A2-BIOS/BMC version pin set; p 1-power pin; p 2-independent board on-bit signal pins; p 3-ground pin; P3V3_STBY-3.3V bypass power supply; r0-pull-down resistor in place; r100-bit pull-up resistor; board ID0-7, eight item number pins; SKU ID0-2, three SKU number pins; FW Ver0-2, three BIOS/BMC version pins; reserved0-2, three Reserved pins; r1-a first resistor; r2-a second resistor; r3-a third resistor; r4-fourth resistor; r5-fifth resistor; r6-sixth resistance; r7-seventh resistor; r8-eighth resistor; r9-ninth resistance; r10-tenth resistor; r11-eleventh resistor; r12-twelfth resistor; r13-thirteenth resistance; r14-fourteenth resistors; r15-fifteenth resistor; r16-sixteenth resistance.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
BMC, abbreviated as Baseboard Manager Controller, baseboard management controller.
PCH is the integrated south bridge of Platform Controller Hub, intel corporation.
Example 1:
as shown in fig. 1, the present invention provides a system for adapting to different requirements of a motherboard by using an independent board card, comprising an independent board card 1 and a motherboard 2;
the independent board card 1 is provided with a first interface 3;
the main board 2 is provided with a second interface 4, a PCH 5 and a BMC 6;
the first interface 3 and the second interface 4 can be matched, and the second interface 4 is connected with the PCH 5 and the BMC 6;
the independent board card 1 is provided with a selection module which is used for realizing the distinction of the main boards with different requirements. The independent board card adopts SKU board, SKU is Stock Keeping Unit for short, is a stock quantity unit, namely a basic unit for stock in-out metering, and can be a unit of parts, boxes, trays and the like. Products are now being extended to product unification numbers, each corresponding to a unique SKU number, which is used for distinguishing different packages and refinement requirements for respective items for the server product SKU number.
Example 2:
as shown in fig. 1 and 2, the present invention provides a system for adapting to different requirements of a motherboard by using an independent board card, comprising an independent board card 1 and a motherboard 2;
the independent board card 1 is provided with a first interface 3;
the main board 2 is provided with a second interface 4, a PCH 5 and a BMC 6;
the first interface 3 and the second interface 4 can be matched, and the second interface 4 is connected with the PCH 5 and the BMC 6;
the independent board card 1 is provided with a selection module which is used for distinguishing the main boards with different requirements;
the first interface 3 and the second interface 4 are respectively provided with a project number pin group A0, a SKU number pin group A1 and a BIOS/BMC version pin group A2;
the item number pin group A0 of the second interface 3 is connected with the PCH 5 and the BMC 6 through item number line rows, the SKU number pin group A1 of the second interface 4 is connected with the PCH 5 and the BMC 6 through SKU number line rows, and the BIOS/BMC version pin group A2 of the second interface 4 is connected with the PCH 5 and the BMC 6 through version number group line rows;
the selection module comprises a project number pull-up and pull-down resistor bank, a SKU number pull-up and pull-down resistor bank and a version number pull-up and pull-down resistor bank; the item number pin group A0 of the first interface 3 is connected with the item number pull-up resistor bank, the SKU number pin group A1 of the first interface 3 is connected with the SKU number pull-up resistor bank, and the BIOS/BMC version pin group A2 of the first interface 3 is connected with the version number pull-up resistor bank;
the first interface 3 and the second interface 4 are respectively provided with an independent board card bit signal pin p2, a power supply pin p1 and a grounding pin p3;
the independent board card of the second interface 4 is connected with the first end of the bit pull-up resistor R100 at the bit signal pin P2, and the bit signal pin P2, PCH 5 and BMC 6 are connected, the second end of the bit pull-up resistor R100 is connected with the 3.3V bypass power P3V3_STBY of the main board, the independent board card of the first interface 3 is connected with the first end of the bit pull-down resistor R0 at the bit signal pin P2, and the second end of the bit pull-down resistor R0 is grounded;
the power pin P1 of the second interface 4 is connected with the 3.3V bypass power P3V3_STBY of the main board, and the ground pin P3 of the second interface 4 is grounded;
the independent board card of the first interface 3 is inserted into the in-place signal pin p2 of the independent board card of the second interface 4, the power pin p1 of the first interface 3 is inserted into the power pin p1 of the second interface 4, and the grounding pin p3 of the first interface 3 is inserted into the grounding pin p3 of the second interface 4;
the item number pin group A0 of the first interface 3 comprises a plurality of item number pins;
the project number pull-up resistor bank comprises a plurality of project number resistor branches connected in parallel, and each project number resistor branch is provided with a project number pull-up resistor or a project number pull-down resistor;
each item number pin of the first interface 3 is connected with an item number pull-up resistor or an item number pull-down resistor of a corresponding item number resistor branch, each item number pull-up resistor is connected with a power pin p1 of the first interface 3, and each item number pull-down resistor is grounded;
the SKU number pin group A1 of the first interface 3 includes a plurality of SKU number pins;
the SKU number pull-up resistor bank comprises a plurality of SKU number resistor branches connected in parallel, and each SKU number resistor branch is provided with a SKU number pull-up resistor or a SKU number pull-down resistor;
each SKU number pin of the first interface 3 is connected with a SKU number pull-up resistor or a SKU number pull-down resistor of a corresponding SKU number resistor branch, each SKU number pull-up resistor is connected with a power pin p1 of the first interface 3, and each SKU number pull-down resistor is grounded;
the BIOS/BMC version pin group A2 of the first interface 3 comprises a plurality of BIOS/BMC version pins;
the version number pull-up resistor bank comprises a plurality of version number resistor branches connected in parallel, and each version number resistor branch is provided with a version number pull-up resistor or a version number pull-down resistor;
each BIOS/BMC version pin of the first interface 3 is connected with a version number pull-up resistor or a version number pull-down resistor of a corresponding version number resistor branch, each version number pull-up resistor is connected with a power pin p1 of the first interface 3, and each version number pull-down resistor is grounded;
the item number pin group A0 of the first interface 3 is spliced with the item number pin group A0 of the second interface 4;
the SKU number pin group A1 of the first interface 3 is spliced with the SKU number pin group A1 of the second interface 4;
the BIOS/BMC version pin group A2 of the first interface 3 is spliced with the BIOS/BMC version pin group A2 of the second interface 4;
reserved pins are arranged on the first interface 3 and the second interface 4.
Example 3:
as shown in fig. 1 and 2, the present invention provides a system for adapting to different requirements of a motherboard by using an independent board card, comprising an independent board card 1 and a motherboard 2;
the independent board card 1 is provided with a first interface 3;
the main board 2 is provided with a second interface 4, a PCH 5 and a BMC 6;
the first interface 3 and the second interface 4 can be matched, and the second interface 4 is connected with the PCH 5 and the BMC 6;
the independent board card 1 is provided with a selection module which is used for distinguishing the main boards with different requirements;
the first interface 3 and the second interface 4 are respectively provided with a project number pin group A0, a SKU number pin group A1 and a BIOS/BMC version pin group A2;
the item number pin group A0 of the second interface 3 is connected with the PCH 5 and the BMC 6 through item number line rows, the SKU number pin group A1 of the second interface 4 is connected with the PCH 5 and the BMC 6 through SKU number line rows, and the BIOS/BMC version pin group A2 of the second interface 4 is connected with the PCH 5 and the BMC 6 through version number group line rows;
the selection module comprises a project number pull-up and pull-down resistor bank, a SKU number pull-up and pull-down resistor bank and a version number pull-up and pull-down resistor bank;
the item number pin group A0 of the first interface 3 is connected with an item number pull-up resistor bank, the SKU number pin group A1 of the first interface 3 is connected with a SKU number pull-up resistor bank, and the BIOS/BMC version pin group A2 of the first interface 3 is connected with a version number pull-up resistor bank;
the first interface 3 and the second interface 4 are respectively provided with an independent board card bit signal pin p2, a power supply pin p1 and a grounding pin p3;
the independent board card of the second interface 4 is connected with the first end of the bit pull-up resistor R100 at the bit signal pin P2, and the bit signal pin P2, PCH 5 and BMC 6 are connected, the second end of the bit pull-up resistor R100 is connected with the 3.3V bypass power P3V3_STBY of the main board, the independent board card of the first interface 3 is connected with the first end of the bit pull-down resistor R0 at the bit signal pin P2, and the second end of the bit pull-down resistor R0 is grounded; the value of the pull-down resistor R0 in place takes 100 ohms, and the signal pin p2 of the independent board card in place is used for indicating the independent board card in place;
the power pin P1 of the second interface 4 is connected with the 3.3V bypass power P3V3_STBY of the main board, and the ground pin P3 of the second interface 4 is grounded;
the independent board card of the first interface 3 is inserted into the in-place signal pin p2 of the independent board card of the second interface 4, the power pin p1 of the first interface 3 is inserted into the power pin p1 of the second interface 4, and the grounding pin p3 of the first interface 3 is inserted into the grounding pin p3 of the second interface 4;
the item number pin group A0 of the first interface 3 includes eight item number pins Board ID0-7;
the project number pull-up resistor bank comprises eight parallel project number resistor branches, and each project number resistor branch is provided with a project number pull-up resistor or a project number pull-down resistor; each item number resistor branch can select one of an item number pull-up resistor and an item number pull-down resistor; the project number resistor branch corresponding to the project number pin BOARD ID0 is connected with a first resistor R1 or a second resistor R2, wherein the first resistor R1 is a pull-up resistor, the second resistor R2 is a pull-down resistor, and only one of the first resistor R1 and the second resistor R2 can be selected; the project number resistor branch corresponding to the project number pin BOARD ID1 is connected with a third resistor R3 or a fourth resistor R4, wherein the third resistor R3 is a pull-up resistor, the fourth resistor R4 is a pull-down resistor, and only one of the third resistor R3 and the fourth resistor R4 can be selected; the project number resistor branch corresponding to the project number pin BOARD ID2 is connected with a fifth resistor R5 or a sixth resistor R6, wherein the fifth resistor R5 is a pull-up resistor, the sixth resistor R6 is a pull-down resistor, and only one of the fifth resistor R5 and the sixth resistor R6 can be selected; the project number resistor branch corresponding to the project number pin BOARD ID3 is connected with a seventh resistor R7 or an eighth resistor R8, wherein the seventh resistor R7 is a pull-up resistor, the eighth resistor R8 is a pull-down resistor, and only one of the seventh resistor R7 and the eighth resistor R8 can be selected; the project number resistor branch corresponding to the project number pin BOARD ID4 is connected with a ninth resistor R9 or a tenth resistor R10, wherein the ninth resistor R9 is a pull-up resistor, the tenth resistor R10 is a pull-down resistor, and only one of the ninth resistor R9 and the tenth resistor R10 can be selected; the project number resistor branch corresponding to the project number pin BOARD ID5 is connected with an eleventh resistor R11 or a twelfth resistor R12, wherein the eleventh resistor R11 is a pull-up resistor, the twelfth resistor R12 is a pull-down resistor, and only one of the eleventh resistor R11 and the twelfth resistor R12 can be selected; the project number resistor branch corresponding to the project number pin BOARD ID6 is connected with a thirteenth resistor R13 or a fourteenth resistor R14, wherein the thirteenth resistor R13 is a pull-up resistor, the fourteenth resistor R14 is a pull-down resistor, and only one of the thirteenth resistor R13 and the fourteenth resistor R14 can be selected; the project number resistor branch corresponding to the project number pin BOARD ID7 is connected with a fifteenth resistor R15 or a sixteenth resistor R16, wherein the fifteenth resistor R15 is a pull-up resistor, the sixteenth resistor R16 is a pull-down resistor, and only one of the fifteenth resistor R15 and the sixteenth resistor R16 can be selected; the unselected resistors are marked by 'CN', which means that no piece is put on, as shown in fig. 3, taking a project number pin Board_ID0 as an example, the corresponding pull-up resistor is a first resistor R1, the pull-down resistor is a second resistor R2, wherein the second resistor R2 is marked by 'CN', namely no piece is put on, and the first resistor R1 is not marked by 'CN', namely the piece is put on, so that the Board_ID0 is a level of 3.3V, namely a high level, and PCH 5 and BMC 6 at the end of a main Board 2 can be marked as '1' after passing through a first interface 3 and a second interface 4; when the first resistor R1 is not in the upper part and the second resistor R2 is in the upper part, the first resistor R1 is expressed as 0; specifically selecting according to the corresponding value of the item number pin in the number truth table; FIG. 6 is a diagram of the corresponding values of the item number pins in the numbering truth table of different items; the item columns represent different items, namely an item A, an item B, an item C, an item D and the like, the different items are set by maintaining a truth table, the pull-up resistance setting of each different independent board card is determined, and the different items are represented by setting a secondary truth table; the truth table corresponding to SKU ID0-2 is the same as the principle of the project number pins Board ID0-7, and the pull-up and pull-down mode is adopted to carry out pull-up of the resistor according to the package requirements of different projects; the truth table corresponding to the BIOS/BMC version pins FW Ver0-2 is the same as the principle of the SKU number pins SKU ID0-2, and is used for distinguishing different BIOS/BMC versions;
each item number pin of the first interface 3 is connected with an item number pull-up resistor or an item number pull-down resistor of a corresponding item number resistor branch, each item number pull-up resistor is connected with a power pin p1 of the first interface 3, and each item number pull-down resistor is grounded;
SKU number pin set A1 of first interface 3 includes three SKU number pins SKU ID0-2;
the SKU number pull-up resistor and pull-down resistor row comprises three SKU number resistor branches connected in parallel, and each SKU number resistor branch is provided with a SKU number pull-up resistor or a SKU number pull-down resistor;
each SKU number pin of the first interface 3 is connected with a SKU number pull-up resistor or a SKU number pull-down resistor of a corresponding SKU number resistor branch, each SKU number pull-up resistor is connected with a power pin p1 of the first interface 3, and each SKU number pull-down resistor is grounded;
the BIOS/BMC version pin group A2 of the first interface 3 comprises three BIOS/BMC version pins FW Ver0-2;
the version number pull-up resistor bank comprises three version number resistor branches connected in parallel, and each version number resistor branch is provided with a version number pull-up resistor or a version number pull-down resistor;
each BIOS/BMC version pin of the first interface 3 is connected with a version number pull-up resistor or a version number pull-down resistor of a corresponding version number resistor branch, each version number pull-up resistor is connected with a power pin p1 of the first interface 3, and each version number pull-down resistor is grounded;
the item number pin group A0 of the first interface 3 is spliced with the item number pin group A0 of the second interface 4;
the SKU number pin group A1 of the first interface 3 is spliced with the SKU number pin group A1 of the second interface 4;
the BIOS/BMC version pin group A2 of the first interface 3 is spliced with the BIOS/BMC version pin group A2 of the second interface 4;
the structures of the first interface 3 and the second interface 4 are shown in fig. 4;
three Reserved pins Reserved0-2 are further arranged on the first interface 3 and the second interface 4, and specific names and functions of the pins are shown in fig. 5.
Example 4:
as shown in fig. 7, the present invention provides a method for adapting to different requirement mainboards through independent boards based on the above embodiment 1, embodiment 2 or embodiment 3, which includes the following steps:
s1, distinguishing each main board project according to project requirements, and establishing a numbering truth table for each main board project;
s2, selecting a pull-up resistor or a pull-down resistor for a resistor branch corresponding to each resistor bank on the independent board according to a numbering truth table of each main board item;
s3, plugging the first interface on the independent board card with the second interface of the main board.
Example 5:
as shown in fig. 8, the present invention provides a method for adapting to different requirements of a motherboard by using an independent board card, which includes the following steps:
s1, distinguishing each main board project according to project requirements, and establishing a numbering truth table for each main board project; the method comprises the following specific steps:
s11, dividing each main board project according to project requirements, generating project numbers according to project differences, generating SKU numbers according to project packages, and generating version numbers according to BIOS/BMC versions;
s12, generating different numbers for the corresponding main board items according to the item numbers, the SKU numbers and the version numbers of the main board items;
s13, converting numbers of all main board items into binary numbers, and generating a number truth table; the binary digits are summed with the number of the project number pins, the SKU number pins and the BIOS/BMC version pins, and each binary digit corresponds to one pin;
s2, selecting a pull-up resistor or a pull-down resistor for a resistor branch corresponding to each resistor bank on the independent board according to a numbering truth table of each main board item; the method comprises the following specific steps:
s21, acquiring the values of each binary system in the numbering truth table and corresponding pins thereof;
s22, positioning a pin;
s23, acquiring a binary value of the positioning pin, and judging whether the binary value of the positioning pin is 1;
if yes, go to step S24;
if not, go to step S25;
s24, setting a resistor branch corresponding to a positioning pin to be connected with a pull-up resistor, setting the pull-up resistor to be connected with a 3.3V bypass power supply of the main board, and entering step S26;
s25, setting a resistor branch corresponding to the positioning pin to be connected with a pull-down resistor, setting the pull-down resistor to be grounded, and entering step S26;
s26, judging whether all pins are positioned;
if yes, enter step S3;
if not, positioning the next pin, and returning to the step S23;
s3, plugging a first interface on the independent board card with a second interface of the main board; the method comprises the following specific steps:
s31, through the plug-in connection of the first interface and the second interface, the plug-in connection of the independent board card and the main board is realized;
s32, powering on a 3.3V bypass power supply of the main board;
s33, the BMC and the PCH acquire the positions of the independent boards through independent board in-position signal pins of the first interface and the second interface, and the distinction of different mainboard projects is realized.
Although the present invention has been described in detail by way of preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Various equivalent modifications and substitutions may be made in the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and it is intended that all such modifications and substitutions be within the scope of the present invention/be within the scope of the present invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A system for adapting to different requirements of a motherboard by means of a separate board, characterized in that it comprises a separate board (1) and a motherboard (2);
the independent board card (1) is provided with a first interface (3);
the main board (2) is provided with a second interface (4), a PCH (5) and a BMC (6);
the first interface (3) can be matched with the second interface (4), and the second interface (4) is connected with the PCH (5) and the BMC (6);
the independent board card (1) is provided with a selection module which is used for distinguishing the main boards with different requirements; the first interface (3) and the second interface (4) are respectively provided with a project number pin group (A0), a SKU number pin group (A1) and a BIOS/BMC version pin group (A2);
the project number pin group (A0) of the second interface (3) is connected with the PCH (5) and the BMC (6) through a project number line row, the SKU number pin group (A1) of the second interface (4) is connected with the PCH (5) and the BMC (6) through a SKU number line row, and the BIOS/BMC version pin group (A2) of the second interface (4) is connected with the PCH (5) and the BMC (6) through a version number group line row;
the selection module comprises a project number pull-up and pull-down resistor bank, a SKU number pull-up and pull-down resistor bank and a version number pull-up and pull-down resistor bank;
the item number pin group (A0) of the first interface (3) is connected with the item number pull-up resistor bank, the SKU number pin group (A1) of the first interface (3) is connected with the SKU number pull-up resistor bank, and the BIOS/BMC version pin group (A2) of the first interface (3) is connected with the version number pull-up resistor bank.
2. The system for adapting to different-demand motherboards through independent boards according to claim 1, wherein the first interface (3) and the second interface (4) are respectively provided with an independent board in-place signal pin (p 2), a power pin (p 1) and a ground pin (p 3);
an independent board card of the second interface (4) is connected with a first end of an on-site pull-up resistor (R100) at an on-site signal pin (P2), the on-site signal pin (P2) is connected with a PCH (5) and a BMC (6), a second end of the on-site pull-up resistor (R100) is connected with a 3.3V bypass power supply (P3V3_STBY) of a main board, an independent board card of the first interface (3) is connected with a first end of an on-site pull-down resistor (R0) at an on-site signal pin (P2), and a second end of the on-site pull-down resistor (R0) is grounded;
the power pin (P1) of the second interface (4) is connected with a 3.3V bypass power supply (P3V3_STBY) of the main board, and the grounding pin (P3) of the second interface (4) is grounded;
the independent board card of the first interface (3) is inserted into the on-site signal pin (p 2) of the second interface (4), the power pin (p 1) of the first interface (3) is inserted into the power pin (p 1) of the second interface (4), and the grounding pin (p 3) of the first interface (3) is inserted into the grounding pin (p 3) of the second interface (4).
3. A system for adapting to different requirements of a motherboard by means of separate boards according to claim 2, characterized in that the set of item number pins (A0) of the first interface (3) comprises a number of item number pins;
the project number pull-up resistor bank comprises a plurality of project number resistor branches connected in parallel, and each project number resistor branch is provided with a project number pull-up resistor or a project number pull-down resistor;
each item number pin of the first interface (3) is connected with an item number pull-up resistor or an item number pull-down resistor of a corresponding item number resistor branch, each item number pull-up resistor is connected with a power pin (p 1) of the first interface (3), and each item number pull-down resistor is grounded;
the SKU number pin group (A1) of the first interface (3) comprises a plurality of SKU number pins;
the SKU number pull-up resistor bank comprises a plurality of SKU number resistor branches connected in parallel, and each SKU number resistor branch is provided with a SKU number pull-up resistor or a SKU number pull-down resistor;
each SKU number pin of the first interface (3) is connected with a SKU number pull-up resistor or a SKU number pull-down resistor of a corresponding SKU number resistor branch, each SKU number pull-up resistor is connected with a power pin (p 1) of the first interface (3), and each SKU number pull-down resistor is grounded;
the BIOS/BMC version pin group (A2) of the first interface (3) comprises a plurality of BIOS/BMC version pins;
the version number pull-up resistor bank comprises a plurality of version number resistor branches connected in parallel, and each version number resistor branch is provided with a version number pull-up resistor or a version number pull-down resistor;
each BIOS/BMC version pin of the first interface (3) is connected with a version number pull-up resistor or a version number pull-down resistor of a corresponding version number resistor branch, each version number pull-up resistor is connected with a power pin (p 1) of the first interface (3), and each version number pull-down resistor is grounded.
4. The system for adapting to different-demand motherboards by means of separate boards according to claim 1, characterized in that the set of item number pins (A0) of the first interface (3) is plugged with the set of item number pins (A0) of the second interface (4);
the SKU serial number pin group (A1) of the first interface (3) is spliced with the SKU serial number pin group (A1) of the second interface (4);
the BIOS/BMC version pin group (A2) of the first interface (3) is spliced with the BIOS/BMC version pin group (A2) of the second interface (4).
5. A method for adapting to different requirements of a motherboard by means of a separate board card according to any of the preceding claims 1-4, characterized by the steps of:
s1, distinguishing each main board project according to project requirements, and establishing a numbering truth table for each main board project;
s2, selecting a pull-up resistor or a pull-down resistor for a resistor branch corresponding to each resistor bank on the independent board according to a numbering truth table of each main board item;
s3, plugging the first interface on the independent board card with the second interface of the main board.
6. The method for adapting to different requirement motherboards through independent boards according to claim 5, wherein step S1 comprises the following specific steps:
s11, dividing each main board project according to project requirements, generating project numbers according to project differences, generating SKU numbers according to project packages, and generating version numbers according to BIOS/BMC versions;
s12, generating different numbers for the corresponding main board items according to the item numbers, the SKU numbers and the version numbers of the main board items;
s13, converting numbers of all main board items into binary numbers, and generating a number truth table.
7. The method of adapting to different requirements of a motherboard by a stand-alone board according to claim 6, wherein the binary digits are summed with the item number pins and SKU number pins and BIOS/BMC version pins, and each binary digits corresponds to one pin.
8. The method for adapting to different requirement motherboards by using independent boards as recited in claim 5, wherein step S2 comprises the following specific steps:
s21, acquiring the values of each binary system in the numbering truth table and corresponding pins thereof;
s22, positioning a pin;
s23, acquiring a binary value of the positioning pin, and judging whether the binary value of the positioning pin is 1;
if yes, go to step S24;
if not, go to step S25;
s24, setting a resistor branch corresponding to a positioning pin to be connected with a pull-up resistor, setting the pull-up resistor to be connected with a 3.3V bypass power supply of the main board, and entering step S26;
s25, setting a resistor branch corresponding to the positioning pin to be connected with a pull-down resistor, setting the pull-down resistor to be grounded, and entering step S26;
s26, judging whether all pins are positioned;
if yes, enter step S3;
if not, the next pin is located, and the process returns to step S23.
9. The method for adapting to different requirement motherboards by using independent boards as recited in claim 5, wherein step S3 comprises the following specific steps:
s31, through the plug-in connection of the first interface and the second interface, the plug-in connection of the independent board card and the main board is realized;
s32, powering on a 3.3V bypass power supply of the main board;
s33, the BMC and the PCH acquire the positions of the independent boards through independent board in-position signal pins of the first interface and the second interface, and the distinction of different mainboard projects is realized.
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