CN210721440U - PCIE card abnormity recovery device, PCIE card and PCIE expansion system - Google Patents
PCIE card abnormity recovery device, PCIE card and PCIE expansion system Download PDFInfo
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- CN210721440U CN210721440U CN201921589547.4U CN201921589547U CN210721440U CN 210721440 U CN210721440 U CN 210721440U CN 201921589547 U CN201921589547 U CN 201921589547U CN 210721440 U CN210721440 U CN 210721440U
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Abstract
The utility model relates to a PCIE card unusual recovery device and PCIE card, PCIE extension system for carry out unusual the recovery to the PCIE card of being connected with system processor, the PCIE card includes interconnect's memory and first treater, first treater pass through the PCIE interface with system processor connects, and wherein the device includes the second treater, the second treater is equipped with first interface, second interface and SMBUS interface, the second treater through first interface with the memory is connected, through the second interface with first treater is connected, through SMBUS interface with system processor connects. The utility model discloses can need not artificial intervention for unusual PCIE card automatic recovery normal work improves the reliability of system.
Description
Technical Field
The utility model relates to a PCIE card control technical field, more specifically relates to a PCIE card unusual recovery unit and PCIE card, PCIE extended system.
Background
A PCIE (peripheral component interconnect express) bus is widely applied to various fields, such as storage and servers, as a high-speed serial computer expansion bus. Various PCIE cards based on a PCIE protocol are applied to a storage device or a server device, and these PCIE cards are connected to a hard disk and a server as a front-end card or a back-end card, and are integrated on a motherboard as an expansion card, or are connected to the motherboard in a form of a plug-in card.
An existing PCIE card generally includes a processor and a Flash memory, where the processor may be an FPGA (Field-Programmable Gate Array), an SOC (System on Chip), an ASIC (Application Specific Integrated Circuit), or the like, and a program of the PCIE card is solidified inside the Flash memory of the PCIE card. In an existing computer system with a PCIE card, when the PCIE card works normally, a Central Processing Unit (CPU) on a motherboard of the computer system may perform operations such as service data interaction and Flash program upgrade on the PCIE card through a PCIE bus interface. However, when the PCIE card is abnormal, for example, the content in the Flash memory is abnormally rewritten, the PCIE program abnormally operates, the PCIE interface timing sequence is abnormal, and the like, the CPU cannot communicate with the PCIE card, and at this time, the computer must be restarted by powering down, and even the PCIE card needs to be taken out from the computer, and the failure recovery is performed manually.
SMBUS (System Management Bus) is an interface in the PCIE protocol, which provides only a physical definition of the interface, but does not specify its purpose. In the existing PCIE card, the SMBUS is generally only used for monitoring parameters such as temperature and voltage, and is not responsible for other operations.
SUMMERY OF THE UTILITY MODEL
The utility model discloses aim at overcoming above-mentioned prior art's at least one kind defect (not enough), provide a PCIE card unusual recovery device and PCIE card, PCIE extended system, can need not artificial intervention for unusual PCIE card automatic recovery normal work improves the reliability of system.
The utility model adopts the technical proposal that:
the utility model provides a PCIE card anomaly recovery device for carry out the anomaly to the PCIE card that is connected with system processor and resume, the PCIE card includes interconnect's memory and first treater, first treater pass through the PCIE interface with system processor connects, including the second treater, the second treater is equipped with first interface, second interface and SMBUS interface, the second treater through first interface with the memory is connected, through the second interface with first treater is connected, through SMBUS interface with system processor connects.
When the PCIE card is abnormal, the system processor cannot perform service data interaction with the first processor through the PCIE interface or upgrade a program stored in the memory. At this moment, the system processor can send the recovery program to the second processor through the SMBUS interface of the second processor, the second processor writes the recovery program into the memory through the first interface of the second processor or replaces an abnormal program in the memory, and then the second processor triggers the first processor to read the recovery program from the memory again through the second interface of the second processor to operate, so that the abnormal recovery of the PCIE card can be automatically completed, manual intervention is not needed, and the reliability of the whole system is effectively improved.
Furthermore, the second processor is also provided with a third interface, and the second processor is connected with the first processor through the third interface.
When the system processor can not communicate with the first processor through the PCIE interface, the second processor reads the state information of the first processor through the third interface of the second processor, and feeds the state information back to the system processor through the SMBUS interface. The system processor can judge the abnormal type of the PCIE card through the received state information of the first processor, and performs corresponding recovery operation by matching with the second processor according to the judgment result.
When the system processor detects that the system processor cannot communicate with the PCIE card through the PCIE interface, the SMBUS interface of the second processor can trigger the second processor to read the state information of the first processor through the third interface.
Furthermore, the PCIE card is further provided with a monitoring module for monitoring operation of the PCIE card and outputting an operation parameter, and the second processor is further connected to the monitoring module through an SMBUS interface.
The monitoring module can monitor the operation conditions of the PCIE card such as the operation temperature, the current or voltage and output corresponding operation parameters, and the second processor can forward the operation parameters output by the monitoring module to the system processor through the SMBUS interface of the second processor, so that the system processor can operate and maintain the PCIE card better.
Further, the first interface is a CFI interface.
Further, the second interface is a CFG interface.
Further, the third interface is an SPI interface.
A PCIE card includes a memory, a first processor, and the PCIE card exception recovery apparatus described above.
A PCIE expansion system includes a system processor and the PCIE card as described above.
Compared with the prior art, the beneficial effects of the utility model are that: through the connection between the second processor and the first processor and between the second processor and the system processor, when the PCIE card is abnormal, the abnormal recovery of the PCIE card can be automatically realized without manual intervention, so that the reliability of the whole system is effectively improved; moreover, the system processor can quickly judge the specific abnormal type of the PCIE card, and favorable information is provided for system operation and maintenance.
Drawings
Fig. 1 is a block diagram of a hardware architecture according to an embodiment of the present invention.
Detailed Description
The drawings of the present invention are for illustration purposes only and are not to be construed as limiting the invention. For a better understanding of the following embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
As shown in fig. 1, the present embodiment provides a PCIE card exception recovery apparatus, configured to perform exception recovery on a PCIE card 10 connected to a system processor 20.
The PCIE card 10 includes a first processor 11 and a memory 12 that are connected to each other, where the memory 12 is used to store a program, and the first processor 11 may read, write, and run the program stored in the memory 12; the first processor 11 is connected to the system processor 20 through a PCIE interface, and the first processor 11 may communicate with the system processor 20 through the PCIE interface.
The PCIE card abnormality recovery device comprises a second processor 13, wherein the second processor 13 is provided with a first interface, a second interface and an SMBUS interface; the second processor 13 is connected to the memory 12 via a first interface, to the first processor 11 via a second interface, and to the system processor 20 via an SMBUS interface.
On the PCIE card 10, the first processor 11 is a master device, and is responsible for main service data processing, and performs service data interaction with the system processor 20 through a PCIE interface, and the first processor 11 may be an FPGA, an SOC, an ASIC, or the like. The memory 12 may be a Flash memory, and stores a program that the first processor 11 needs to run. The first processor 11 may read a program from the memory 12 through a Common Flash Interface (CFI) to operate, and may also upgrade a program stored in the memory 12 through the CFI.
If the present embodiment is applied to a computer system, the system processor 20 is a CPU of the computer system.
Under normal conditions, the system processor 20 may perform service data interaction with the first processor 11 through the PCIE interface, control program upgrade in the memory 12, and the like.
When the PCIE card 10 is abnormal, for example, the program in the memory 12 is abnormally rewritten, or the first processor 11 is abnormal when running the program, or the PCIE interface timing sequence is abnormal, the system processor 20 may not communicate with the PCIE card 10 through the PCIE interface. At this time, the system processor 20 may send the recovery program to the second processor 13 through the SMBUS interface of the second processor 13, the second processor 13 writes the recovery program into the memory 12 through its first interface or replaces the abnormal program in the memory 12, and then the second processor 13 triggers the first processor 11 to read the recovery program from the memory 12 again through its second interface for running, thereby completing the abnormal recovery of the PCIE card 10.
In a specific implementation, the second processor 13 may be an MCU (micro controller Unit).
In a specific implementation process, the second processor 13 may be integrated on the PCIE card 10, or may be disposed outside the PCIE card 10.
Through the arrangement of the second processor 13 and the connection interface thereof, and the combination of the system processor 20, the abnormal recovery of the PCIE card 10 can be automatically realized, manual intervention is not required, and the reliability of the entire system is effectively improved.
In one embodiment, the second processor 13 is further provided with a third interface, through which the second processor 13 is connected with the first processor 11.
When the system processor 20 cannot communicate with the first processor 11 through the PCIE interface, the second processor 13 reads the state information of the first processor 11 through the third interface thereof, such as register information inside the first processor 11, and feeds back the state information to the system processor 20 through the SMBUS interface thereof, and the system processor 20 may determine the specific abnormal condition of the PCIE card 10 according to the state information of the first processor 11 fed back by the second processor 13.
If the second processor 13 can read the state information of the first processor 11 through the third interface thereof, that is, the system processor 20 can receive the state information of the first processor 11 fed back by the second processor 13 through the SMBUS interface of the second processor, the system processor 20 can determine the exception type of the first processor 11 according to the state information fed back by the first processor 11, and can perform an exception recovery operation on the first processor 11 in a targeted manner by cooperating with the second processor 13 according to the exception type, and send a corresponding recovery program to the second processor 13.
If the second processor 13 cannot read the status information of the first processor 11 through the third interface thereof, that is, the system processor 20 cannot receive the status information of the first processor 11 fed back by the second processor 13 through the SMBUS interface of the second processor, the system processor 20 may determine that the first processor 11 is failed as a whole.
Therefore, no matter whether the second processor 13 can read the status information of the first processor 11 through the third interface thereof, the second processor 13 can obtain information beneficial to determining the abnormal type of the PCIE card 10 and feed the information back to the system processor 20.
The second processor 13 may also receive an exception type request sent by the system processor 20 through the SMBUS interface, and trigger reading of the state information of the first processor 11 through the third interface according to the received exception type request.
When the system processor 20 detects that it is unable to communicate with the PCIE card 10 through the PCIE interface, the system processor 13 may send the exception type request to the second processor 13 through the SMBUS interface of the second processor 13, and the second processor 13 reads the state information of the first processor 11 through the third interface according to the received exception type request.
In one embodiment, the first Interface may be a CFI (Common Flash Interface), the second Interface may be a CFG (Configuration Interface), and the third Interface may be an SPI (Serial Peripheral Interface).
In one embodiment, the PCIE card 10 is further provided with a monitoring module 14 for monitoring the operation of the PCIE card 10 and outputting an operation parameter; the second processor 13 is connected to the monitoring module 14 via an SMBUS interface.
The monitoring module 14 may monitor the operation conditions of the PCIE card 10, such as the current or voltage, and output corresponding operation parameters, and the second processor 13 may forward the operation parameters output by the monitoring module 14 to the system processor 20 through the SMBUS interface, so that the system processor 20 can better operate and maintain the PCIE card 10.
In another embodiment, the monitoring module 14 may also be directly connected to the system processor 20 via the SMBUS interface to send the operating parameters to the system processor 20.
The specific implementation process can be as follows: when the system processor detects that the system processor cannot communicate with the PCIE card through the PCIE interface, the system processor sends an abnormal type request to the second processor through an SMBUS interface of the second processor; after receiving the abnormal type request sent by the system processor, the second processor reads the state information of the first processor through a third interface of the second processor, and feeds the state information of the first processor back to the system processor through an SMBUS interface of the second processor; the system processor judges the abnormal condition of the PCIE card according to the state information of the first processor, and sends a recovery program to the second processor through an SMBUS interface of the second processor; after receiving the recovery program sent by the system processor, the second processor writes the recovery program into the memory or replaces an abnormal program in the memory through the first interface of the second processor, and triggers the first processor to read the recovery program from the memory again through the second interface of the second processor for running, so that the abnormal recovery of the PCIE card is completed.
The embodiment also provides a PCIE card, which includes a memory, a first processor, and the PCIE card exception recovery apparatus described above.
The present embodiment further provides a PCIE expansion system, which includes the system processor 20 and the PCIE card described above.
It is obvious that the above embodiments of the present invention are only examples for clearly illustrating the technical solutions of the present invention, and are not limitations to the specific embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims (8)
1. The utility model provides a PCIE card anomaly recovery device for carry out the anomaly to the PCIE card that is connected with system processor and resume, the PCIE card includes interconnect's memory and first treater, first treater pass through the PCIE interface with system processor connects, its characterized in that, including the second treater, the second treater is equipped with first interface, second interface and SMBUS interface, the second treater pass through first interface with the memory is connected, pass through the second interface with first treater is connected, pass through SMBUS interface with system processor connects.
2. The PCIE card abnormality recovery apparatus according to claim 1, wherein the second processor is further provided with a third interface, and the second processor is connected to the first processor through the third interface.
3. The PCIE card abnormality recovery apparatus according to claim 1 or 2, wherein the PCIE card is further provided with a monitoring module for monitoring operation of the PCIE card and outputting an operation parameter, and the second processor is further connected to the monitoring module through an SMBUS interface.
4. The apparatus according to claim 1, wherein the first interface is a CFI interface.
5. The apparatus according to claim 1, wherein the second interface is a CFG interface.
6. The PCIE card abnormality recovery apparatus according to claim 2, wherein the third interface is an SPI interface.
7. A PCIE card comprising a memory and a first processor connected to each other, and further comprising the PCIE card abnormality recovery apparatus according to any one of claims 1 to 6.
8. A PCIE expansion system comprising a system processor and the PCIE card of claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921589547.4U CN210721440U (en) | 2019-09-23 | 2019-09-23 | PCIE card abnormity recovery device, PCIE card and PCIE expansion system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921589547.4U CN210721440U (en) | 2019-09-23 | 2019-09-23 | PCIE card abnormity recovery device, PCIE card and PCIE expansion system |
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| CN210721440U true CN210721440U (en) | 2020-06-09 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110825547A (en) * | 2019-09-23 | 2020-02-21 | 京信通信系统（中国）有限公司 | SMBUS-based PCIE card exception recovery device and method |
| CN114995860A (en) * | 2022-08-01 | 2022-09-02 | 摩尔线程智能科技(北京)有限责任公司 | Method for upgrading firmware of graphic processor and graphic processor |
-
2019
- 2019-09-23 CN CN201921589547.4U patent/CN210721440U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110825547A (en) * | 2019-09-23 | 2020-02-21 | 京信通信系统（中国）有限公司 | SMBUS-based PCIE card exception recovery device and method |
| CN110825547B (en) * | 2019-09-23 | 2024-04-12 | 京信网络系统股份有限公司 | PCIE card exception recovery device and method based on SMBUS |
| CN114995860A (en) * | 2022-08-01 | 2022-09-02 | 摩尔线程智能科技(北京)有限责任公司 | Method for upgrading firmware of graphic processor and graphic processor |
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Address after: 510663 Shenzhou Road, Guangzhou Science City, Guangzhou economic and Technological Development Zone, Guangdong, 10 Patentee after: Jingxin Network System Co.,Ltd. Address before: 510663 Shenzhou Road, Guangzhou Science City, Guangzhou economic and Technological Development Zone, Guangdong, 10 Patentee before: Comba Telecom System (China) Ltd. |
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| CP01 | Change in the name or title of a patent holder |