CN114995860A - Method for upgrading firmware of graphic processor and graphic processor - Google Patents
Method for upgrading firmware of graphic processor and graphic processor Download PDFInfo
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- CN114995860A CN114995860A CN202210914402.7A CN202210914402A CN114995860A CN 114995860 A CN114995860 A CN 114995860A CN 202210914402 A CN202210914402 A CN 202210914402A CN 114995860 A CN114995860 A CN 114995860A
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Abstract
The invention discloses a method for upgrading firmware of a graphic processor and the graphic processor, which can be applied to the technical field of data communication. The method comprises the following steps: receiving an upgrade request command from a processor through a system management bus; receiving firmware to be upgraded through the system management bus; and upgrading the firmware of the graphic processor based on the firmware to be upgraded. The firmware of the GPU is upgraded through the SMBus, so that when the PCIe bus is abnormal or fails due to abnormality or failure of the GPU board card and communication can not be carried out through the PCIe bus, the abnormality of the GPU board card is repaired on line.
Description
Technical Field
The present invention relates to the field of data communication technologies, and in particular, to a system and a method for upgrading firmware of a graphics processor.
Background
Currently, communication between a Graphics Processing Unit (GPU) card and a motherboard is performed through a Peripheral Component interface express (PCIe) bus. If the PCIe bus fails and the communication through the PCIe bus cannot be performed due to the abnormality of the GPU card, the abnormality of the GPU card cannot be repaired on line.
This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
Disclosure of Invention
The embodiment of the invention provides a method for upgrading firmware of a Graphics Processing Unit (GPU), which upgrades the firmware of the GPU through a System Management Bus (SMBus), thereby realizing online repair of the abnormity of a GPU board card. The method comprises the following steps:
receiving an upgrade request command from a processor through a system management bus;
receiving firmware to be upgraded through the system management bus;
and upgrading the firmware of the graphic processor based on the firmware to be upgraded.
The embodiment of the invention also provides a method for upgrading the firmware of the graphic processor, which is used for realizing the online repair of the abnormity of the GPU card. The method comprises the following steps:
generating an upgrade request command;
and sending the upgrading request command to a graphic processor through a system management bus.
The embodiment of the invention also provides a graphics processor, which is used for realizing online repairing of the abnormity of the GPU card. The graphics processor has:
the system management bus slave interface is in communication connection with the system management bus master interface of the processor;
a receiving unit that receives an upgrade request command from the processor through the system management bus from an interface;
the receiving unit also receives firmware to be upgraded from the processor from an interface through the system management bus.
The embodiment of the invention also provides a processor which is used for realizing online repairing of the abnormity of the GPU card. The processor has:
the system management bus master interface is in communication connection with a system management bus slave interface of the graphics processor;
a command generating unit that generates an upgrade request command;
a transmitting unit which transmits the upgrade request command to a graphic processor through the system management bus master interface.
An embodiment of the present invention further provides a computer device, which includes a memory, a graphics processor or a processor, and a computer program stored on the memory and executable on the graphics processor or the processor, and when the graphics processor or the processor executes the computer program, the method is implemented.
An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the above method.
An embodiment of the present invention further provides a computer program product, where the computer program product includes a computer program, and when the computer program is executed by a processor, the computer program implements the foregoing method
In the embodiment of the invention, the firmware of the GPU is upgraded through the system management bus, so that when the PCIe bus is abnormal or fails due to the abnormality or the failure of the GPU card and the communication can not be realized through the PCIe bus, the abnormality of the GPU card is repaired on line.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts. In the drawings:
FIG. 1 is a diagram illustrating a method for upgrading firmware of a graphics processor according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a predefined command frame format of an embodiment of the present invention.
Fig. 3 is a schematic diagram of a predefined message frame format according to an embodiment of the present invention.
FIG. 4 is another diagram of a method for firmware upgrade of a graphics processor according to an embodiment of the present invention.
FIG. 5 is a flowchart illustrating a method for firmware upgrade of a graphics processor according to an embodiment of the present invention.
FIG. 6 is a further schematic diagram of a method of firmware upgrade of a graphics processor according to an embodiment of the present invention.
FIG. 7 is a further schematic diagram of a method for firmware upgrade of a graphics processor according to an embodiment of the present invention.
FIG. 8 is a further schematic diagram of a method of firmware upgrade of a graphics processor according to an embodiment of the present invention.
FIG. 9 is a schematic diagram of a system for graphics processor firmware upgrade, according to an embodiment of the present invention.
FIG. 10 is another schematic diagram of a system for graphics processor firmware upgrade, according to an embodiment of the present invention.
FIG. 11 is a diagram of a graphics processor, according to an embodiment of the present invention.
FIG. 12 is a schematic diagram of a processor of an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
The embodiment of the invention provides a method for upgrading firmware of a graphic processor. FIG. 1 is a schematic diagram of a method of an embodiment of the invention.
As shown in fig. 1, the method 100 may include:
step 101: the processor 1 generates an upgrade request command;
step 102: the processor 1 transmits the update request command to the graphics processor 2 via a System Management Bus (SMBus, hereinafter sometimes referred to as "SMBus Bus");
step 103: the graphics processor 2 receives the upgrade request command through the SMBus;
therefore, firmware of the GPU can be upgraded through the SMBus bus, and therefore when the PCIe bus is abnormal or fails due to abnormality or failure of the GPU board card and communication cannot be achieved through the PCIe bus, abnormality of the GPU board card can be repaired on line.
In step 101, the processor 1 may generate an upgrade request command according to a predefined command frame format, where the predefined command frame format includes a command header and may further include at least one of a custom command field, a sub-command field, a data length field, and a first data field.
Fig. 2 is a schematic diagram of a predefined command frame format of an embodiment of the present invention.
As shown in fig. 2, a frame format defined by an Intelligent Platform Management Interface (IPMI) protocol may include a network function field, a request/response identifier field, a request program ID field, a response program ID field, a command field, and a data field. In addition, the frame format defined by the IPMI protocol may further include other fields, specifically, which fields may be selected according to different data formats, which is not limited in this embodiment of the present invention.
The command header in the command frame format according to the embodiment of the present invention is compatible with the command header defined by the IPMI protocol, that is, the command header in the command frame format according to the embodiment of the present invention may also include at least one of a network function field, a request/response identifier field, a request procedure ID field, and a response procedure ID field. In addition, the customized frame format in the embodiment of the present invention may further include other fields defined by the IPMI protocol, specifically which fields are included may be selected according to different data formats, which is not limited in the embodiment of the present invention.
In addition, in the portion corresponding to the command field and the data field of the frame format of the IPMI protocol, the embodiment of the present invention is customized, that is, the command frame in the embodiment of the present invention may further include at least one of a customized command field, a sub-command field, a data length field, and a first data field. Wherein the custom command field indicates that the command is a custom command, which may be a vendor custom command, for example, to distinguish from a standard command of the IPMI protocol; the sub-command field indicates the category of the command; the first data field indicates the type of data carried by the command; the data length field indicates the length of the corresponding data indicated in the first data field.
For example, table 1 lists the data format of some fields of a predefined command frame of an embodiment of the present invention.
Table 1:
in table 1, the network function field may select data that does not conflict with the standard command of the IPMI protocol, for example, a pair of data of 0x30-0x3F for the request command and the reply message, for example, an even number in the request command and an odd number of the next bit of the even number in the reply message. However, the present invention is not limited to this, and an odd number may be selected in the request command, an even number preceding or following the odd number may be selected in the reply message, and the like. The following description will take an example in which the network function field selects "0 x 3E" for the request command.
The custom command field is illustrated as "0 xF0," but the embodiments of the present invention are not limited thereto, and other data that does not conflict with the standard command of the IPMI protocol may be selected.
Further, on the graphics processor 2 side, for example, it is possible to distinguish whether the received command is a standard command of the IPMI protocol or a non-standard command, i.e., a custom command, according to the network function field. The received command may be distinguished as a standard command of the IPMI protocol or a non-standard command according to the custom command field, and at least one of the network function field and the custom command field may be included in one command frame.
The data length field indicates the length of data carried by the command or the length of data corresponding to the type of data carried by the command, and maximum supports 4 gbytes and minimum 16 bytes, but the embodiment of the present invention is not limited thereto, and the data length may also be greater than 4 bytes, so that a larger length of data may be supported.
The first data field, i.e. the data 1 field, indicates the type of data carried by the command or the type of data carried by the command, for example, the data itself to be transmitted may be directly carried by the command, or the type corresponding to the data to be transmitted may be indicated by the command, for example, the type of firmware to be upgraded may be indicated by the data 1 field.
For example, Table 2 lists one format of an upgrade request command as defined by the predefined command frame format in Table 1:
table 2:
in table 2, as the command frame, the network function field selects 0x 3E. However, the present invention is not limited to this, and other data may be selected.
Further, fields such as the request/response identifier, the requester ID, and the response ID may be customized or determined according to the IPMI protocol standard.
Data 1, i.e., the first data, may include 3 types, i.e., the firmware type may be GPU RTOS, VBIOS, or Bootloader. However, the embodiment of the present invention is not limited thereto, and the data 1 may also be defined according to other firmware of the GPU. In addition, the data of the firmware to be upgraded can be directly carried by the data 1. Reference may be made to related technologies, which are not described herein in detail.
In at least one embodiment, as shown in fig. 1, the method 100 may further comprise:
step 104: the graphics processor 2 generates an upgrade confirm message,
step 105: the graphics processor 2 sends the upgrade confirm message to the processor through the SMBus.
In step 104, the graphics processor 2 may generate an upgrade confirm message in accordance with a predefined message frame format, where the predefined message frame format includes a command header and may further include at least one of a custom command field, a completion code field, and a second data field.
Fig. 3 is a schematic diagram of a predefined message frame format according to an embodiment of the present invention.
As shown in fig. 3, the predefined message frame of the embodiment of the present invention can also be compatible with the frame format defined by the IPMI protocol, wherein the command header portion may include at least one of a network function field, a request/response identifier field, a requester ID field, and a responder ID field. In addition, the customized frame format according to the embodiment of the present invention may further include other fields defined by the IPMI protocol, and specifically, which fields may be selected according to different data formats.
In addition, the functions of the fields included in the command header of the predefined message frame in the embodiment of the present invention are the same as the functions of the fields included in the command header of the predefined command frame, and the same contents are incorporated herein, which is not described herein again.
In addition, in the parts corresponding to the command field and the data field of the frame format of the IPMI protocol, the embodiment of the present invention is customized, that is, the message frame of the embodiment of the present invention may further include at least one of a customized command field, a completion code field, and a second data field. The self-defined command field indicates that the command is a self-defined command, the completion code field indicates the completion state of the command, and the second data field indicates data carried by the command.
For example, table 3 lists the data format of some fields of a predefined message frame of an embodiment of the present invention.
Table 3:
in table 3, the network function field corresponds to the network function field in table 1, and a pair of data in 0x30-0x3F may be selected, for example, corresponding to the network field "0 x 3E" in table 2, and "0 x 3F" may be selected in the reply message. The present invention is not limited thereto and other data may be used.
Furthermore, data 2, i.e. the second data field, is the data carried by the command, in an embodiment of the present invention, if the message does not carry data, this field may not be constructed when constructing the reply message, i.e. it may be in a "default" state.
Table 4 lists one format of the upgrade confirm message as defined by the predefined message frame format in table 3.
Table 4:
in table 4, a completion code "0 x 00" for example indicates "upgrade request command is received and upgrade conditions are currently met" or "upgrade request command is received and preparation for receiving upgrade firmware data is made", and a completion code "0 x 01" for example indicates "upgrade conditions are not currently met".
In addition, the meaning of each data representation of the completion code may also be defined according to the actual situation, and the embodiment of the present invention is not limited thereto. In addition, regardless of the meaning of the completion code, if the completion code is received on the processor side, it means that the graphics processor side has received the upgrade request command sent from the processor.
Further, fields such as the request/response identifier, the requester ID, and the response ID may be customized or determined according to the IPMI protocol standard.
In at least one embodiment, as shown in fig. 1, the method 100 may further comprise:
step 106: the processor 1 receives the upgrade confirm message;
step 107: the processor 1 sends the firmware to be upgraded to the graphics processor 2 through the SMBus;
step 108: the graphics processor 2 receives the firmware to be upgraded;
step 109: the graphics processor 2 performs a firmware upgrade operation,
step 110: after the upgrade is successful, the graphics processor 2 generates an upgrade success message according to a predefined message frame format;
step 111: the graphics processor 2 sends an upgrade success message to the processor 1 through the SMBus.
In step 107, the processor 1 sends the firmware of the firmware type corresponding to the first data field in the upgrade request command, i.e., GPU RTOS, VBIOS, or Bootloader, to the graphics processor 2. Further, in the case where the processor 1 directly transmits the firmware data to be upgraded to the graphic processor 2 through the upgrade request command, step 107 may be omitted. In addition, the firmware data to be upgraded may be transmitted or received in the form of an upgrade package, for example, or may be transmitted or received in other forms, and embodiments of the present invention are not limited thereto,
in step 109, the graphics processor 2 parses the received firmware and writes the firmware into a predetermined area, for example, the system management unit of the graphics processor 2 parses the received firmware, and acquires a Unique communication Identifier (UUID), a signature, image content of the firmware to be upgraded, and a type of the firmware to be upgraded; the signature is checked according to preset signature checking algorithms such as an asymmetric encryption algorithm RSA or SM2, and therefore the integrity of the mirror image is guaranteed; after the signature verification is successful, a written region of the mirror image content to be upgraded is searched in the storage medium according to the UUID and the type of the firmware to be upgraded, the mirror image content to be upgraded is written in the region, for example, a main partition of information such as a mirror image writing address is searched in a partition table of the storage medium according to the UUID and the type of the firmware to be upgraded, the mirror image content to be upgraded is written in an address corresponding to the partition table of the main partition, and the main partition table is updated. The storage medium is, for example, SPI nor flash, EMMC, or the like.
In at least one embodiment, the above description is given by taking the step 109 after the steps 101 to 108 as an example, but the embodiment of the present invention is not limited thereto. In step 102, the processor 1 may directly transmit the firmware data to be upgraded to the graphic processor 2 through the upgrade request command, in which case step 109 may be performed after step 103. That is, in the case where the processor directly transmits the firmware data to be upgraded to the graphic processor 2 through the upgrade request command, the graphic processor 2 may directly perform the firmware upgrade according to the received firmware data to be upgraded, may not reply the upgrade confirmation message through the steps 104 and 105, or may not perform the upgrade after waiting for the processor 1 to transmit the upgrade command. In addition, the graphic processor 2 may also wait for the processor 1 to issue an upgrade command after receiving the firmware data to be upgraded, and then execute the upgrade after receiving the upgrade command. The embodiment of the invention does not limit the trigger condition for the graphics processor 2 to execute the firmware upgrade, and can be set according to actual requirements.
In step 110, the upgrade success message may be defined according to a predefined message frame format in table 3, for example, table 5 lists one format of the upgrade success message defined according to the predefined message frame format in table 3.
Table 5:
before step 110, the step of the graphics processor 2 checking whether the upgrade is successful may also be included, and in case the upgrade is successful, step 110 is entered, and in case the upgrade fails, step 110A is entered: the graphic processor 2 generates an upgrade failure message according to a predefined message frame format, for example, when the upgrade fails due to a tag failure, "0 x 01" is written in the completion code field of the upgrade failure message, and when the upgrade fails due to a flash refresh failure, "0 x 02" is written in the completion code field of the upgrade failure message; then step 111A is entered: the graphics processor 2 sends an upgrade failure message to the processor 1 through the SMBus.
As shown in fig. 1, the method 100 may further include:
step 112: the processor 1 generates an upgrade state request command according to a predefined command frame format;
step 113: the processor 1 sends an upgrade status request command to the graphics processor 2 through the SMBus.
In step 112, the upgrade status request may be defined according to the predefined command frame format in table 1, for example, table 6 lists one format of the upgrade status request command defined according to the predefined command frame format in table 1:
table 6:
in step 113, the processor 1 may send an upgrade status request command to the graphics processor 2 every predetermined time after the firmware to be upgraded is sent, for example, send the upgrade status request command every 2s or 3s to query the upgrade result; when the reply message of the graphic processor 2 is not received within a preset time, for example, 2 minutes, the upgrade is judged to fail, and the upgrade is ended; in addition, if the processor 1 receives the upgrade status confirmation message replied from the graphic processor 2 within a predetermined time, it inquires whether the replied message is an upgrade success message or an upgrade failure message according to table 3, and then ends the upgrade.
FIG. 4 is another schematic of a method of an embodiment of the invention.
As shown in fig. 4, the method 400 may further include:
step 401: the processor detects whether a PCIe bus communicated with the graphics processor is abnormal or not, and enters a step 403 when the PCIe bus is abnormal, and enters a step 405 when the PCIe bus is normal;
step 403: the processor communicates with the graphics processor through the SMBus, and, for example, an upgrade request command may be sent to the graphics processor through the SMBus.
Step 405: the processor ends the detection.
Thus, the processor and the graphics processor may communicate through the SMBus when an exception or failure occurs in the PCIe bus.
In this embodiment of the present invention, the processor 1 may be a Central Processing Unit (CPU), a Baseboard Management Controller (BMC), or other processors or controllers with similar functions, which is not limited in this embodiment of the present invention.
FIG. 5 is a flowchart illustrating a method for firmware upgrade of a graphics processor according to an embodiment of the present invention. The following describes a process of upgrading GPU firmware according to an embodiment of the present invention by taking fig. 5 as an example.
As shown in fig. 5, flow 500 includes a master processor side flow 5100 and a slave processor side flow 5200, where the master processor may be processor 1 as described above and the slave processor may be graphics processor 2 as described above.
As shown in fig. 5, the host processor-side flow 5100 may include:
operation 5101: initializing a main processor side program;
operation 5102: constructing an upgrading request command according to a predefined command frame format;
operation 5103: sending the constructed upgrading request command;
operation 5104: waiting for receiving an upgrade confirm message from the slave processor side;
operation 5105: judging whether an upgrade confirmation message is received, entering operation 5106 under the condition of receiving the upgrade confirmation message, and continuing to wait under the condition of not receiving the upgrade confirmation message;
operation 5106: sending the firmware to be upgraded;
operation 5107: constructing an upgrade state request command according to a predefined command frame format;
operation 5108: sending the constructed upgrading state request command;
operation 5109: waiting to receive an upgrade status confirmation message from the slave processor;
operation 5110: judging whether an upgrade status confirmation message is received, and entering operation 5112 if the upgrade status confirmation message is received, and entering operation 5111 if the upgrade status confirmation message is not received;
operation 5111: judging whether the distance sending upgrading state request command exceeds the preset time or not, if so, entering operation 5113, and if not, continuing to wait;
operation 5112: analyzing the received upgrade status confirmation message;
operation 5113: and finishing upgrading.
In operation 5101, initializing a program of the host processor side may include: the storage area initialization, the parameter initialization, and the like may refer to related technologies, which is not limited in this embodiment of the present invention.
In operation 5102, the host processor may construct an upgrade request command in the data format of the fields of table 1.
In operation 5103, the master processor may send a constructed upgrade request command to the slave processor over the SMBus channel. In addition, under the condition that the PCIe bus is normal, the main processor can also send an upgrade request command to the slave processor through the PCIe channel.
In operation 5104, the channel receiving the message corresponds to that in operation 5103, that is, if the upgrade request command is sent through the SMBus bus in operation 5103, the upgrade confirm message is received through the SMBus interface in operation 5104, and if the upgrade request command is sent through the PCIe bus in operation 5103, the upgrade confirm message is received through the PCIe interface in operation 5104.
In operation 5105, in the event that the upgrade confirm message is not received, it continues to wait for the upgrade confirm message to be received. In addition, a waiting time may also be set, and if the upgrade confirmation message is not received within a predetermined time, it may be determined that the current communication channel is not clear, and an operation of ending the upgrade is performed, where the predetermined time may be, for example, 30s, 1 minute, and the like, and this is not limited in the embodiment of the present invention.
In operation 5106, the firmware to be upgraded is sent to the slave processor over the SMBus bus. The firmware type to be upgraded is, for example, GPU RTOS, VBIOS, or Bootloader, and the format of the firmware may be formed in the form of UUID + signature + image file. However, the embodiment of the present invention is not limited to this, the firmware to be upgraded may also be of other types, and the format of the firmware may also be configured in other forms, which may specifically refer to the related prior art.
In operation 5107, the master processor may construct an upgrade status request command in the data format of the fields of table 1 to inquire whether the upgrade of the slave processors is completed.
In operation 5108, the master processor may send a constructed upgrade status request command to the slave processor over the SMBus channel. In addition, under the condition that the PCIe bus is normal, the main processor can also send an upgrade state request command to the auxiliary processor through the PCIe channel.
In operation 5109, the channel on which the message is received corresponds to operation 5108, that is, if the upgrade status request command is sent through the SMBus bus in operation 5108, the upgrade status confirm message is received through the SMBus interface in operation 5104, and if the upgrade status confirm command is sent through the PCIe bus in operation 5103, the upgrade status confirm message is received through the PCIe interface in operation 5104.
In operation 5110, in case that the upgrade status confirmation message is not received, it continues to wait for the reception of the upgrade status confirmation message. In addition, after the firmware to be upgraded is sent, the upgrade status request command may also be sent to the slave processor at intervals of a predetermined query time to query the upgrade result, where the predetermined query time may be, for example, 2s or 3s, or other times, which is not limited in this embodiment of the present invention.
In operation 5111, a timeout mechanism is set to query the upgrade result, that is, if the upgrade status confirmation message is not received within a predetermined waiting time, it may be determined that the upgrade fails, and an operation of ending the upgrade is performed, where the predetermined waiting time may be, for example, 1 minute or 2 minutes, or other times, which is not limited in this embodiment of the present invention.
In operation 5112, the main processor may parse the upgrade status confirmation message according to table 3, find a completion code, and confirm the upgrade result, i.e., confirm whether the upgrade status confirmation message is an "upgrade success message" or an "upgrade failure message".
As shown in fig. 5, slave processor side flow 5200 includes:
operation 5201: initializing a slave processor side program;
operation 5202: waiting for receiving an upgrade request command from a main processor side;
operation 5203: judging whether an upgrade request command is received, if so, entering operation 5206, and if not, entering operation 5204;
operation 5204: judging whether other commands are received, if so, entering operation 5205, and if not, continuing to wait for the upgrade request command;
operation 5205: executing other commands;
operation 5206: analyzing the upgrading request command;
operation 5207: constructing upgrade acknowledgements in accordance with a predefined message frame format
Operation 5208: sending the constructed upgrade confirmation message;
operation 5209: receiving firmware data to be upgraded;
operation 5210: analyzing the received firmware data, and acquiring a signature value, mirror image content, UUID and the type of the upgraded firmware;
operation 5211: signature verification is carried out according to RSA or SM2 algorithm;
operation 5212: judging whether the signature verification is successful, if so, entering operation 5213, and if not, entering operation 5217;
operation 5213: searching a main partition of information such as mirror image content write-in addresses and the like in a partition table of a storage medium FLASH according to the analyzed UUID;
operation 5214: writing the mirror image content into an address corresponding to a partition table of the main partition according to the inquired information, and updating the main partition table;
operation 5215: determining whether the upgrade operation was successful, if so, entering operation 5218, and if not, entering operation 5216;
operation 5216: starting an upgrade failure recovery mechanism, finding out a backup partition mirror image through a FLASH partition table, writing back the backup partition mirror image to a main partition, and replying failure command data;
operation 5217: constructing an upgrade failure message according to a predefined message frame format;
operation 5218: constructing an upgrade success message according to a predefined message frame format;
operation 5219: receiving an upgrade status request command;
operation 5220: reply to an upgrade status request message, i.e., reply to the "upgrade success message" generated in operation 5218 or reply to the "upgrade failure message" generated in operation 5217;
operation 5221: and (5) finishing upgrading.
In operation 5201, initializing the program from the slave side may include: for storage area initialization, parameter initialization, and the like, reference may be made to related technologies, which is not limited in this embodiment of the present invention.
In operation 5202, an upgrade request command is received from the processor over the SMBus channel.
In operations 5203 and 5204, if a command is received from the SMBus channel, it is parsed whether the command is an upgrade request command, and if not, corresponding command processing is performed; if it is an upgrade request command, operation 5206 is entered.
In operation 5206, the slave processor may parse the upgrade request command according to table 1 to obtain the data length and firmware type of the firmware to be upgraded, ready to receive the storage area of the firmware.
In operation 5207, the slave processor may construct an upgrade confirm message in the data format of the fields of Table 3.
In operation 5208, the slave processor may send a constructed upgrade confirm message to the master processor over the SMBus channel. In addition, under the condition that the PCIe bus is normal, the slave processor can also send an upgrade confirmation message to the master processor through the PCIe channel.
In operation 5209, the channel of receiving the firmware corresponds to that in operation 5208, i.e., if the upgrade confirm message is sent through the SMBus bus in operation 5208, the firmware to be upgraded is received through the SMBus interface in operation 5209, and if the upgrade confirm message is sent through the PCIe bus in operation 5208, the firmware to be upgraded is received through the PCIe interface in operation 5209.
In operation 5210, the received firmware data to be upgraded may be parsed according to the prior art, which is not limited by the embodiment of the present invention.
In operation 5211, signature verification may be performed by the asymmetric cryptographic algorithm RSA or SM2 so that the integrity of the image may be guaranteed. However, the embodiment of the present invention is not limited thereto, and the signature verification may also be performed according to other algorithms, which may specifically refer to the prior art.
In operations 5213 to 5215, the firmware upgrade method is described by taking the example of writing the image content into the address of the queried main partition as an example, but the embodiment of the present invention is not limited thereto, and the firmware may also be upgraded according to other methods, which may specifically refer to the prior art, and the embodiment of the present invention is not limited thereto.
In operation 5216, the upgrade failure recovery mechanism is described by taking the mirror write of the backup partition to the main partition as an example, but the embodiment of the present invention is not limited thereto, and the upgrade failure recovery mechanism may also be executed according to other methods, which may specifically refer to the prior art, and the embodiment of the present invention is not limited thereto.
In operation 5217 and operation 5218, the slave processor may construct an upgrade failure message and an upgrade success message in the data format of the fields of table 3.
In operations 5219 and 5220, an upgrade status request message is replied after receiving the upgrade status request command, i.e., an "upgrade success message" indicating that the upgrade was successful or an "upgrade failure message" indicating that the upgrade failed. However, the embodiment of the present invention is not limited to this, and the slave processor may also actively send a corresponding upgrade status message to the master processor after determining that the upgrade is successful or failed, and does not need to reply after receiving the upgrade status request command.
The embodiment of the invention also provides a method for upgrading the firmware of the graphic processor, which can be applied to the Graphic Processor (GPU). Fig. 6 is a schematic diagram of the method.
As shown in fig. 6, method 600 may include:
step 601: receiving an upgrade request command from a processor through the SMBus;
step 602: receiving firmware to be upgraded through an SMBus;
step 603: and upgrading the firmware of the graphic processor based on the firmware to be upgraded.
FIG. 7 is a further schematic diagram of a method of firmware upgrade of a graphics processor according to an embodiment of the present invention.
In at least one embodiment, as shown in fig. 7, method 700 may include:
step 701: generating an upgrade confirm message;
step 703: and sending the upgrading confirmation message to the processor through the SMBus.
Further, as shown in fig. 7, the method 700 may further include:
step 705: receiving firmware to be upgraded sent by a processor through an SMBus;
step 707: generating an upgrade status confirmation message according to a predefined message frame format;
step 709: and sending the upgrading state confirmation message to the processor through the SMBus.
Since the related steps have been described in detail in the above method 100 and flowchart 500, the same contents are incorporated herein and will not be described again.
The embodiment of the invention also provides a method for upgrading the firmware of the graphic processor, which can be applied to a Central Processing Unit (CPU) or a Baseboard Management Controller (BMC). Fig. 8 is a schematic diagram of the method.
As shown in fig. 8, method 800 may include:
step 801: an upgrade request command generated according to a predefined command frame format;
step 802: and sending the upgrading request command to a graphics processor through the SMBus.
Further, as shown in fig. 8, the method 800 may further include:
step 803: receiving an upgrade confirm message from the graphics processor through the SMBus;
step 804: sending firmware to be upgraded through the SMBus;
step 805: an upgrade status request command generated according to a predefined command frame format;
step 806: an upgrade status request command is sent through the SMBus.
Since the related steps have been described in detail in the above method 100 and flowchart 500, the same contents are incorporated herein and will not be described again.
The embodiment of the invention also provides a system for upgrading the firmware of the graphic processor. FIG. 9 is a schematic diagram of a system for graphics processor firmware upgrade, according to an embodiment of the present invention.
As shown in fig. 9, system 900 may include a graphics processor 910 and a processor 920, graphics processor 901 having an SMBus Slave interface (SMBus Slave) 911, processor 902 being, for example, a CPU or BMC, processor 902 having an SMBus Master interface (SMBus Master) 921, the SMBus Master interface 921 of the processor being communicatively connected to the SMBus Slave interface 911 of the graphics processor 901, for example, communicating via an SMBus bus.
The processor 920 generates an upgrade request command in a predefined command frame format, transmits the upgrade request command to the graphic processor 910 through the SMBus master interface 921, and the graphic processor 910 receives the upgrade request command through the SMBus slave interface.
The operation principle of the graphics processor 910 in the embodiment of the present invention is the same as the operation principle of the graphics processor 2 in the method 100, and the operation principle of the processor 920 in the embodiment of the present invention is the same as the operation principle of the processor 1 in the method 100, and the contents thereof are incorporated herein, and are not described again here.
Furthermore, as shown in fig. 9, the graphics processor 910 may further have a PCIe bus interface 912, the processor 920 may further have a PCIe bus interface 922, and the PCIe bus interface 912 of the graphics processor 910 is communicatively connected to the PCIe bus interface 922 of the processor 920. The processor 920 may detect whether a PCIe bus communicating with the graphics processor 910 is abnormal, and when detecting the PCIe bus abnormality, the processor 920 communicates with the graphics processor 910 through the SMBus bus, for example, when detecting the PCIe bus abnormality, the processor 920 sends an upgrade request command to the graphics processor 910 through the SMBus bus. Therefore, the firmware of the GPU is upgraded through the SMBus bus, and therefore when the PCIe bus is abnormal or fails due to abnormality or failure of the GPU board card and communication cannot be achieved through the PCIe bus, the abnormality of the GPU board card is repaired on line.
In addition, when the PCIe bus is normal, the processor 920 may also send an upgrade request command to the graphics processor 910 through the SMBus bus, and upgrade the firmware of the GPU through the SMBus bus.
In addition, when the PCIe bus is normal, the processor 920 may also upgrade the firmware of the GPU through the PCIe bus.
FIG. 10 is another schematic diagram of a system for graphics processor firmware upgrade, according to an embodiment of the present invention.
As shown in fig. 10, in the GPU board, the PCIe interface and the SMBus slave interface may be integrated into a standard PCIe interface, so that the SMBus slave interface of the GPU board may be physically connected to the SMBus master interface of the CPU or BMC by inserting the GPU board into a PCIe slot of the CPU or BMC. In addition, inside the GPU board card, the GPU system management unit can be in communication connection with the SMBus slave interface, so that the GPU system management unit can be communicated with a CPU or a BMC through an SMBus bus.
In addition, the CPU or BMC in fig. 10 may be a CPU motherboard or a server motherboard with an SMBus interface and a PCIe interface, or may be a motherboard with a standard PCIe slot, which is not limited in this embodiment of the present invention.
Fig. 11 is a schematic diagram of a graphics processor according to an embodiment of the present invention.
As shown in fig. 11, the graphics processor 1000 includes an SMBus Slave interface (SMBus Slave) 1001, a receiving unit 1002, a message generating unit 1003, and a transmitting unit 1004. Wherein the SMBus slave interface 1001 is communicably connected to the SMBus master interface of the processor; the receiving unit 1002 receives an upgrade request command from the processor from the interface 1001 through the SMBus; the message generating unit 1003 generates an upgrade confirm message according to a predefined message frame format; the transmission unit 1004 transmits an upgrade confirmation message to the processor from the interface 1001 through the SMBus.
The operation principle of the graphic processor 1000 according to the embodiment of the present invention is the same as the operation principle of the graphic processor 2 in the method 100, and the contents thereof are incorporated herein and will not be described again.
Further, as shown in fig. 11, the graphics processor 1000 may further include a PCIe interface 1005, and the graphics processor 1000 may communicate with the processor through the PCIe bus through the PCIe interface 1005. Further, graphics processor 1000 may choose to communicate with the processor from interface 1001 through the SMBus when the PCIe bus is abnormal.
In addition, the graphics processor 1000 may further include a unit not shown in fig. 11, for example, a storage unit, and the embodiment of the present invention does not limit which units are specifically included in the graphics processor 1000, and may be configured according to an actual situation.
Fig. 12 is a schematic diagram of a processor according to an embodiment of the present invention.
As shown in fig. 12, the processor 1100 has an SMBus main interface (SMBus Master) 1101, a sending unit 1102, and a command generating unit 1103, the SMBus main interface 1101 being communicatively connected to an SMBus interface of the graphics processor; the command generating unit 1103 generates an upgrade request command according to a predefined command frame format; the sending unit 1102 sends an upgrade request command to the graphics processor through the SMBus main interface 1101.
The operation principle of the processor 110 according to the embodiment of the present invention is the same as the operation principle of the processor 1 in the method 100, and the content thereof is incorporated herein and is not described herein again.
In addition, the processor 1100 according to the embodiment of the present invention may be a CPU or a BMC, for example, the processor 1100 may be at least a part of a CPU motherboard with an SMBus interface, or may also be at least a part of a motherboard of a server. Processor 1100 may also be at least a portion of another type of processor or a motherboard with a processor, as embodiments of the invention are not limited in this respect.
Furthermore, as shown in fig. 12, the processor 1100 may further include a detection unit 1104 and a PCIe interface 1105, where the detection unit 1104 detects whether communication of the PCIe interface 1105 is abnormal, and when the communication of the PCIe interface 1105 is detected to be abnormal, the processor 1100 may select to communicate with the graphics processor through the SMBus main interface 1101.
In addition, the processor 1100 may further include units that are not shown in fig. 12, for example, a storage unit, and the specific units included in the processor 1100 are not limited in this embodiment and may be configured according to actual situations.
The embodiment of the invention also provides computer equipment which comprises a memory, a graphics processor or a processor and a computer program which is stored on the memory and can run on the graphics processor or the processor, wherein when the graphics processor or the processor executes the computer program, the method for upgrading the firmware of the graphics processor is realized.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the method for upgrading the firmware of the graphic processor.
An embodiment of the present invention further provides a computer program product, where the computer program product includes a computer program, and when the computer program is executed by a processor, the method for upgrading firmware of the graphics processor is implemented.
In the embodiment of the invention, the firmware of the GPU is upgraded through the SMBus bus, so that when the PCIe bus is abnormal or fails due to the abnormality or the failure of the GPU board card and the communication cannot be carried out through the PCIe bus, the abnormality of the GPU board card is repaired on line.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (20)
1. A method of firmware upgrade of a graphics processor, the method comprising:
receiving an upgrade request command from a processor through a system management bus;
receiving firmware to be upgraded through the system management bus;
and upgrading the firmware of the graphic processor based on the firmware to be upgraded.
2. The method of claim 1, wherein upgrading firmware of a graphics processor based on the firmware to be upgraded comprises:
analyzing the firmware to be upgraded to acquire a signature, a firmware image and a universal unique identification code;
verifying the signature;
under the condition of successful verification, searching and analyzing a partition table from a storage medium according to the universal unique identification code;
and writing the firmware mirror image into the corresponding partition according to the analyzed partition table information.
3. The method of claim 2, wherein the method further comprises:
and in case of successful upgrade, sending an upgrade success message to the processor through the system management bus.
4. The method of claim 2, wherein, in the step of verifying the signature,
the signature is verified according to the RSA algorithm or SM2 algorithm.
5. The method of claim 1, wherein the method further comprises:
receiving an upgrade status confirmation message from a processor through the system management bus;
and sending an upgrade success message or an upgrade failure message to the processor through the system management bus.
6. The method of claim 5, wherein,
the upgrade success message or the upgrade failure message has a predefined message frame format.
7. The method of claim 1, wherein the method further comprises:
generating an upgrade confirm message in reply to the upgrade request command;
and sending the upgrade confirmation message to the processor through the system management bus.
8. The method of claim 7, wherein,
the upgrade confirm message has a predefined message frame format.
9. The method of claim 6 or 8,
the predefined message frame format includes a command header, and further includes at least one of a custom command field, a completion code field, and a second data field,
the command header is compatible with an intelligent platform management interface protocol;
the custom command field indicates that the command is a custom command,
the completion field indicates a status of command completion;
the second data field indicates the data carried by the command.
10. A method of firmware upgrade of a graphics processor, the method comprising:
generating an upgrade request command;
and sending the upgrading request command to a graphic processor through a system management bus.
11. The method of claim 10, wherein,
the upgrading request command carries the firmware to be upgraded.
12. The method of claim 10, wherein the method further comprises:
receiving an upgrade confirm message from a graphics processor through the system management bus;
and sending the firmware to be upgraded to the graphics processor through the system management bus.
13. The method of any of claims 10 to 12, wherein the method further comprises:
generating an upgrade status request command;
and sending the upgrade status request command to the graphics processor through the system management bus.
14. The method of claim 13, wherein,
the upgrade request command or the upgrade status request command has a predefined command frame format,
the predefined command frame format includes a command header, and further includes at least one of a custom command field, a sub-command field, a data length field, and a first data field,
the command header is compatible with the intelligent platform management interface protocol,
the custom command field indicates that the command is a custom command,
the sub-command field indicates a category of command;
the first data field indicates the data carried by the command or the type of the data carried by the command;
the data length field indicates the length of the data indicated by the first data field or the length of the data corresponding to the type indicated by the first data field.
15. A graphics processor, the graphics processor having:
the system management bus slave interface is in communication connection with the system management bus master interface of the processor;
a receiving unit that receives an upgrade request command from the processor through the system management bus from an interface;
the receiving unit also receives firmware to be upgraded from the processor from an interface through the system management bus.
16. A processor, characterized in that the processor has:
the system management bus master interface is in communication connection with a system management bus slave interface of the graphics processor;
a command generating unit that generates an upgrade request command;
a transmitting unit that transmits the upgrade request command to a graphic processor through the system management bus master interface.
17. A computer device comprising a memory, a graphics processor and a computer program stored on the memory and executable on the graphics processor, characterized in that the graphics processor implements the method of any of claims 1 to 9 when executing the computer program.
18. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any of claims 10 to 14 when executing the computer program.
19. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by a processor, implements the method of any one of claims 1 to 14.
20. A computer program product, characterized in that the computer program product comprises a computer program which, when being executed by a processor, carries out the method of any one of claims 1 to 14.
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