CN106528464A - Computer system with memory access conflict control - Google Patents
Computer system with memory access conflict control Download PDFInfo
- Publication number
- CN106528464A CN106528464A CN201610981615.6A CN201610981615A CN106528464A CN 106528464 A CN106528464 A CN 106528464A CN 201610981615 A CN201610981615 A CN 201610981615A CN 106528464 A CN106528464 A CN 106528464A
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- CN
- China
- Prior art keywords
- master controllers
- smbus
- smbus master
- controller
- coffret
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Abstract
The invention provides a computer system with memory access conflict control. The computer system is provided with a first SMBUS (System Management Bus) master controller, a second SMBUS master controller, a controller and a selector, wherein the controller outputs a control signal when the first SMBUS master controller and the second SMBUS master controller both request to read and write memory, and the selector selectively switches the first SMBUS master controller or the second SMBUS master controller to read and write the memory via a transmission interface according to the control signal. When the control signal indicates the selector to select the first SMBUS master controller to read and write the memory and the first SMBUS master controller finishes reading and writing the memory, the controller receives an end signal output by the first SMBUS master controller, and indicates the selector to switch the second SMBUS master controller to read and write the memory via the transmission interface.
Description
Technical field
The present invention relates to regard to a kind of computer system, particularly a kind of department of computer science with memory access conflict control
System.
Background technology
In a single computer system, baseboard management controller (Baseboard ManagementController, BMC)
Manage the working condition of whole server system, such as temperature, voltage, electric fan, power supply supply and cabinet invasion etc..Substrate pipe
Reason controller provides the functions such as server system autonomic monitoring, logout and Fault recovery, belongs in server system quite
An important management assembly.
Based on cost control and the design concept of Performance optimization, the workstation platform (platform) of present new development by
Gradually no longer adopt and be used as control signal communication using baseboard management controller, but use platform path controller
(Platform Controller Hub) little by little replaces the function of baseboard management controller control signal communication.However, in order to
The transmission port for making platform path amount controller limited or transmission path, can efficiently be supplied to central processing unit to carry out
Transmission communication between other assemblies, has the setting that multiple components share a transport part or transmission path often, and then
Platform path controller is allowed easily to have the problem of access conflict.
The content of the invention
It is an object of the invention to provide a kind of computer system with memory access conflict control, uses platform path
There is the problem of access conflict in controller.
In order to achieve the above object, the invention provides a kind of computer system with memory access conflict control, tool
(second system is controlled a SMBUS master controllers (the first system controlling bus master controller), the 2nd SMBUS master controllers
Bus master controller), controller and selector.The communication that first SMBUS master controllers are used between input/output bus.Second
SMBUS master controllers are used for the monitoring of system hardware program.Controller couples a SMBUS master controllers, as a SMBUS master
When controller and the 2nd SMBUS master controllers all require read/write memory, controller output control signal.Selector coupling control
Device, a SMBUS master controllers and the 2nd SMBUS master controllers.Selector receives control signal, and selects according to control signal
Property ground switching the first SMBUS master controllers or the 2nd SMBUS master controllers via coffret read/write memory.When control signal refers to
Show that selector is selected by a SMBUS master controller read/write memories, and when a SMBUS master controllers have read and write internal memory, control
Device processed receives the end signal of SMBUS master controllers output, and depending at least on end signal, output control signal, to refer to
Show that selector switches the 2nd SMBUS master controllers via coffret read/write memory.
The computer system with memory access conflict control according to disclosed by the invention described above, by controller the
When one SMBUS master controllers and the 2nd SMBUS master controllers occur access conflict, control signal is produced to selector, make selection
Device controls to allow a SMBUS master controllers to be conducted to coffret according to control signal, or allows the 2nd SMBUS master controllers to lead
Coffret is passed to, is used and is solved the problems, such as that a SMBUS master controllers and the 2nd SMBUS master controllers occur access conflict.
Description of the drawings
Fig. 1 is the functional block diagram of the computer system according to one embodiment of the invention；
The functional block diagram of computer system of Fig. 2 systems according to another embodiment of the present invention.
In figure：
10th, 20 computer system
11st, 21 the oneth SMBUS master controllers
12nd, 22 the 2nd SMBUS master controllers
13rd, 23 controller
14th, 24 selector
15th, 25 coffret
Specific embodiment
The specific embodiment of the present invention is described in more detail below in conjunction with schematic diagram.According to description below and
Claims, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is in the form of simplifying very much and equal
Using non-accurately ratio, only to purpose that is convenient, lucidly aiding in illustrating the embodiment of the present invention.
Fig. 1 is refer to, Fig. 1 is the functional block diagram of the computer system according to one embodiment of the invention.Such as Fig. 1 institutes
Show, computer system 10 have the first system controlling bus (System Management Bus, SMBUS) master controller 11, the
Two system controlling bus (System Management Bus, SMBUS) master controller 12, controller 13, selector 14, transmission
Interface 15 and internal memory 16.
The first system controlling bus master controller 11, hereinafter referred to as a SMBUS master controllers 11, e.g. platform path control
Other suitable group in device (Platform Controller Hub) processed, South Bridge chip, north bridge chips or computer system 10
Part.The communication that first SMBUS master controllers 11 are used between input/output bus, in other words, a SMBUS master controllers 11 are electric
Property is connected to the central processing unit (Central Processing Unit, CPU) in computer system 10, to control central authorities
Signal communication of the processor to other assemblies.
Second system controlling bus master controller 12, hereinafter referred to as the 2nd SMBUS master controllers 12, e.g. hardware monitor
(Hardware Monitor) or other suitable components.2nd SMBUS master controllers 12 are used for the monitoring of system hardware program,
The information of hardware in fan, display adapter, the temperature of hard disk, frequency, electricity or other computer systems 10 is monitored such as.
Controller 13 is, for example, a kind of complexity can program logic device (Complex Programmable Logic
Device, CPLD).Controller 13 couples a SMBUS master controllers 11, selector 14 and coffret 15.Implement at one
In example, a SMBUS master controllers 11 are held with universal input and output (General Purpose I/O), 13 coupling of controller
It is connected to the universal input/output terminal of a SMBUS master controllers 11.
Selector 14 for example has first input end, the second input, control end and output end.The first of selector 14 is defeated
Enter end and be electrically connected with a SMBUS master controllers 11, the second input of selector 14 is electrically connected with the 2nd SMBUS master controllers
12.First SMBUS master controllers 11 and the 2nd SMBUS master controllers 12 are turned on coffret 15 via selector 14.One
In individual embodiment, a SMBUS master controllers 11 and the 2nd SMBUS master controllers 12 are with System control bus (System
Management Bus, SMBUS) used as the terminal of transmission standard, selector 14 and a SMBUS master controllers 11 are with system control
Bus processed is electrically connected with, and selector 14 and the 2nd SMBUS master controllers 12 are similarly electrically connected with System control bus.Select
The control end of device 14 is electrically connected with controller 13, and output end is electrically connected with coffret 15.In one embodiment, coffret
The coffret of 15 output ends for referring to selector 14, selector 14 are electrically connected to memory 16 by coffret 15.
In the situation of a running of computer system 10, when a SMBUS master controllers 11 and the 2nd SMBUS main controls
When device 12 is required simultaneously by 15 read/write memory 16 of coffret, controller 13 outputs control signals to selector 14.At one
In embodiment, controller 13 detects what a SMBUS master controllers 11 and the 2nd SMBUS master controllers 12 were connected with selector 14
SMBUS is judging whether a SMBUS master controllers 11 and the 2nd SMBUS master controllers 12 require read/write memory 16.Another
In individual embodiment, controller 13 can also be notified via selected device 14, and learns a SMBUS master controllers 11 and second
SMBUS master controllers 12 all require the situation of read/write memory 16.In other words, controller 13 in a SMBUS master controllers 11 and
When 2nd SMBUS master controllers 12 occur access conflict, control signal is produced.
Selector 14 receives the control signal of the output of controller 13, and optionally switches first according to control signal
One of SMBUS master controllers 11 and the 2nd SMBUS master controllers 12 can carry out read/write memory 16 via coffret 15.
That is, the control signal that selector 14 is exported according to controller 13 is determining to allow 11 read/write memory of a SMBUS master controllers
16 allow 12 read/write memory 16 of the 2nd SMBUS master controllers.
When control signal indicates that selector 14 is selected by SMBUS 11 read/write memories 16 of master controller, a SMBUS
Master controller 11 is turned on by coffret 15 and internal memory 16 with read/write memory 16.When a SMBUS master controllers 11 have been read and write
During internal memory 16, a SMBUS master controllers 11 are believed with universal input/output terminal (General Purpose I/O) end of output
Number to controller 13, to inform message that the read-write of controller 13 is completed.Controller 13 is exported according to a SMBUS master controllers 11
End signal, output control signal, with indicate selector 14 switching allow the 2nd SMBUS master controllers 12 via coffret 15
Read/write memory 16.
In one embodiment, when controller 13 receives the end signal of SMBUS master controllers output, control
Device 13 can go to read the signal on coffret 15, detecting coffret 15 whether idle (idle).When controller 13 judges to pass
When defeated interface 15 leaves unused, ability output control signal, and output control signal, allow selector 14 to be switched to the 2nd SMBUS main controls
12 read/write memory 16 of device.In other words, controller 13 except according to a SMBUS master controllers 11 output end signal, also according to
Carry out output control signal according to whether coffret 15 leaves unused.
In the example of a reality, coffret 15 at least has data line and frequency signal line.Data transfer
Line transmits the data of internal memory 16 to a SMBUS master controllers 11 to transmit data-signal, such as.Frequency signal line is to pass
Frequency signal is sent, allows data line to carry out transmission data according to frenquency signal.In the present embodiment, controller 13 can be according to number
It is believed that number and frequency signal voltage level, judge whether coffret 15 leaves unused.
Next, refer to Fig. 2, Fig. 2 is the function block of the computer system according to another embodiment of the present invention
Figure.As shown in Fig. 2 computer system 20 has a SMBUS master controllers 21, the 2nd SMBUS master controllers 22, controller
23rd, selector 24, coffret 25 and internal memory 26.First SMBUS master controllers 21 are, for example, platform path controller
Other suitable components in (Platform Controller Hub), South Bridge chip, north bridge chips or computer system 20, use
With the communication between the input/output bus of control central processing unit.2nd SMBUS master controllers 22 are, for example, hardware monitor
(HardwareMonitor) or other suitable components, to hardware program or hardware information in supervisory computer system 20.
Controller 23 be, for example, complexity can program logic device, be electrically connected at a SMBUS master controllers 21, selector
24 and coffret 25.Selector 24 has first switch 241 and second switch 242.First switch 241 is arranged at first
In SMBUS master controllers 21 and the transmission path of internal memory 26, second switch 242 be arranged at the 2nd SMBUS master controllers 22 with it is interior
Deposit in 26 transmission path.First switch 241 and second switch 242 are turned on according to the control of controller 23, and make a SMBUS
Master controller 21 is turned on internal memory 26 by coffret 25, or make the 2nd SMBUS master controllers 22 by coffret 25 with
Internal memory 26 is turned on, with read/write memory 26.
In one embodiment, a SMBUS master controllers 21 and the 2nd SMBUS master controllers 22 are with system control
Bus (System Management Bus, SMBUS) is used as the terminal of transmission standard, first switch 241 and a SMBUS master
Controller 21 is electrically connected with by System control bus, and second switch 242 and the 2nd SMBUS master controllers 22 are likewise by being
System controlling bus are electrically connected with.In one embodiment, coffret 25 refers to the coffret of the output end of selector 24, choosing
Select device 24 memory 26 is electrically connected to by coffret 25.
In one embodiment, first switch 241 is predetermined to be conducting, and second switch 242 is predetermined to be and is not turned on.Change
Yan Zhi, in computer system 20 is operated, when 22 failed call read/write memory 26 of the 2nd SMBUS master controllers, a SMBUS master
Controller 21 can be reached by 25 read/write memory 26 of coffret.When the 2nd SMBUS master controllers 22 require read/write memory 26
When, a SMBUS master controllers 21 also require that read/write memory 26.Now, a SMBUS master controllers 21 and the 2nd SMBUS
There is access conflict in master controller 22.Controller 23 outputs control signals to first switch 241 and second switch 242, to control
First switch 241 and second switch 242 are turned on or are not turned on, and mediate a SMBUS master controllers 21 and the 2nd SMBUS master controls
The requirement of 22 read/write memory 26 of device processed.
In the present embodiment, controller 23 can output control signal indicate that first switch 241 is switching-on, and control the
Two switches 242 are switched to and are not turned on, and make a SMBUS master controllers 21 by coffret read/write memory 26.When first
When SMBUS master controllers 21 have read and write internal memory 26, controller 23 can receive a SMBUS master controls from universal input/output terminal
Device processed 21 informs the end signal that read-write is completed.The end signal that controller 23 is exported according to a SMBUS master controllers 21, reads
The data line and frequency signal line on coffret 25 is taken, according to data-signal and the voltage level of frequency signal, is judged
Whether coffret 25 leaves unused.
When controller 23 judges that coffret 25 leaves unused, 23 output control signal of controller, to control first switch 241
Switch to and be not turned on, and it is switching-on to control second switch 242.When second switch 242 is turned on, the 2nd SMBUS main controls
Device 22 can pass through 25 read/write memory 26 of coffret.
It is comprehensive the above, the embodiment of the present invention provides a kind of computer system with memory access conflict control, mat
By controller when a SMBUS master controllers and the 2nd SMBUS master controllers occur access conflict, controlled with control signal
Selector so that one of a SMBUS master controllers and the 2nd SMBUS master controllers can be connect by selector and transmission
Mouth is conducted to internal memory to carry out reading and writing data, uses the first SMBUS master controllers of solution and the 2nd SMBUS master controllers occur to visit
Ask the problem of conflict
The preferred embodiments of the present invention are above are only, any restriction effect is not played to the present invention.Belonging to any
Those skilled in the art, in the range of without departing from technical scheme, to the invention discloses technical scheme and
Technology contents make the variation such as any type of equivalent or modification, belong to the content without departing from technical scheme, still
Belong within protection scope of the present invention.
Claims (8)
1. it is a kind of with memory access conflict control computer system, it is characterised in that the computer system includes：
One the oneth SMBUS master controllers, for the communication between input/output bus；
One the 2nd SMBUS master controllers, for the monitoring of system hardware program；
One controller, couples a SMBUS master controllers, in a SMBUS master controllers and the 2nd SMBUS master controls
When device processed all requires to read and write an internal memory, the controller exports a control signal；And
One selector, couples the controller, a SMBUS master controllers and the 2nd SMBUS master controllers, and the selector connects
The control signal is received, and optionally switches a SMBUS master controllers or described second according to the control signal
SMBUS master controllers read and write the internal memory via a coffret；
Wherein when the control signal indicates that the selector selects to read and write the internal memory by a SMBUS master controllers, and
When a SMBUS master controllers have read and write the internal memory, controller receives the SMBUS master controllers output
One end signal, and depending at least on the end signal, export the control signal, to indicate the selector switching described the
Two SMBUS master controllers read and write the internal memory via the coffret.
2. there is the computer system of memory access conflict control as claimed in claim 1, it is characterised in that the controller
When receiving the end signal of the SMBUS master controllers output, whether the controller judges the coffret
It is idle, and when the controller judges that the coffret leaves unused, the control signal is exported, to indicate that the selector is cut
Change the 2nd SMBUS master controllers internal memory is read and write via the coffret.
3. there is the computer system of memory access conflict control as claimed in claim 2, it is characterised in that the transmission
Interface includes at least a data line and a frequency signal line, and the data line is to transmit a data-signal, described
Frequency signal line to transmit a frequency signal, the controller according to the data-signal and the voltage level of frequency signal,
Judge whether the coffret leaves unused.
4. there is the computer system of memory access conflict control as claimed in claim 1, it is characterised in that the selection
Utensil has a first switch and a second switch, and the first switch is arranged at the coffret with a SMBUS master
In the transmission path of controller, the second switch is arranged at the biography of the coffret and the 2nd SMBUS master controllers
On defeated path, when the 2nd SMBUS master controllers do not read and write the internal memory, the selector is preset conducting described first and is opened
Close and disconnect the second switch.
5. there is the computer system of memory access conflict control as claimed in claim 1, it is characterised in that described first
SMBUS master controllers are a platform path controller.
6. there is the computer system of memory access conflict control as claimed in claim 1, it is characterised in that described second
SMBUS master controllers are a hardware monitor.
7. there is the computer system of memory access conflict control as claimed in claim 1, the coffret for one is
System controlling bus.
8. there is the computer system of memory access conflict control, a SMBUS main controls as claimed in claim 1
Utensil has a universal input/output terminal, and a SMBUS master controllers couple institute by the universal input/output terminal
State controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610981615.6A CN106528464A (en) | 2016-11-08 | 2016-11-08 | Computer system with memory access conflict control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610981615.6A CN106528464A (en) | 2016-11-08 | 2016-11-08 | Computer system with memory access conflict control |
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| Publication Number | Publication Date |
|---|---|
| CN106528464A true CN106528464A (en) | 2017-03-22 |
Family
ID=58349989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610981615.6A Pending CN106528464A (en) | 2016-11-08 | 2016-11-08 | Computer system with memory access conflict control |
Country Status (1)
| Country | Link |
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| CN (1) | CN106528464A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108491299A (en) * | 2018-04-03 | 2018-09-04 | 郑州云海信息技术有限公司 | A kind of signal detection board and the mainboard for signal detection |
| US11768788B2 (en) | 2019-07-23 | 2023-09-26 | Hewlett-Packard Development Company, L.P. | Bus endpoint isolation |
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| CN1452745A (en) * | 2000-04-03 | 2003-10-29 | 先进微装置公司 | Bus bridge including memory controller having improved memory request arbitration mechanism |
| CN1819525A (en) * | 2004-11-15 | 2006-08-16 | 英特尔公司 | Intelligent platform management bus switch system |
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| CN108491299A (en) * | 2018-04-03 | 2018-09-04 | 郑州云海信息技术有限公司 | A kind of signal detection board and the mainboard for signal detection |
| US11768788B2 (en) | 2019-07-23 | 2023-09-26 | Hewlett-Packard Development Company, L.P. | Bus endpoint isolation |
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Application publication date: 20170322 |