CN113064771B - I2C link checking method, system, terminal and storage medium - Google Patents
I2C link checking method, system, terminal and storage medium Download PDFInfo
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- CN113064771B CN113064771B CN202110239590.3A CN202110239590A CN113064771B CN 113064771 B CN113064771 B CN 113064771B CN 202110239590 A CN202110239590 A CN 202110239590A CN 113064771 B CN113064771 B CN 113064771B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention provides an I2C link checking method, a system, a terminal and a storage medium, which can all comprise the following steps: analyzing a schematic diagram netlist generated by EDA software, acquiring names netnames of all networks in the schematic diagram netlist, and analyzing all I2C related netnames from all the acquired names netnames, wherein all the I2C related netnames are marked as target network names netnames; analyzing a schematic diagram device table generated by EDA software, determining data representing a server device, and analyzing all I2C related devices from the determined data of the server device to be marked as target devices; constructing an I2C link by adopting the target network name netname and the target device; checking whether the SCL and the SDA in the constructed I2C link are connected correctly or not; it is checked whether there is only one pull-up resistor in the I2C link constructed. The method is used for reducing the difficulty of I2C link construction.
Description
Technical Field
The invention relates to the field of servers, in particular to an I2C link checking method, a system, a terminal and a storage medium.
Background
I2C (Inter-integrated circuit) is an abbreviation of I2CBus, named integrated circuit bus, which is a serial communication bus. The I2C bus is a half-duplex (bi-directional) structure, in which data can flow in both directions, but data is allowed to flow in only one direction at a time, and the whole circuit structure is composed of two signal lines, i.e. a serial data line (SDA) and a Serial Clock Line (SCL) connecting one or more microcontrollers and a plurality of interface devices.
Each device connected in parallel to the bus, such as BMC, EEPROM, CPU, PCH, CPLD, GPIO, etc., has a unique address for transmitting or receiving data to or from each other. In the two lines of I2C, SDA is dedicated to transmitting data, SCL is used to transmit clock, and these two lines cannot be connected in reverse, if a connection error occurs, for example, the chip side SCL is connected to the chip side SDA, or the chip side SDA is connected to the chip side SCL, which results in the device being unusable.
Both SDA and SCL lines of I2CBus need to add pull-up resistor (pull-up resistor) to convert the floating state to logic High (High) state, but the whole link only needs one pull-up resistor, and the repeated pull-up resistors can cause unnecessary cost increase. In addition, each I2C device can be optionally provided with an impedance matching resistor according to the requirement of the current situation. Current schematic designs are often done with EDA software, and developers need to manipulate the software to connect all I2C devices, matching resistors, and pull-up resistors together. However, the server product has a complex structure, and the types and the number of electronic components are many, and errors occurring in the I2C link cannot be known in time, so that the difficulty in ensuring the design quality of the I2C device is high.
Therefore, the present invention provides an I2C link check method, system, terminal and storage medium, which are used to solve the above problems.
Disclosure of Invention
In view of the foregoing defects in the prior art, the present invention provides an I2C link checking method, system, terminal and storage medium, which are used to assist in improving the design quality of I2C devices.
In a first aspect, the present invention provides an I2C link checking method, including the steps of:
analyzing a schematic diagram netlist generated by EDA software, acquiring names netnames of all networks in the schematic diagram netlist, and analyzing all I2C related netnames from all the acquired names netnames, wherein all the I2C related netnames are marked as target network names netnames;
analyzing a schematic diagram device table generated by EDA software, determining data representing a server device, and analyzing all I2C related devices from the determined data of the server device to be marked as target devices;
constructing an I2C link by adopting the target network name netname and the target device;
checking whether the SCL and the SDA in the constructed I2C link are connected correctly or not;
it is checked whether there is only one pull-up resistor in the I2C link constructed.
Further, the method for checking whether SCL and SDA in the constructed I2C link are connected correctly is as follows:
checking whether the Pinname of a target device in the I2C link is connected to the target network name netname of the SCL when the Pinname of the target device is the SCL;
checking whether the target device in the I2C link is connected to the target network name netname of the SDA when the Pinname of the target device is the SDA.
Further, the method for checking whether there is only one pull-up resistor in the constructed I2C link is as follows:
and detecting whether only one pull-up resistor is arranged in the I2C link or not by checking the number of the resistors which are connected to the power supply at the single end in the I2C link.
Further, the checking of the number of resistors connected to the power supply at one end in the I2C link is based on: the power source is conventionally named.
In a second aspect, the present invention provides an I2C link inspection system, comprising:
the netlist analyzing unit is used for analyzing the schematic diagram netlist generated by the EDA software, acquiring the names netnames of all networks in the schematic diagram netlist, and analyzing all I2C related netnames from the acquired names netnames, wherein the names are marked as target network names;
the device unit is used for analyzing a schematic diagram device table generated by EDA software, determining data representing the server device, and analyzing all I2C related devices from the determined data of the server device and marking as target devices;
the link construction unit is used for constructing an I2C link by adopting the target network name netname and the target device;
the first checking unit is used for checking whether the SCL and the SDA in the constructed I2C link are connected correctly or not;
and the second checking unit is used for checking whether the built I2C link has only one pull-up resistor.
Further, the first checking unit includes:
the first SCL checking module is used for checking whether the target device in the I2C link is connected to the target network name netname of the SCL when the Pinname of the target device is the SCL;
a first SDA checking module for checking whether a target device in the I2C link is connected to a target network name netname of SDA when the Pinname of the target device is SDA.
Further, the method for the second checking unit to check whether the built I2C link has only one pull-up resistor includes: and detecting whether only one pull-up resistor exists in the I2C link or not by checking the number of the resistors connected to the power supply at a single end in the I2C link.
Further, the second checking unit checks the number of resistors of the I2C link that are connected to the power supply at one end according to: the power source is conventionally named.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The beneficial effect of the invention is that,
the I2C link inspection method, the system, the terminal and the storage medium provided by the invention can automatically realize the logical connection of all I2C related devices and all I2C related netnames in a schematic diagram and the inspection of the logical connection relation based on an electronic design auxiliary system, and are beneficial to feeding back I2C link errors to developers in time, so that the developers can correct the I2C link errors in time, the product quality is prevented from being low and even incapable of operating, the purpose of improving the design quality of the designed I2C equipment in an auxiliary manner is achieved, the development time of the developers can be saved, and the working efficiency is improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is another schematic flow diagram of a method of one embodiment of the invention.
FIG. 3 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a computer storage medium according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the present invention.
As shown in fig. 1, the method 100 includes:
step 110, analyzing a schematic diagram netlist generated by EDA software, acquiring names netnames of all networks in the schematic diagram netlist, and analyzing all I2C related netnames from all the acquired names netnames, wherein all the I2C related netnames are recorded as target network names netnames;
step 120, analyzing a schematic diagram device table generated by EDA software, determining data representing a server device, and analyzing all I2C related devices from the determined data of the server device, wherein the I2C related devices are marked as target devices;
step 130, constructing an I2C link by adopting the target network name netname and the target device;
step 140, checking whether the SCL and the SDA in the constructed I2C link are connected correctly respectively;
step 150 checks whether there is only one pull-up resistor in the constructed I2C link.
Optionally, as an embodiment of the present invention, a method for checking whether SCL and SDA in the constructed I2C link are connected correctly is:
checking whether the Pinname of a target device in the I2C link is connected to the target network name netname of the SCL when the Pinname of the target device is the SCL;
checking whether the target device in the I2C link is connected to the target network name netname of the SDA when the Pinname of the target device is the SDA.
Optionally, as an embodiment of the present invention, the method for checking whether there is only one pull-up resistor in the constructed I2C link includes:
and detecting whether only one pull-up resistor exists in the I2C link or not by checking the number of the resistors connected to the power supply at a single end in the I2C link.
Optionally, as an embodiment of the present invention, the checking of the number of resistors connected to the power supply at one end in the I2C link is based on: the power sources are conventionally named.
In order to facilitate understanding of the present invention, the principle of the present method is further described below with reference to the embodiment of the I2C link check method provided by the present invention.
As shown in fig. 2, the I2C link checking method includes:
step S1: the design software netlist file (the schematic netlist generated for EDA-based software) is analyzed and all netnames are extracted from it.
Specifically, the design software netlist file can be checked line by line for netname extraction until all rows of the design software netlist file are checked.
Step S2: and collecting all I2C related netnames from the extracted netnames.
And step S3: design software device files (schematic device tables generated based on EDA software) were analyzed and I2C related devices were gathered.
Correspondingly, the design software netlist file can be checked line by line for I2C related device collection until all the lines of the design software netlist file are checked.
And step S4: and integrating the I2C related netname and the I2C related device to construct a complete I2C link.
Step S5: and checking whether the device terminal SCL is connected with the SCL or not and checking whether the device terminal SDA is connected with the SDA or not.
If the checking result is that the device end SCL is connected with the SCL and the device end SDA is connected with the SDA, the respective logical connection relation of the SCL and the SDA of the constructed I2C link is correct, otherwise, the corresponding logical connection relation is wrong, and the wrong logical connection relation is output, so that developers can correct the errors in time.
Step S6: check if the I2C link constructed above has only one pull-up resistor.
If the checking result is yes, the checking is passed, otherwise, the constructed I2C link does not only have one pull-up resistor, and an error is output, so that a developer can correct the error in time.
As shown in fig. 3, the system 200 includes:
a netlist analyzing unit 201, configured to analyze a schematic diagram netlist generated by EDA software, obtain names netnames of all networks in the schematic diagram netlist, and analyze all I2C-related netnames from all the obtained names netnames, where all the names are denoted as target network names netnames;
the device unit 202 is used for analyzing a schematic diagram device table generated by EDA software, determining data representing the server device, and analyzing all I2C related devices from the determined data of the server device, wherein the I2C related devices are marked as target devices;
a link constructing unit 203, configured to construct an I2C link by using the target network name and the target device;
a first checking unit 204, configured to check whether SCL and SDA in the constructed I2C link are connected correctly respectively;
a second checking unit 205 for checking whether there is only one pull-up resistor in the constructed I2C link.
Optionally, as an embodiment of the present invention, the first checking unit 204 includes:
the first SCL checking module is used for checking whether the target device in the I2C link is connected to the target network name netname of the SCL when the Pinname of the target device is the SCL;
a first SDA checking module for checking whether a target network name netname of the SDA is connected when the Pinname of the target device in the I2C link is SDA.
Optionally, as an embodiment of the present invention, the method for the second checking unit 205 to check whether there is only one pull-up resistor in the constructed I2C link is as follows: and detecting whether only one pull-up resistor is arranged in the I2C link or not by checking the number of the resistors which are connected to the power supply at the single end in the I2C link.
Optionally, as an embodiment of the present invention, the checking by the second checking unit of the number of resistors connected to the power supply at one end in the I2C link is based on: the power source is conventionally named.
Fig. 4 is a schematic structural diagram of a terminal 300 according to an embodiment of the present invention, where the terminal 300 may be used to execute the method 100 according to the embodiment of the present invention.
Among them, the terminal 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium 400, as shown in fig. 5, the computer storage medium 400 may store a program 410, and the program 410 may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
The same and similar parts in the various embodiments in this specification may be referred to each other. In particular, as for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and reference may be made to the description in the method embodiment for relevant points.
The terms referred to in this specification are to be interpreted as:
I2C: inter-integrated circuit, integrated circuit bus;
EDA (electronic design automation): electronic design automation;
BMC: a BasebardManagementcontroller, a motherboard management controller;
a CPU: central processing unit, central processor;
EEPROM: an electrically erasable programmable read only memory (a type of memory);
platform controller, PCH;
CPLD: complexProgrammableLogicDevice, complex programmable logic device;
GPIO: general-purpose input/output.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. An I2C link check method, comprising the steps of:
analyzing a schematic diagram netlist generated by EDA software, acquiring names netnames of all networks in the schematic diagram netlist, and analyzing all I2C related netnames from all the acquired names netnames, wherein all the I2C related netnames are marked as target network names netnames;
analyzing a schematic diagram device table generated by EDA software, determining data representing a server device, and analyzing all I2C related devices from the determined data of the server device to be marked as target devices;
constructing an I2C link by adopting the target network name netname and the target device;
checking whether the SCL and the SDA in the constructed I2C link are connected correctly or not;
checking whether the built I2C link has only one pull-up resistor;
the method for checking whether the SCL and the SDA in the constructed I2C link are connected correctly respectively comprises the following steps:
checking whether the Pinname of a target device in the I2C link is connected to the target network name of the SCL when the Pinname of the target device is the SCL;
checking whether a target network name netname of the SDA is connected when the Pinname of the target device in the I2C link is the SDA;
the method for checking whether the built I2C link has only one pull-up resistor comprises the following steps:
and detecting whether only one pull-up resistor exists in the I2C link or not by checking the number of the resistors connected to the power supply at a single end in the I2C link.
2. The I2C link check method of claim 1, wherein the checking the number of resistors connected to the power supply at one end in the I2C link is based on: the power source is conventionally named.
3. An I2C link inspection system, comprising:
the netlist analyzing unit is used for analyzing the schematic diagram netlist generated by the EDA software, acquiring the names netnames of all networks in the schematic diagram netlist, and analyzing all I2C related netnames from the acquired names netnames, wherein the names are marked as target network names;
the device unit is used for analyzing a schematic diagram device table generated by EDA software, determining data representing the server device, and analyzing all I2C related devices from the determined data of the server device and marking as target devices;
the link construction unit is used for constructing an I2C link by adopting the target network name netname and the target device;
the first checking unit is used for checking whether the SCL and the SDA in the constructed I2C link are connected correctly or not;
the second checking unit is used for checking whether the built I2C link has only one pull-up resistor;
the first checking unit includes:
the first SCL checking module is used for checking whether the target device in the I2C link is connected to the target network name netname of the SCL when the Pinname of the target device is the SCL;
a first SDA checking module for checking whether a target network name netname of a target device in the I2C link is connected to the SDA when the Pinname of the target device is the SDA;
the method for the second checking unit to check whether the built I2C link has only one pull-up resistor comprises the following steps: and detecting whether only one pull-up resistor is arranged in the I2C link or not by checking the number of the resistors which are connected to the power supply at the single end in the I2C link.
4. The I2C link check system of claim 3, wherein the second check unit checks the number of resistors in the I2C link that are connected to the power supply on one end based on: the power source is conventionally named.
5. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any of claims 1-2.
6. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-2.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0884154A (en) * | 1994-09-13 | 1996-03-26 | Sony Corp | Bus line system |
| US6460094B1 (en) * | 1998-07-08 | 2002-10-01 | Microsoft Corporation | Peripheral device configured to detect the type of interface to which it is connected and configuring itself accordingly |
| CN204389654U (en) * | 2014-12-23 | 2015-06-10 | 东莞职业技术学院 | Based on the battery electric quantity detection system that cell resistance is followed the tracks of |
| CN105426557A (en) * | 2014-09-19 | 2016-03-23 | 昆达电脑科技(昆山)有限公司 | System and method for automatically checking pull-up resistor |
| CN107515958A (en) * | 2016-06-16 | 2017-12-26 | 迈普通信技术股份有限公司 | Wiring inspection method and device |
| CN107908912A (en) * | 2017-12-21 | 2018-04-13 | 郑州云海信息技术有限公司 | A kind of automatic method for checking line power and being connected to ground |
| CN108228917A (en) * | 2016-12-09 | 2018-06-29 | 展讯通信（上海）有限公司 | Circuit diagram check device and method |
| CN110941942A (en) * | 2019-11-29 | 2020-03-31 | 紫光展讯通信(惠州)有限公司 | Method, device and system for checking circuit schematic diagram |
| WO2020239944A1 (en) * | 2019-05-31 | 2020-12-03 | Ams International Ag | An inter-integrated circuit (i2c) apparatus |
| CN112052643A (en) * | 2020-08-27 | 2020-12-08 | 烽火通信科技股份有限公司 | Circuit schematic diagram checking method and system |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080141194A1 (en) * | 2006-12-07 | 2008-06-12 | Fujitsu Limited | Check support apparatus, method, and computer product |
| US7653886B2 (en) * | 2007-05-16 | 2010-01-26 | Mark Laing | Crosslinking of netlists |
| US8601173B2 (en) * | 2010-06-30 | 2013-12-03 | Silicon Image, Inc. | Detection of cable connections for electronic devices |
| JP6115042B2 (en) * | 2012-08-27 | 2017-04-19 | 富士通株式会社 | Information processing device, test data creation device, test data creation method, and program |
| US9864825B2 (en) * | 2016-02-01 | 2018-01-09 | Ciena Corporation | Systems and methods for dynamic symbols for devices in electrical schematics |
-
2021
- 2021-03-04 CN CN202110239590.3A patent/CN113064771B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0884154A (en) * | 1994-09-13 | 1996-03-26 | Sony Corp | Bus line system |
| US6460094B1 (en) * | 1998-07-08 | 2002-10-01 | Microsoft Corporation | Peripheral device configured to detect the type of interface to which it is connected and configuring itself accordingly |
| CN105426557A (en) * | 2014-09-19 | 2016-03-23 | 昆达电脑科技(昆山)有限公司 | System and method for automatically checking pull-up resistor |
| CN204389654U (en) * | 2014-12-23 | 2015-06-10 | 东莞职业技术学院 | Based on the battery electric quantity detection system that cell resistance is followed the tracks of |
| CN107515958A (en) * | 2016-06-16 | 2017-12-26 | 迈普通信技术股份有限公司 | Wiring inspection method and device |
| CN108228917A (en) * | 2016-12-09 | 2018-06-29 | 展讯通信（上海）有限公司 | Circuit diagram check device and method |
| CN107908912A (en) * | 2017-12-21 | 2018-04-13 | 郑州云海信息技术有限公司 | A kind of automatic method for checking line power and being connected to ground |
| WO2020239944A1 (en) * | 2019-05-31 | 2020-12-03 | Ams International Ag | An inter-integrated circuit (i2c) apparatus |
| CN110941942A (en) * | 2019-11-29 | 2020-03-31 | 紫光展讯通信(惠州)有限公司 | Method, device and system for checking circuit schematic diagram |
| CN112052643A (en) * | 2020-08-27 | 2020-12-08 | 烽火通信科技股份有限公司 | Circuit schematic diagram checking method and system |
Non-Patent Citations (1)
| Title |
|---|
| 网络表装入分析;段萍峰;《黑龙江科技信息》;20030215(第04期);全文 * |
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