CN110781501A - Control circuit and server - Google Patents
Control circuit and server Download PDFInfo
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- CN110781501A CN110781501A CN201910959058.1A CN201910959058A CN110781501A CN 110781501 A CN110781501 A CN 110781501A CN 201910959058 A CN201910959058 A CN 201910959058A CN 110781501 A CN110781501 A CN 110781501A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/575—Secure boot
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Abstract
The application discloses control circuit includes: the system comprises a power switch, an OR gate, an AND gate, a bridge chip, a memory and a trusted platform control module TPCM; the first input end of the OR gate is connected with the power switch; the second input end of the OR gate is connected with the measurement signal end of the TPCM; the output end of the OR gate is connected with the control end of the bridge piece and is used for controlling a control end signal of the bridge piece; the first input end of the AND gate is connected with the measurement signal end of the TPCM; the second input end of the AND gate is connected with a TPCM in-place signal end of the TPCM; the output end of the AND gate is connected with the control end of the gate; the first interface of the gate is connected with the first interface of the bridge chip, the second interface of the gate is connected with the first interface of the memory, and the third interface of the gate is connected with the first interface of the TPCM.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a control circuit and a server.
Background
A Trusted Platform Control Module (TPCM) is applied to the field of computers, and the TPCM can guarantee the safety and reliability of the system.
In the actual application process of the TPCM, the TPCM has strict requirements on the power-on time sequence of the mainboard, the TPCM needs to measure the bottom file in the mainboard before the mainboard is powered on, and the mainboard is powered on after the bottom file is measured to be abnormal.
In the conventional technology, the power-on timing sequence is controlled by a Complex Programmable Logic Device (CPLD), and at this time, the CPLD needs to be added on the motherboard to control the power-on timing sequence of the motherboard, which causes cost waste, and the CPLD also needs software support for operation, further increasing development cost.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a control circuit and a device, which can realize the control of the power-on time sequence of a mainboard without adding a CPLD.
A control circuit, comprising: the system comprises a power switch, an OR gate, an AND gate, a bridge chip and a trusted platform control module TPCM;
the first input end of the OR gate is connected with the power switch; the power switch is at a low level when being switched off and at a high level when being switched off;
the second input end of the OR gate is connected with the measurement signal end of the TPCM; wherein, before said TPCM measures the memorizer, said measurement signal terminal is the high level, after said TPCM measures the memorizer, said measurement signal terminal is the low level;
the output end of the OR gate is connected with the control end of the bridge piece; when the control end of the bridge chip is at a low level, the bridge chip guides the file in the memory to initialize the system;
the first input end of the AND gate is connected with the measurement signal end of the TPCM;
the second input end of the AND gate is connected with a TPCM in-place signal end of the TPCM; wherein, the TPCM is at high level at the bit signal end;
the output end of the AND gate is connected with the control end of the gate;
the first interface of the gate is connected with the first interface of the bridge chip;
the second interface of the gate is connected with the memory;
the third interface of the gate is connected with the first interface of the TPCM.
Optionally, the and gate includes: a first AND gate and a second AND gate;
optionally, the gate includes: a first gate and a second gate;
the first input end of the first AND gate is connected with a basic input output system memory BIOS FLASH measurement signal end of the TPCM;
the first input end of the first AND gate is connected with the second input end of the OR gate;
the second input end of the first AND gate is connected with the TPCM in-place signal end of the TPCM;
the output end of the first AND gate is connected with the control end of the first gate;
the first interface of the first gate is connected with the first interface of the bridge chip;
the second interface of the first gate is connected with the BIOS FLASH;
the third interface of the first gate is connected with the first interface of the TPCM;
the first input end of the second AND gate is connected with a baseboard management control memory BMC FLASH measurement signal end of the TPCM;
a second input end of the second AND gate is connected with the TPCM in-place signal end of the TPCM; the output end of the second AND gate is connected with the control end of the second gate;
a first interface of the second gate is connected with a baseboard management controller BMC;
a second interface of the second gate is connected with the BMC FLASH;
the third interface of the second gate is connected with the second interface of the TPCM; and in the process of measuring the memory by the TPCM, firstly measuring the BMC FLASH and then measuring the BIOS FLASH.
Optionally, when the control terminal of the gate is at a high level, the second interface and the third interface of the gate are turned on, so that the TPCM measures the memory; when the control end of the gate is in a low level, the first interface and the second interface of the gate are conducted, so that the bridge chip is connected with the memory.
Optionally, the gate is a multi-way selection switch.
Optionally, the first and gate includes a first diode and a second diode; and the anode of the first diode is connected with the anode of the second diode to serve as the output end of the first AND gate, the cathode of the first diode serves as the first input end of the first AND gate, and the cathode of the second diode serves as the second input end of the first AND gate.
Optionally, the second and gate includes a third diode and a fourth diode;
and the anode of the third diode is connected with the anode of the fourth diode to serve as the output end of the second AND gate, the cathode of the third diode serves as the first input end of the second AND gate, and the cathode of the fourth diode serves as the second input end of the second AND gate.
A server, comprising the above circuit, further comprising: a CPU and a memory;
the circuit is used for controlling the power-on time sequence of the memory;
the circuit is also used for guiding the CPU to initialize.
Compared with the prior art, the invention has the following advantages:
referring to the circuit shown in fig. 1, before the TPCM measures the memory, the measurement signal terminal is at a high level, and one input terminal of the or gate is at a high level, then the output of the or gate is at a high level, at this time, after the power switch is turned on, a control terminal signal of the bridge chip is at a high level, the bridge chip does not guide the system initialization, since the TPCM is at a high level at the in-place signal terminal, and at this time, the control terminal of the gate is at a high level, the memory is turned on with the TPCM, the TPCM measures the memory, after the measurement is completed, the measurement signal terminal is at a low level, since one input terminal of the and gate is at a low level, the output of the and gate is at a low level, and at this time, the control terminal of the gate is at a low level, the memory is turned on with the bridge chip, and the power switch is turned on, then both input terminals of the or, the output of the or gate is at a low level, the control end of the bridge chip is at the low level, the bridge chip guides the file in the memory to initialize the system, the CPLD in the traditional technology is replaced by the control circuit, the cost is reduced, further, the control circuit does not need software support, and the development cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a control circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a control circuit according to another embodiment of the present disclosure;
fig. 3a is a schematic structural diagram of a first and gate according to an embodiment of the present disclosure;
fig. 3b is a schematic structural diagram of a second and gate according to the embodiment of the present application;
fig. 4 is a schematic structural diagram of a server according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the actual application process of the TPCM, the TPCM has strict requirements on the power-on time sequence of the mainboard, before the mainboard is powered on, the TPCM needs to measure the bottom file in the mainboard, and after the measurement of the bottom file is not abnormal, the mainboard is powered on.
Various non-limiting embodiments of the present application are described in detail below with reference to the accompanying drawings.
The first embodiment is as follows:
referring to fig. 1, the diagram is a schematic structural diagram of a control circuit according to an embodiment of the present disclosure.
The control circuit provided in the first embodiment of the present application includes: power switch 101, or gate 102, and gate 103, bridge 104, gate 105, and TPCM 106;
a first input terminal of the or gate 102 is connected to the power switch 101;
a second input of the or gate 102 is connected to a metric signal terminal of the TPCM 106;
the output end of the or gate 102 is connected with the control end of the bridge plate 104;
a first input terminal of the and gate 103 is connected to a measurement signal terminal of the TPCM 106;
a second input end of the and gate 103 is connected with a TPCM in-place signal end of the TPCM 106;
the output end of the and gate 103 is connected with the control end of the gate 105;
a first interface of the gate 105 is connected with a first interface of the bridge chip 104;
the second interface of the gate 105 is connected with the memory 107;
the third interface of the gate 105 is connected to the first interface of the TPCM 106.
It should be noted that, in the first embodiment of the present application, the power switch 101 is at a low level when closed, and at a high level when open; before the TPCM106 measures the memory 107, the measurement signal terminal is at a high level, and after the TPCM106 measures the memory 107, the measurement signal terminal is at a low level; when the control terminal of the bridge chip 104 is at a low level, the bridge chip 104 guides the file in the memory 107 through the connection established by the gate 105 to initialize the system; the TPCM is at high level at the bit signal end.
It should be noted that, in a first implementation manner of this embodiment of the present application, when the control terminal of the gate 105 is at a high level, the second interface and the third interface of the gate 105 are turned on, so that the TPCM106 measures the file in the memory 107, and when the control terminal of the gate 105 is at a low level, the first interface and the second interface of the gate 105 are turned on, so that the bridge slice 104 establishes a connection with the file in the memory 107.
It should be noted that, in a first possible implementation manner of the embodiment of the present application, the gate 105 is a multi-way selection switch.
According to the characteristics of the or gate 102 and the and gate 103, in the control circuit provided in the first embodiment of the present application, before the TPCM106 measures the memory 107, the measurement signal terminal is at a high level, the second input terminal of the or gate 102 is at a high level, at this time, no matter the power switch 101 is in a closed state or an open state, the output of the or gate 102 is at a high level, the control terminal of the bridge 104 is at a high level, the bridge 104 does not guide system initialization, that is, the main board cannot be powered on through the power switch 101, because the TPCM is at a high level at the bit signal terminal, both input terminals of the and gate 103 are at a high level, the output terminal of the and gate 103 is also at a high level, that is, the control terminal of the gate 105 is at a high level, the gate 105 selects the TPCM106 to be turned on with the memory 107, and at this time, the TPCM106 measures the memory 107, after the measurement of the memory 107 is completed, the measurement signal terminal becomes low, the first input terminal of the and gate 103 becomes low, since one input terminal of the and gate 103 is at a low level, the output terminal of the and gate 103 is at a low level, i.e., the control terminal of the gate 105 is at low level, the gate 105 selects the bridge 104 to conduct with the memory 107, at this time, the bridge 104 establishes a connection with the memory 107, since the measurement signal terminal has become low, the second input terminal of the or gate 102 is low, when the power switch 101 is turned on, and the first input terminal of the or gate 102 is at a low level, the output of the or gate 102 is at a low level, i.e. the control terminal of the bridge 104 is at low level, the bridge 104 guides the file in the memory 107 through the connection to initialize the system.
Example two:
referring to fig. 2, the diagram is a schematic structural diagram of another control circuit provided in the embodiment of the present application.
The control circuit that this application embodiment two provided includes: a power switch 201, an or gate 202, a first gate 2051, a second gate 2052, a bridge 204, a first and gate 2031, a second and gate 2032, and a TPCM 206;
a first input terminal of the or gate 202 is connected to the power switch 201;
a second input terminal of the or gate 202 is connected to a bios flash metric signal terminal of the basic input output system memory of the TPCM 206;
the output end of the or gate 202 is connected with the control end of the bridge chip 204;
a first input end of the first and gate 2031 is connected to a BIOS FLASH measurement signal end of the TPCM 206;
a second input terminal of the first and gate 2031 is connected to a TPCM in-place signal terminal of the TPCM 206;
the output end of the first and gate 2031 is connected to the control end of the first gate 2051;
a first input terminal of the second and gate 2032 is connected to a BMCFLASH metric signal terminal of the BMCFLASH control memory of the TPCM 206;
a second input terminal of the second and gate 2032 is connected to a TPCM in-place signal terminal of the TPCM 206;
the output end of the second and gate 2032 is connected to the control end of the second gate 2052;
a first interface of the first gate 2051 is connected with a first interface of the bridge chip 204;
the second interface of the first gate 2051 is connected to the BIOS FLASH 207;
the third interface of the first gate 2051 is connected to the first interface of the TPCM 206;
a first interface of the second gate 2052 is connected with the baseboard management controller BMC 209;
a second interface of the second gate 2052 is connected with a baseboard management control memory BMC FLASH 208;
a third interface of the second gate 2052 is coupled to a second interface of the TPCM 206.
It should be noted that, in the second embodiment of the present application, the power switch 201 is at a low level when closed, and at a high level when open; before the TPCM206 measures the BMC FLASH 208, the BMC FLASH measurement signal end is at a high level, and after the TPCM206 measures the BMC FLASH 208, the BMC FLASH measurement signal end is at a low level; before the TPCM206 measures the BIOS FLASH207, the BIOS FLASH measurement signal terminal is at a high level, and after the TPCM206 measures the BIOS FLASH207, the BIOS FLASH measurement signal terminal is at a low level; in the measurement process, the TPCM206 measures the BMC FLASH 208 first and then measures the bios FLASH 207; when the control terminal of the bridge chip 204 is at a low level, the bridge chip 204 will conduct system initialization; the TPCM is at high level at the bit signal end.
It should be noted that, in the second embodiment of the present application, when the control terminal of the second gate 2052 is at a high level, the second interface and the third interface of the second gate 2052 are turned on, so that the TPCM206 measures the BMC FLASH 208, and when the control terminal of the second gate 2052 is at a low level, the second interface and the first interface of the second gate 2052 are turned on, so that the BMC FLASH 208 guides the BMC 209 to initialize.
It should be noted that, in the second embodiment of the present application, when the control terminal of the first gate 2051 is at a high level, the second interface and the third interface of the first gate 2051 are turned on, so that the TPCM206 measures the BIOS FLASH207, and when the control terminal of the first gate 2051 is at a low level, the second interface and the first interface of the first gate 2051 are turned on, so that the bridge slice 204 boots the system initialization.
It should be noted that, in the second embodiment of the present application, a possible implementation manner is that the first gate 2051 is a first multi-way selection switch, and the second gate 2052 is a second multi-way selection switch.
It should be noted that, referring to fig. 3a, a possible implementation manner in the second embodiment of the present application is that an anode of the first diode D1 is connected to an anode of the second diode D2 to serve as the output end of the first and gate 2031, a cathode of the first diode D1 serves as the first input end of the first and gate 2031, and a cathode of the second diode D2 serves as the second input end of the first and gate 2031.
It should be noted that, referring to fig. 3b, a possible implementation manner in the second embodiment of the present application is that an anode of the third diode D3 is connected to an anode of the fourth diode D4 to serve as an output end of the second and gate 2032, a cathode of the third diode D3 serves as a first input end of the second and gate 2032, and a cathode of the fourth diode D4 serves as a second input end of the second and gate 2032.
According to the characteristics of the or gate 202 and the first and gate 2031 and the second and gate 2032, in the control circuit provided in the second embodiment of the present application, before the TPCM206 measures the BIOS FLASH207, the BIOS FLASH measurement signal end is at a high level, and the second input end of the or gate 202 is at a high level, at this time, no matter the power switch 201 is in a closed state or an open state, the output of the or gate 202 is at a high level, the control end of the bridge 204 is at a high level, and the bridge 204 does not boot system initialization, that is, the main board cannot be powered on through the power switch 201; before the TPCM206 measures the BMC FLASH 208, the BMC FLASH measurement signal end is at a high level, since the TPCM is at a high level at the in-place signal end, both input ends of the second and gate 2032 are at a high level, the output end of the second and gate 2032 is also at a high level, that is, the control end of the second gate 2052 is at a high level, the second gate 2052 selects the TPCM206 to be conducted with the BMC FLASH 208, at this time, the TPCM206 measures the BMC FLASH 208, after the measurement of the BMC FLASH 208 is completed, the BMC FLASH measurement signal end is changed to a low level, the first input end of the second and gate 2032 is at a low level, that is, the control end of the second gate 2032 is at a low level, the second gate 2052 selects the BMC FLASH 208 to be conducted with the BMC 209, to initialize to BMC 209; since both the on-site signal end of the TPCM and the BIOS FLASH measurement signal end are at a high level, both the input ends of the first and gate 2031 are at a high level, the output end of the first and gate 2031 is also at a high level, that is, the control end of the first gate 2051 is at a high level, the first gate 2051 selects the BIOS FLASH207 to be conducted with the TPCM206, at this time, the TPCM206 measures the BIOS FLASH207, after the measurement of the BIOS FLASH207 is completed, the BIOS FLASH measurement signal end is changed to a low level, the first input end of the first and gate 2031 is at a low level, the output end of the first and gate 2031 is also at a low level, that is, the control end of the first gate 2051 is changed to a low level, the first gate 2051 selects the BIOS FLASH207 to be conducted with the bridge 204, at this time, the bridge 204 is connected with the BIOS FLASH207, the second input terminal of the or gate 202 is at a low level, and when the power switch 201 is turned off, and the first input terminal of the or gate 202 is at a low level, the output terminal of the or gate 202 is at a low level, that is, the control terminal of the bridge 204 is at a low level, and the bridge 204 guides the system to initialize.
It should be noted that the TPCM206 preferably measures the BMC FLASH 208, and after the measurement is completed, the TPCM206 measures the BIOS FLASH 207.
The embodiment of the application has the following beneficial effects:
the control circuit replaces a CPLD in the traditional technology, the power-on time sequence of the mainboard is controlled, the production cost is reduced, furthermore, the control circuit does not need software support, and the development cost is reduced.
Example three:
referring to fig. 4, this figure is a schematic structural diagram of a server according to an embodiment of the present application.
The server provided by the third embodiment of the present application includes: a control circuit 401, a memory 402, and a CPU 403.
The control circuit 401 includes any one of the circuits in the first embodiment or the second embodiment of the present application;
the control circuit 401 is configured to control a power-on timing of the memory 402;
the control circuit 401 is also used to direct the CPU 403 to initialize.
It should be noted that the control circuit 401 preferentially powers on the memory 402, measures the memory 402, and after the measurement is completed, directs the control circuit 401 to initialize the CPU 403.
The embodiment of the application has the following beneficial effects:
the power-on time sequence of the mainboard is controlled by the server comprising the control circuit, the CLPD does not need to be installed on the mainboard, the production cost is reduced, and further, the development cost is reduced without software support.
It should be understood that the above-disclosed embodiments are merely preferred embodiments of the invention, and are not intended to limit the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (7)
1. A control circuit, comprising: the system comprises a power switch, an OR gate, an AND gate, a bridge chip and a trusted platform control module TPCM;
the first input end of the OR gate is connected with the power switch; the power switch is at a low level when being switched off and at a high level when being switched off;
the second input end of the OR gate is connected with the measurement signal end of the TPCM; wherein, before said TPCM measures the memorizer, said measurement signal terminal is the high level, after said TPCM measures the memorizer, said measurement signal terminal is the low level;
the output end of the OR gate is connected with the control end of the bridge piece; when the control end of the bridge chip is at a low level, the bridge chip guides the file in the memory to initialize the system;
the first input end of the AND gate is connected with the measurement signal end of the TPCM;
the second input end of the AND gate is connected with a TPCM in-place signal end of the TPCM; wherein, the TPCM is at high level at the bit signal end;
the output end of the AND gate is connected with the control end of the gate;
the first interface of the gate is connected with the first interface of the bridge chip;
the second interface of the gate is connected with the memory;
the third interface of the gate is connected with the first interface of the TPCM.
2. The circuit of claim 1, wherein the and gate comprises: a first AND gate and a second AND gate; the gate includes: a first gate and a second gate;
the first input end of the first AND gate is connected with a basic input output system memory BIOS FLASH measurement signal end of the TPCM;
the first input end of the first AND gate is connected with the second input end of the OR gate;
the second input end of the first AND gate is connected with the TPCM in-place signal end of the TPCM;
the output end of the first AND gate is connected with the control end of the first gate;
the first interface of the first gate is connected with the first interface of the bridge chip;
the second interface of the first gate is connected with the BIOS FLASH;
the third interface of the first gate is connected with the first interface of the TPCM;
the first input end of the second AND gate is connected with a baseboard management control memory BMC FLASH measurement signal end of the TPCM;
a second input end of the second AND gate is connected with the TPCM in-place signal end of the TPCM; the output end of the second AND gate is connected with the control end of the second gate;
a first interface of the second gate is connected with a baseboard management controller BMC;
a second interface of the second gate is connected with the BMC FLASH;
the third interface of the second gate is connected with the second interface of the TPCM; and in the process of measuring the memory by the TPCM, firstly measuring the BMC FLASH and then measuring the BIOS FLASH.
3. The circuit of claim 1, wherein when the control terminal of the gate is at a high level, the second interface and the third interface of the gate are turned on to enable the TPCM to measure the memory;
when the control end of the gate is in a low level, the first interface and the second interface of the gate are conducted, so that the bridge chip is connected with the memory.
4. The circuit of claim 1, wherein the gate is a multiplexing switch.
5. The circuit of claim 2, wherein the first and gate comprises a first diode and a second diode;
and the anode of the first diode is connected with the anode of the second diode to serve as the output end of the first AND gate, the cathode of the first diode serves as the first input end of the first AND gate, and the cathode of the second diode serves as the second input end of the first AND gate.
6. The circuit of claim 2, wherein the second and gate comprises a third diode and a fourth diode;
and the anode of the third diode is connected with the anode of the fourth diode to serve as the output end of the second AND gate, the cathode of the third diode serves as the first input end of the second AND gate, and the cathode of the fourth diode serves as the second input end of the second AND gate.
7. A server comprising the circuitry of any of claims 1-6, and further comprising: a CPU and a memory;
the circuit is used for controlling the power-on time sequence of the memory;
the circuit is also used for guiding the CPU to initialize.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114281890A (en) * | 2021-11-26 | 2022-04-05 | 苏州浪潮智能科技有限公司 | BIOS out-of-band management system and method |
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