CN211906032U - Initialization control circuit and electronic equipment - Google Patents

Abstract

The embodiment of the utility model discloses an initialization control circuit and electronic equipment, the initialization control circuit includes switch, first controller, switch module and second controller; the power switch is electrically connected with the first controller; the first controller is electrically connected with the second controller through the switch module; the first controller controls the switch module to be conducted. The embodiment of the utility model provides a, establish ties switch, first controller, switch module and second controller in proper order, when switch closed, the initialization was first accomplished to first controller to switch on by first controller control switch module, so that the initialization is accomplished to the second controller, thereby realized that first controller and second controller accomplish the purpose of initialization in proper order.

Description

Initialization control circuit and electronic equipment

Technical Field

The embodiment of the utility model provides a relate to computer technology field, especially relate to an initialization control circuit and electronic equipment.

Background

The notebook computer or desktop computer system comprises a plurality of chips, and the initialization sequence of each chip has a great influence on the starting process when the computer is started.

Taking an Embedded Controller (EC) and a Power Management Integrated Circuit (PMIC) as an example, both play important roles in the system, and the EC controls the timing of most important signals during the system startup process, such as the control of a keyboard Controller, a charging indicator light, a fan and other devices, and also controls the states of the system such as standby and sleep. The PMIC is used to manage the power devices in the host system, and plays a crucial role in the system. Fig. 1 is a schematic structural diagram of a conventional initialization control circuit, and as shown in fig. 1, most of the initialization schemes at present are that after a power switch 10 is closed, a low-level boot signal is simultaneously transmitted to EC 3 and PMIC 4 through a zero-ohm resistor 2, so that EC 3 and PMIC 4 are connected in parallel to realize simultaneous initialization.

However, in the scheme of parallel initializing the EC and the PMIC during the boot process, the EC and the PMIC often occupy the bus resource at the same time, and the system cannot arbitrate the priority of the EC and the PMIC, so that the problem of chip code crash occurs.

SUMMERY OF THE UTILITY MODEL

An object of the embodiment of the utility model is to provide an initialization control circuit and electronic equipment to each chip in the system accomplishes the initialization according to certain order when realizing the computer start.

In a first aspect, an embodiment of the present invention provides an initialization control circuit, including a power switch, a first controller, a switch module, and a second controller;

the power switch is electrically connected with the first controller; the first controller is electrically connected with the second controller through the switch module; the first controller controls the switch module to be conducted.

Further, the switch module includes a diode; the cathode of the diode is electrically connected with the output end of the first controller, and the anode of the diode is electrically connected with the input end of the second controller.

Further, the switch module includes a switch chip; the control end of the switch chip is electrically connected with the control end of the first controller, the input end of the switch chip is electrically connected with the output end of the first controller, and the output end of the switch chip is electrically connected with the input end of the second controller.

Further, the switch chip includes a metal-oxide semiconductor Field-Effect Transistor (MOSFET, hereinafter referred to as MOS Transistor); the control end of the MOS tube is the control end of the switch chip; the input end of the MOS tube is the input end of the switch chip; the output end of the MOS tube is the output end of the switch chip.

Further, the switch chip further includes: a first resistor, a second resistor and a comparator;

the first end of the first resistor is electrically connected with the output end of the switch chip, the second end of the first resistor is electrically connected with the first end of the second resistor, and the second end of the second resistor is grounded; the positive input end of the comparator is electrically connected with the second end of the first resistor, the reverse input end of the comparator is electrically connected with the input end of the switch chip, and the output end of the comparator is electrically connected with the control end of the MOS tube.

Further, the switch chip further comprises a first capacitor;

the first end of the first capacitor is electrically connected with the first end of the first resistor, and the second end of the first capacitor is electrically connected with the second end of the first resistor.

Further, the circuit also comprises a third resistor and a second capacitor;

the first end of the third resistor and the first end of the second capacitor are electrically connected with the output end of the switch chip, and the second end of the third resistor and the second end of the second capacitor are electrically connected with the input end of the second controller.

Furthermore, the circuit also comprises a first reserved connecting end of a zero ohm resistor and a second reserved connecting end of the zero ohm resistor;

the first reserved connecting end of the zero-ohm resistor is electrically connected with the power switch;

and the second reserved connecting end of the zero-ohm resistor is electrically connected with the second controller and the switch module respectively.

Further, the first controller includes an EC; the second controller includes a PMIC.

In a second aspect, the embodiment of the present invention further provides an electronic device, which includes the initialization control circuit provided in any one of the above aspects.

The utility model discloses technical scheme is through establishing ties switch, first controller, switch module and second controller in proper order, and when switch closed, the initialization was first accomplished to first controller to switch on by first controller control switch module, so that the initialization is accomplished to the second controller, thereby realize that first controller and second controller accomplish the initialization in proper order.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an initialization control circuit in the prior art;

fig. 2 is a schematic structural diagram of an initialization control circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another initialization control circuit provided in an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another initialization control circuit provided in an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another initialization control circuit provided in the embodiment of the present invention;

fig. 6 is a schematic structural diagram of a compatible initialization control circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 2 is a schematic structural diagram of an initialization control circuit provided by an embodiment of the present invention, as shown in fig. 2, the circuit includes a power switch 10, a first controller 20, a switch module 30 and a second controller 40, the power switch 10 is electrically connected to the first controller 20, the first controller 20 is electrically connected to the second controller 40 through the switch module 30, and the first controller 20 controls the switch module 30 to be turned on.

The power switch 10 is a switch controlled by a power-on key of a computer, the computer can be started by pressing the power-on key, a plurality of controllers (chips) complete initialization in the starting process of the computer, and the first controller 20 and the second controller 40 are taken as examples to illustrate the working mechanism of the initialization control circuit provided by the embodiment of the present invention.

The importance or priority of the first controller 20 is higher than that of the second controller 40, and the priority of the controller can be defined according to manufacturer requirements or chip functions, which is not limited by the embodiment of the present invention. Taking EC and PMIC as an example, if the priority of EC is higher than that of PMIC, EC is the first controller 20 and PMIC is the second controller 40, whereas if the priority of PMIC is higher than EC, PMIC is the first controller 20 and EC is the second controller 40.

It should be noted that EC and PMIC are of high importance in many chips of the system, and therefore, EC and PMIC are used as the first controller 20 and the second controller 40, and the initialization control circuit is also applicable to other chips in the system.

The on and off of the switch module 30 is controlled by the first controller 20, and when the first controller 20 receives a power-on signal of the power switch 10, the switch module 30 is controlled to be turned on to transmit the power-on signal to the second controller 40, so that the second controller 40 completes the initialization. It should be noted that the switch module 30 may be any device known in the art, and the on and off of the device may be determined by the output signal of the first controller 20, which is not limited by the embodiment of the present invention.

The utility model discloses technical scheme is through establishing ties switch, first controller, switch module and second controller in proper order, and when switch closed, the initialization was first accomplished to first controller to by switching on of first controller control switch module, so that the initialization is accomplished to the second controller, thereby realize that first controller and second controller accomplish the initialization in proper order.

Two specific implementations of the initialization control circuit provided by the embodiments of the present invention are described below based on different selections of the switch module 30.

Fig. 3 is a schematic structural diagram of another initialization control circuit provided in the embodiment of the present invention, and the circuit structure shown in fig. 3 is a first implementation manner. Referring to fig. 3, optionally, the switch module 30 includes a diode 310, a cathode of the diode 310 is electrically connected to the output terminal 22 of the first controller 20, and an anode of the diode 310 is electrically connected to the input terminal 41 of the second controller 40.

It can be understood that, since the cathode of the diode 310 is electrically connected to the output terminal 22 of the first controller 20, the input terminal 41 of the second controller 40 can receive the low-level power-on signal only when the output terminal 22 of the first controller 20 outputs the low-level signal, so as to achieve the purpose of initializing the first controller 20 and then initializing the second controller 40. The scheme can meet the requirement of sequentially starting the first controller 20 and the second controller 40 only by adding one diode 310, has extremely low cost, basically does not increase the load of the system, and has higher practicability.

Fig. 4 is a schematic structural diagram of another initialization control circuit provided in an embodiment of the present invention, and the circuit structure shown in fig. 4 is a second implementation manner. Referring to fig. 4, optionally, the switch module 30 includes a switch chip 320, a control terminal 31 of the switch chip 320 is electrically connected to the control terminal 21 of the first controller 20, an input terminal 32 of the switch chip 320 is electrically connected to the output terminal 22 of the first controller 20, and an output terminal 33 of the switch chip 320 is electrically connected to the input terminal 41 of the second controller 40.

Specifically, the first controller 20 controls the switch chip 320, so that after the first controller 20 completes initialization, the input terminal 32 and the output terminal 33 of the switch chip 320 are controlled to be conducted, so that the second controller 40 completes initialization, thereby achieving the purpose of sequentially initializing the first controller 20 and the second controller 40.

With continued reference to fig. 4, optionally, the switch chip 320 includes a MOS transistor; the control end of the MOS tube is the control end of the switch chip; the input end of the MOS tube is the input end of the switch chip; the output end of the MOS tube is the output end of the switch chip. For example, fig. 4 shows a case where the MOS transistor is a PMOS transistor 321, specifically, a gate of the PMOS transistor 321 is electrically connected to the control terminal 31 of the switch chip 320, a source of the PMOS transistor 321 is electrically connected to the input terminal 32 of the switch chip 320, and a drain of the PMOS transistor 321 is electrically connected to the output terminal 33 of the switch chip 320. After the first controller 20 completes initialization, a low level signal may be output to the gate of the PMOS transistor 321 to turn on the source and the drain of the PMOS transistor 321, so as to achieve the purpose of initializing the second controller 40 after the first controller 20 completes initialization.

It should be noted that, in other embodiments, the MOS transistor may also be an NMOS transistor, which is not limited in the embodiment of the present invention.

It should be noted that, in other embodiments, an MOS transistor may be directly used to replace the switch chip 320, so that each functional pin of the MOS transistor is electrically connected to the control end 21 and the output end 22 of the first controller 20 and the input end 41 of the second controller 40, respectively, to implement the corresponding function, and a specific connection manner may refer to fig. 4, which is not described herein again.

It should be noted that the signals output by the switch chip 320 or the MOS transistors are all high level signals, and the initialization start signal (i.e., the power-on signal) of the controller needs to be a low level signal, so that the second controller 40 needs to be designed with related logic circuits, for example, a not gate circuit is designed, and the high level signal transmitted to the input terminal 41 of the second controller 40 is converted into a low level signal, thereby completing the initialization of the second controller 40.

With continued reference to fig. 4, optionally, the switch chip 320 further includes: a first resistor R1, a second resistor R2, and a comparator 322. A first end of the first resistor R1 is electrically connected to the output end 33 of the switch chip 320, a second end of the first resistor R1 is electrically connected to a first end of the second resistor R2, and a second end of the second resistor R2 is grounded; the positive input end of the comparator 322 is electrically connected to the second end of the first resistor R1, the negative input end of the comparator 322 is electrically connected to the input end 32 of the switch chip 320, and the output end of the comparator 322 is electrically connected to the control end of the MOS transistor.

It should be noted that, a short circuit or other fault inside the second controller 40 may cause the level value of the input terminal 41 to be too high, and the input terminal 41 of the second controller 40 is electrically connected to the output terminal 33 of the switch chip 320, when the level value of the input terminal 41 of the second controller 40 is too high and is higher than the level value of the input terminal 32 of the switch chip 320, a current from the second controller 40 to the first controller 20 through the switch chip 320 may occur, and the reverse current may seriously affect the first controller 20, so that the first controller 20 cannot normally operate. Therefore, the level value of the output terminal 33 of the switch chip 320 can be collected through the positive input terminal of the comparator 322, and the level value of the input terminal 32 of the switch chip 320 can be collected through the negative input terminal of the comparator 322, and the level values of the output terminal 33 and the input terminal 32 of the switch chip 320 can be compared. If the level of the output terminal 33 is high, it indicates that the second controller 40 fails, and at this time, the comparator 322 may be used to output a high level signal to control the gate voltage of the PMOS transistor 321 to turn off, thereby protecting the first controller 20. In this embodiment, the switch chip 320 not only can sequentially complete initialization of the first controller 20 and the second controller 40, but also can effectively prevent abnormal voltage and current of the second controller 40 from flowing back to the first controller 20, and when detecting overvoltage and overcurrent of the second controller 40, the input end 32 and the output end 33 of the switch chip 320 are controlled to be disconnected so as to cut off the connection relationship between the second controller 40 and the first controller 20, thereby protecting the first controller 20.

Optionally, the switch chip 320 further includes a first capacitor C1, a first end of the first capacitor C1 is electrically connected to a first end of the first resistor R1, and a second end of the first capacitor C1 is electrically connected to a second end of the first resistor R1.

The first capacitor C1 is arranged, so that the current flowing through the first resistor R1 is more stable, and the level signal acquired by the positive input end of the comparator 322 is more accurate.

Fig. 5 is a schematic structural diagram of another initialization control circuit provided by the embodiment of the present invention, and fig. 5 is a further optimization of the initialization control circuit based on fig. 4. As shown in fig. 5, optionally, the control circuit further includes a third resistor R3 and a second capacitor C2. A first terminal of the third resistor R3 and a first terminal of the second capacitor C2 are electrically connected to the output terminal 33 of the switch chip 320, and a second terminal of the third resistor R3 and a second terminal of the second capacitor C2 are electrically connected to the input terminal 41 of the second controller 40.

The third resistor R3 and the second capacitor C2 form a delay circuit, and the time of delay can be changed by adjusting the sizes of the third resistor R3 and the second capacitor C2. Those skilled in the art can set the sizes of the third resistor R3 and the second capacitor C2 by themselves, which is not limited by the embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a compatible initialization control circuit according to an embodiment of the present invention. As shown in fig. 6, optionally, the circuit further includes a zero-ohm resistor first reserved connection end 51 and a zero-ohm resistor second reserved connection end 52, the zero-ohm resistor first reserved connection end 51 is electrically connected to the power switch 10, and the zero-ohm resistor second reserved connection end 52 is electrically connected to the second controller 40 and the switch module 30, respectively.

In order to meet different initialization sequence requirements, a connecting end of a zero ohm resistor can be reserved. When the first controller 20 and the second controller 40 need to be initialized simultaneously, a zero-ohm resistor can be installed at a reserved position of the circuit board, so that the starting signal is respectively transmitted to the first controller 20 and the second controller 40 according to the direction of the bold dotted line in fig. 6, and the initialization of the first controller 20 and the initialization of the second controller 40 are completed simultaneously; when the first controller 20 and the second controller 40 need to be initialized sequentially, the position of the zero-ohm resistor is left unused, so that the start-up signal is sequentially transmitted to the first controller 20 and the second controller 40 according to the direction of the bold solid line in fig. 6, and the initialization of the two controllers is sequentially completed.

On the basis of the above embodiment, optionally, the first controller 20 includes an EC; the second controller 40 includes a PMIC.

It is understood that with EC as the first controller 20 and PMIC as the second controller 40, initialization of the PMIC after initialization of EC is completed can be achieved by any of the above embodiments.

Furthermore, the embodiment of the utility model provides an electronic equipment is still provided, and this electronic equipment includes the initialization control circuit that the arbitrary embodiment of the aforesaid provided for this electronic equipment each controller when the start is according to the embodiment of the utility model provides an initialization process is accomplished to the initialization control circuit that provides. For example, the electronic device may be a notebook computer, a desktop computer, a tablet computer, or a mobile phone, and the embodiment of the present invention is not limited thereto.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims (10)

1. An initialization control circuit is characterized by comprising a power switch, a first controller, a switch module and a second controller;

the power switch is electrically connected with the first controller; the first controller is electrically connected with the second controller through the switch module; the first controller controls the switch module to be conducted.

2. The initialization control circuit of claim 1, wherein the switching module comprises a diode; the cathode of the diode is electrically connected with the output end of the first controller, and the anode of the diode is electrically connected with the input end of the second controller.

3. The initialization control circuit of claim 1, wherein the switch module comprises a switch chip; the control end of the switch chip is electrically connected with the control end of the first controller, the input end of the switch chip is electrically connected with the output end of the first controller, and the output end of the switch chip is electrically connected with the input end of the second controller.

4. The initialization control circuit of claim 3, wherein the switch chip comprises a metal-oxide-semiconductor field effect transistor;

the control end of the metal-oxide-semiconductor field effect transistor is the control end of the switch chip; the input end of the metal-oxide-semiconductor field effect transistor is the input end of the switch chip; and the output end of the metal-oxide-semiconductor field effect transistor is the output end of the switch chip.

5. The initialization control circuit of claim 4, wherein the switch chip further comprises: a first resistor, a second resistor and a comparator;

the first end of the first resistor is electrically connected with the output end of the switch chip, the second end of the first resistor is electrically connected with the first end of the second resistor, and the second end of the second resistor is grounded; the positive input end of the comparator is electrically connected with the second end of the first resistor, the reverse input end of the comparator is electrically connected with the input end of the switch chip, and the output end of the comparator is electrically connected with the control end of the metal-oxide-semiconductor field effect transistor.

6. The initialization control circuit of claim 5, wherein the switch chip further comprises a first capacitor;

the first end of the first capacitor is electrically connected with the first end of the first resistor, and the second end of the first capacitor is electrically connected with the second end of the first resistor.

7. The initialization control circuit of claim 3, further comprising a third resistor and a second capacitor;

the first end of the third resistor and the first end of the second capacitor are both electrically connected with the output end of the switch chip, and the second end of the third resistor and the second end of the second capacitor are both electrically connected with the input end of the second controller.

8. The initialization control circuit of claim 1, further comprising a zero ohm resistor first reserved connection terminal and a zero ohm resistor second reserved connection terminal;

the first reserved connecting end of the zero-ohm resistor is electrically connected with the power switch;

and the second reserved connecting end of the zero-ohm resistor is electrically connected with the second controller and the switch module respectively.

9. The initialization control circuit of any one of claims 1 to 8, wherein the first controller comprises an embedded controller; the second controller includes a power management integrated circuit.

10. An electronic device, characterized in that it comprises an initialization control circuit according to any one of claims 1 to 9.

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