CN217563319U - Mainboard circuit and circuit system - Google Patents
Mainboard circuit and circuit system Download PDFInfo
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- CN217563319U CN217563319U CN202221656314.3U CN202221656314U CN217563319U CN 217563319 U CN217563319 U CN 217563319U CN 202221656314 U CN202221656314 U CN 202221656314U CN 217563319 U CN217563319 U CN 217563319U
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Abstract
The utility model provides a mainboard circuit and circuit system relates to circuit technical field. The device comprises a central processing unit, a discharge circuit module and a control module; the central processing unit is connected with the power-off control end of the discharge circuit module, and the control module is connected between the central processing unit and the power-off control end of the discharge circuit module; and the central processing unit is used for sending a shutdown signal to the control module, the control module is used for processing the power-on starting signal according to the shutdown signal to obtain a processed power-on starting signal, and sending the processed power-on starting signal to the discharge circuit module so that the discharge circuit module performs discharge operation according to the processed power-on starting signal. Based on central processing unit, the control module that mainboard circuit itself has, combine the circuit module that discharges to discharge and discharge, circuit structure is simpler, still practiced thrift the cost when discharging mainboard circuit.
Description
Technical Field
The utility model relates to the technical field of circuits, particularly, relate to a mainboard circuit and circuit system.
Background
After the motherboard is shut down, the charges stored on the motherboard need to be slowly released by the leakage of the circuit. Such residual electricity is slowly released. If the motherboard is started immediately after shutdown, the power-on time sequence of the central processing unit on the motherboard may not meet the requirement due to the existence of residual power on the motherboard, and the motherboard cannot be started. Therefore, it becomes important to discharge the remaining power on the main board.
In the related art, an additional chip and a control circuit are added, a 555 timer is arranged, and the 555 timer is adopted to release the residual electricity on the mainboard circuit.
However, in the related art, the 555 timer releases the remaining power, an additional chip and a control circuit are required, and the circuit structure is complex and the cost is high.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a mainboard circuit and circuit system to the not enough among the above-mentioned prior art to in solving the correlation technique, through 555 timers release surplus electricity, need increase extra chip and control circuit, the complicated and higher problem of cost of circuit structure.
In order to achieve the above object, the embodiment of the present invention adopts the following technical solutions:
in a first aspect, an embodiment of the present invention provides a motherboard circuit, including: the device comprises a central processing unit, a discharge circuit module and a control module;
the central processing unit is connected with the power-off control end of the discharge circuit module, and the control module is connected between the central processing unit and the power-off control end of the discharge circuit module;
the central processing unit is used for sending a shutdown signal to the control module, the control module is used for processing a power-on starting signal according to the shutdown signal to obtain a processed power-on starting signal, and sending the processed power-on starting signal to the discharge circuit module, so that the discharge circuit module performs discharge operation according to the processed power-on starting signal.
Optionally, the central processing unit is further connected to a reset control end of the discharge circuit module, and the control module is connected between the central processing unit and the reset control end of the discharge circuit module;
the control module is used for sending a reset signal to the central processing unit, carrying out conversion processing on the reset signal to obtain a processed reset signal, and sending the processed reset signal to the discharge circuit module so as to enable the discharge circuit module to discharge according to the processed reset signal.
Optionally, the discharge circuit module includes multiple sets of sub-discharge circuits, a first end of each set of sub-discharge circuit is connected to a corresponding live terminal, a second end of each set of sub-discharge circuit is connected to the power-down control end and the reset control end of the discharge circuit module, and a third end of each set of sub-discharge circuit is grounded.
Optionally, each group of sub-discharge circuits includes: a triode and a resistor;
the base electrode of the triode is respectively connected with the lower electric control end and the reset control end of the discharge circuit module; the collector of the triode is connected with one end of the resistor, and the other end of the resistor is connected with a corresponding electrified terminal; and the emitter of the triode is grounded.
Optionally, the triode is an NPN type triode.
Optionally, the method further includes: a first diode;
the first end of each group of sub-discharge circuits is connected with the cathode of the first diode, and the anode of the first diode is connected with the lower electric control end of the discharge circuit module.
Optionally, the method further includes: a second diode;
the first end of each group of sub-discharge circuits is connected with the cathode of the second diode, and the anode of the second diode is connected with the reset control end of the discharge circuit module.
Optionally, each group of sub-discharge circuits includes: a field effect transistor and a resistor;
the first end of the field effect tube is respectively connected with the power-off control end and the reset control end of the discharge circuit module; the second end of the field effect transistor is connected with one end of the resistor, and the other end of the resistor is connected with a corresponding electrified terminal; and the third end of the field effect transistor is grounded.
Optionally, the control module is an embedded controller or a programmable logic device.
In a second aspect, the embodiment of the present invention further provides a circuit system, including: a power supply and the motherboard circuit of any of the above first aspects; the power supply comprises a central processing unit, a discharge circuit module, a power supply end and a power supply end, wherein the power supply end is used for processing a power-on starting signal, the power supply end is connected between the central processing unit and the power supply end of the discharge circuit module, the power supply end of the power supply is used for obtaining the processed power-on starting signal, and the power supply end of the power supply is used for stopping supplying power to the mainboard circuit according to the processed power-on starting signal.
The utility model has the advantages that: the embodiment of the utility model provides a mainboard circuit, which comprises a central processing unit, a discharge circuit module and a control module; the central processing unit is connected with the power-off control end of the discharge circuit module, and the control module is connected between the central processing unit and the power-off control end of the discharge circuit module; and the central processing unit is used for sending a shutdown signal to the control module, the control module is used for processing the power-on starting signal according to the shutdown signal to obtain a processed power-on starting signal, and sending the processed power-on starting signal to the discharge circuit module so that the discharge circuit module performs discharge operation according to the processed power-on starting signal. Based on the central processing unit and the control module of the mainboard circuit, the discharging circuit module is combined to discharge, the control module processes the power-on starting signal according to the shutdown signal sent by the central processing unit to obtain the processed power-on starting signal, the discharging circuit module can perform discharging operation according to the processed power-on starting signal, a chip and a control circuit corresponding to the 555 timer are not required to be added, the circuit structure is simple, and the cost is saved while the mainboard circuit is discharged.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a motherboard circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a motherboard circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a discharge circuit module according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a discharge circuit module according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a circuit system according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that if the terms "upper", "lower", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is usually arranged when the product of the application is used, the description is only for convenience of describing the application and simplifying the description, but the indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation and operation, and thus, cannot be understood as the limitation of the application.
Furthermore, the terms "first," "second," and the like in the description and in the claims, and in the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
After the motherboard is shut down, the charges stored on the motherboard need to be slowly released by the leakage of the circuit. Such residual electricity is slowly released. If the motherboard is started immediately after shutdown, the power-on time sequence of the central processing unit on the motherboard may not meet the requirement due to the existence of the residual power on the motherboard, and the motherboard cannot be started. Therefore, it becomes important to discharge the remaining power on the main board.
To solve the above technical problems in the related art, an embodiment of the present application provides a motherboard circuit, based on a central processing unit and a control module that the motherboard circuit itself has, a discharge circuit module is combined to discharge, the control module processes a power-on start signal according to a shutdown signal sent by the central processing unit to obtain a processed power-on start signal, the discharge circuit module can perform a discharge operation according to the processed power-on start signal, a chip and a control circuit corresponding to a 555 timer do not need to be added, and when the motherboard circuit is discharged, the cost is also saved.
Fig. 1 is a schematic structural diagram of a motherboard circuit provided in an embodiment of the present application, and as shown in fig. 1, the motherboard circuit may include: a central processing unit 101, a discharge circuit module 102 and a control module 103. The central processing unit 101 may be referred to as a CPU (central processing unit).
The central processing unit 101 is connected to the power-off control terminal of the discharge circuit module 102, and the control module 103 is connected between the central processing unit 101 and the power-off control terminal of the discharge circuit module 102.
In addition, the central processing unit 101 is configured to send a shutdown signal to the control module 103, and the control module 103 is configured to process the power-on start signal according to the shutdown signal to obtain a processed power-on start signal, and send the processed power-on start signal to the discharge circuit module 102, so that the discharge circuit module 102 performs a discharge operation according to the processed power-on start signal.
In some embodiments, after the main board circuit completes the work, the system executes a shutdown action, accordingly, the central processing unit 101 sends a shutdown signal to the control module 103, and the control module 103 obtains the shutdown signal and processes the power-on start signal according to the shutdown signal. For example, the control module 103 may set the power-on start signal to a high level to obtain a processed power-on start signal, that is, the power-on start signal that has been set to the high level.
In addition, the power-ON start signal may be represented as a PS _ ON signal, and may be a power-ON start signal ON a power supply to which the motherboard circuit is connected.
It should be noted that the power down control end of the power supply is connected between the central processing unit 101 and the power down control end of the discharge circuit module 102, the power down control end of the power supply is used for acquiring the processed power-on start signal, the power supply stops supplying power to the motherboard circuit according to the processed power-on start signal, the remaining power still exists on the motherboard circuit, the control module 103 sends the power-on start signal set to the high level to the discharge circuit module 102, and the discharge circuit module 102 performs the discharge operation on the motherboard circuit according to the power-on start signal set to the high level.
To sum up, the embodiment of the present invention provides a motherboard circuit, which includes a central processing unit 101, a discharge circuit module 102 and a control module 103; the central processing unit 101 is connected with the power-off control end of the discharge circuit module 102, and the control module 103 is connected between the central processing unit 101 and the power-off control end of the discharge circuit module 102; the central processing unit 101 is configured to send a shutdown signal to the control module 103, where the control module 103 is configured to process the power-on start signal according to the shutdown signal to obtain a processed power-on start signal, and send the processed power-on start signal to the discharge circuit module 102, so that the discharge circuit module 102 performs a discharge operation according to the processed power-on start signal. Based on the central processing unit 101 and the control module 103 of the main board circuit, the discharging circuit module 102 is combined to discharge, the control module 103 processes the power-on starting signal according to the shutdown signal sent by the central processing unit 101 to obtain the processed power-on starting signal, the discharging circuit module 102 can perform discharging operation according to the processed power-on starting signal, a chip and a control circuit corresponding to the 555 timer are not required to be added, and the cost is saved while the main board circuit is discharged.
Optionally, fig. 2 is a schematic structural diagram of a motherboard circuit provided in an embodiment of the present application, and as shown in fig. 2, the central processing unit 101 is further connected to a reset control end of the discharge circuit module 102, and the control module 103 is connected between the central processing unit 101 and the reset control end of the discharge circuit module 102.
The control module 103 is configured to send a reset signal to the central processing unit 101, convert the reset signal to obtain a processed reset signal, and send the processed reset signal to the discharge circuit module 102, so that the discharge circuit module 102 discharges according to the processed reset signal.
In some embodiments, when a system crash or other system jam occurs in the working process of the motherboard circuit, the control module 103 may send a reset signal to the central processing unit 101, so that the central processing unit 101 resets according to the reset signal; in addition, the control module 103 may further process the reset signal to obtain a processed reset signal, the control module 103 sends the processed reset signal to the discharge circuit module 102, and the discharge circuit module 102 receives the processed reset signal and performs discharge according to the processed reset signal.
The reset signal may be a low-level signal, and the processed reset signal may be a high-level signal.
Wherein the processed reset signal may be represented as a POR _ N signal.
Optionally, fig. 3 is a schematic structural diagram of a discharge circuit module 102 according to an embodiment of the present disclosure, as shown in fig. 3, the discharge circuit module 102 includes a plurality of sets of sub-discharge circuits 1021, a first end of each set of sub-discharge circuits 1021 is connected to a corresponding live terminal, a second end of each set of sub-discharge circuits 1021 is respectively connected to a power-down control end and a reset control end of the discharge circuit module 102, and a third end of each set of sub-discharge circuits 1021 is grounded.
The power-on start signal input by the reset control terminal of the discharge circuit module 102 may be input to each group of sub-discharge circuits 1021, and each group of sub-discharge circuits 1021 may release the remaining power on the connected live terminal according to the power-on start signal.
In addition, a reset signal input by the power-down control terminal of the discharge circuit module 102 may be input to each group of sub-discharge circuits 1021, and each group of sub-discharge circuits 1021 may discharge the remaining power on the connected live terminal according to the reset signal.
Optionally, the plurality of live terminals connected to the plurality of sets of sub-discharge circuits 1021 may be a combination of at least two of the following: vcore terminal, VDDQ terminal, VDDIO terminal, VPP terminal, AVDD _ PLL terminal, VTT terminal, 5v _S0, AVDD _ PEU.
The residual electricity types existing in the respective electrified terminals are different, and the residual electricity types existing in the respective electrified terminals are as follows:
vcore terminal: a core voltage is present;
VDDQ terminal: there is an output buffer supply voltage of the memory chip;
VDDIO terminal: there is a voltage on the power interface of the I/O in the IC;
VPP terminal: there is a word line voltage that powers a DDR (Double Data SDRAM) memory chip;
AVDD _ PLL terminal: a phase-locked loop voltage of the analog circuit power supply is present;
VTT terminal: there is a bus termination voltage;
5v \ u S0 terminal: there is a 5v supply voltage for the 5v supply device operating in the S0 power domain (on state) on the motherboard circuit;
AVDD _ PEU terminal: there is a voltage that powers a PCIE (peripheral component interconnect express) controller.
It should be noted that the residual power at the power-on terminal may be the residual power of the power domains, and the voltage of each power domain may fluctuate dynamically within the operating voltage range, and no specific voltage value is set.
Optionally, fig. 4 is a schematic structural diagram of a discharge circuit module 102 according to an embodiment of the present disclosure, and as shown in fig. 4, each group of sub-discharge circuits 1021 includes: triode, resistance.
The base of the triode is connected with the power-off control end and the reset control end of the discharge circuit module 102 respectively; the collector of the triode is connected with one end of the resistor, and the other end of the resistor is connected with a corresponding live terminal; the emitter of the triode is grounded.
In some embodiments, the resistance may include: r1, R2, R3, R4, R5, R6, R7, R8, R9; the transistor may include: q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9.
As shown in fig. 4, the other ends of the resistors R1 to R9 may be connected to a Vcore terminal, a VDDQ terminal, a VDDIO terminal, a VPP terminal, an AVDD _ PLL terminal, a VTT terminal, a 5v _s0, an AVDD _ PEU, and other live terminals, respectively, which is just an example. The specific live terminal connected to the resistor can be set according to actual requirements, and besides the example live terminal, other live terminals can be also used. The number of sets of the sub-discharge circuits 1021 may be set according to the number of live terminals, and the number of sets of the sub-discharge circuits 1021 may be the same as the number of live terminals.
In this embodiment, the processed reset signal may be a high-level signal, the processed power-on start signal may be a high-level signal, the high-level signal is input to the base of each of the triodes, the collector of each of the triodes is conducted with the emitter, and each of the triodes forms a loop with the ground terminal to perform discharging.
It should be noted that, if the discharging circuit module 102 executes the discharging operation according to the processed power-ON start signal, after the discharging is completed, the PS _ ON signal is always at a high level and waits for the next power-ON. Only when the computer is started up next time, the PS _ ON signal changes to low level, and then all the triodes are closed to finish normal power-ON.
In addition, if the discharging circuit module 102 executes the discharging operation according to the processed reset signal, after the discharging is completed, the control module 103 sends a POR _ N pull-down signal, the POR _ N becomes low level, the base of each triode becomes low level, the collector and the emitter of each triode are closed, and when the power is supplied again, the remaining power of each electrified terminal is released completely, so that the normal power-on time sequence is not influenced, the time for resetting and restarting is also shortened, and the resetting and starting efficiency is improved.
Optionally, the triode is an NPN type triode.
The NPN type triode is formed by clamping a P type semiconductor between two N type semiconductors.
Optionally, as shown in fig. 4, the method further includes: a first diode D1.
The first terminal of each sub-discharge circuit 1021 is connected to the cathode of the first diode D1, and the anode of the first diode D1 is connected to the lower electrical control terminal of the discharge circuit module 102.
It should be noted that the first diode D1 can prevent the processed power-ON start signal from flowing back to affect the reset, and even if the discharging circuit module 102 has a problem, the first diode D1 is set to the low level to set the PS _ ON signal, which will not affect the CPU.
Optionally, as shown in fig. 4, the method further includes: a second diode D2.
The first end of each group of sub-discharge circuits 1021 is connected to the cathode of the second diode D2, and the anode of the second diode D2 is connected to the reset control end of the discharge circuit module 102.
Similarly, the second diode D2 can prevent the backflow of the processed reset signal from affecting the reset, and even if the discharge circuit module 102 has a problem, the second diode D2 sets the POR _ N signal to be at a low level, which does not affect the reset of the CPU.
Optionally, each group of sub-discharge circuits 1021 includes: a field effect transistor and a resistor; the first end of the field effect transistor is respectively connected with the power-off control end and the reset control end of the discharge circuit module 102; the second end of the field effect transistor is connected with one end of the resistor, and the other end of the resistor is connected with a corresponding live terminal; the third end of the field effect transistor is grounded.
The Field Effect Transistor may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS).
Similarly, the number of the field effect transistors and the number of the resistors can be set according to the number of the live terminals, the number of the field effect transistors can be the same as the number of the live terminals needing to release surplus power, and the number of the resistors can be the same as the number of the live terminals needing to release surplus power.
In this embodiment, the processed reset signal may be a high-level signal, the processed power-on start signal may be a high-level signal, the high-level signal is input to each field-effect transistor, each field-effect transistor is turned on, and each field-effect transistor and the ground terminal form a loop to perform discharging.
Optionally, the control module 103 is an Embedded Controller (EC) or a Programmable Logic Device (CPLD).
It should be noted that, if the control module 103 is a programmable logic device, the reset signal may be converted inside the programmable logic device to obtain a processed reset signal; if the control module 103 is an embedded controller, an additional triode or field effect transistor may be provided to convert the reset signal to obtain a processed reset signal.
Optionally, fig. 5 is a schematic structural diagram of a circuit system provided in the embodiment of the present application, and as shown in fig. 5, the circuit system may include: a power supply 104 and the above-mentioned motherboard circuit;
as shown in fig. 5, the power-off control terminal of the power supply 104 is connected between the central processing unit 101 and the power-off control terminal of the discharge circuit module 102, the power-off control terminal of the power supply 104 is configured to obtain the processed power-on start signal, and the power supply terminal of the power supply 104 is configured to stop supplying power to the motherboard circuit according to the processed power-on start signal.
The power source 104 may be an ATX (Advanced Technology eXtended) power source 104, the power source 104 is turned ON when a PS _onsignal is low (less than 1V), the power source 104 supplies power to the motherboard circuit, the power source 104 is turned off when a PS _ ON signal is high (greater than 4.5V), and the power source 104 stops supplying power to the motherboard circuit.
It should be noted that, the central processing unit 101 sends a shutdown signal to the control module 103, the control module 103 obtains the shutdown signal, processes the PS _ ON signal according to the shutdown signal, sets the PS _ ON signal to a high level, and if the PS _ ON signal is the high level, the power supply terminal of the power supply 104 stops supplying power to the motherboard circuit.
In the embodiment of the present application, the power supply 104 may provide three power supplies 104 with different voltage values, such as P12V _ ATX, P5V _ ATX, and P3V3_ ATX, where 0.8V of the core voltage is obtained by converting P12V _ ATX on the PC motherboard through a voltage conversion chip, P5V _ ATX may provide power for some other 5V chips on the motherboard, and P3V3 may provide power for each 3.3V chip.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A motherboard circuit, comprising: the device comprises a central processing unit, a discharge circuit module and a control module;
the central processing unit is connected with the power-off control end of the discharge circuit module, and the control module is connected between the central processing unit and the power-off control end of the discharge circuit module;
the central processing unit is used for sending a shutdown signal to the control module, the control module is used for processing a power-on starting signal according to the shutdown signal to obtain a processed power-on starting signal, and the processed power-on starting signal is sent to the discharge circuit module, so that the discharge circuit module performs discharge operation according to the processed power-on starting signal.
2. The circuit of claim 1, wherein the central processing unit is further connected to a reset control terminal of the discharge circuit module, and the control module is connected between the central processing unit and the reset control terminal of the discharge circuit module;
the control module is used for sending a reset signal to the central processing unit, carrying out conversion processing on the reset signal to obtain a processed reset signal, and sending the processed reset signal to the discharge circuit module so as to enable the discharge circuit module to discharge according to the processed reset signal.
3. The circuit of claim 2, wherein the discharge circuit module comprises a plurality of sets of sub-discharge circuits, a first terminal of each set of sub-discharge circuits is connected to a corresponding live terminal, a second terminal of each set of sub-discharge circuits is respectively connected to the power-down control terminal and the reset control terminal of the discharge circuit module, and a third terminal of each set of sub-discharge circuits is grounded.
4. The circuit of claim 3, wherein each group of sub-discharge circuits comprises: a triode and a resistor;
the base electrode of the triode is respectively connected with the lower electric control end and the reset control end of the discharge circuit module; the collector of the triode is connected with one end of the resistor, and the other end of the resistor is connected with a corresponding electrified terminal; and the emitter of the triode is grounded.
5. The circuit of claim 4, wherein the transistor is an NPN transistor.
6. The circuit of claim 3, further comprising: a first diode;
the first end of each group of sub-discharge circuits is connected with the cathode of the first diode, and the anode of the first diode is connected with the lower electric control end of the discharge circuit module.
7. The circuit of claim 3, further comprising: a second diode;
the first end of each group of sub-discharge circuits is connected with the cathode of the second diode, and the anode of the second diode is connected with the reset control end of the discharge circuit module.
8. The circuit of claim 3, wherein each group of sub-discharge circuits comprises: a field effect transistor and a resistor;
the first end of the field effect tube is respectively connected with the power-off control end and the reset control end of the discharge circuit module; the second end of the field effect transistor is connected with one end of the resistor, and the other end of the resistor is connected with a corresponding electrified terminal; and the third end of the field effect transistor is grounded.
9. The circuit of claim 1, wherein the control module is an embedded controller or a programmable logic device.
10. A circuit system, comprising: a power supply and a motherboard circuit as claimed in any of the preceding claims 1 to 9; the power supply comprises a central processing unit, a discharge circuit module, a power supply end and a power supply end, wherein the power supply end is used for processing a power-on starting signal, the power supply end is connected between the central processing unit and the power supply end of the discharge circuit module, the power supply end of the power supply is used for obtaining the processed power-on starting signal, and the power supply end of the power supply is used for stopping supplying power to the mainboard circuit according to the processed power-on starting signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221656314.3U CN217563319U (en) | 2022-06-28 | 2022-06-28 | Mainboard circuit and circuit system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221656314.3U CN217563319U (en) | 2022-06-28 | 2022-06-28 | Mainboard circuit and circuit system |
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| Publication Number | Publication Date |
|---|---|
| CN217563319U true CN217563319U (en) | 2022-10-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202221656314.3U Active CN217563319U (en) | 2022-06-28 | 2022-06-28 | Mainboard circuit and circuit system |
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| CN (1) | CN217563319U (en) |
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