CN117095729B - Single Pin input control code generation circuit for chip test mode - Google Patents
Single Pin input control code generation circuit for chip test mode Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a single Pin input control code generating circuit for a chip test mode, which comprises a decoding circuit and a shift register which are connected, wherein a series of negative pulse width modulation signals are input into the decoding circuit through a single chip Pin Vpulse and converted into a level signal DATA and a clock control signal CK of the shift register, and mode control codes CT 1-CTN are written into the shift register and used for controlling the test mode control circuit to control a chip to enter different test modes. The decoding circuit of the invention enables one pin of the chip to be used for inputting the negative pulse width modulation signal, generates the data signal and the clock control signal required by the shift register in the test mode control circuit, and saves one chip pin; meanwhile, only a string of negative pulse width modulation signals are input through a single chip pin, the mode control codes can be written into the register, the coding and code sending processes input from the pin are simplified, and the chip testing efficiency is improved.
Description
Technical Field
The invention relates to the technical field of digital integrated circuits, in particular to a single Pin input control code generation circuit for a chip test mode.
Background
After the packaging of the chip is finished, the chip needs to be tested before leaving the factory to judge whether the chip meets the design index requirement. In order to test the packaged chip conveniently, a circuit special for testing mode control is designed at the beginning of chip design and is used for receiving a special mode control code through a chip pin to enter a testing mode different from a normal working mode.
Typically, such special mode control codes are configured using an integrated circuit bus (Inter-Integrated Circuit, I2C) protocol, which requires a start signal, i.e., SCL, to be high, SDA to be changed from high to low, and then a reply signal to be returned via a reply circuit during the time that SCL is high, such that SDA is changed from high to low. This process requires two pins of the chip to be occupied for transmitting data and clock signals, respectively, which is not applicable to chips with a particular shortage of some pin resources. Meanwhile, the I2C circuit is a conventional general protocol, the coding and transmission of the test mode control code are required to follow corresponding specifications, the problem of low coding and code sending modes is solved, and the test efficiency of the chip is affected to a certain extent.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a single Pin input control code generating circuit for a chip test mode, which not only saves chip pins, but also improves the test efficiency of chips.
In order to achieve the technical purpose, the invention adopts the following technical scheme: a single Pin input control code generating circuit for a chip test mode comprises a decoding circuit and a shift register which are connected, wherein a string of negative pulse width modulation signals is input into the decoding circuit through a single chip Pin Vpulse and converted into a level signal DATA and a clock control signal CK of the shift register, and mode control codes CT 1-CTN are written into the shift register and used for controlling the test mode control circuit to control the chip to enter different test modes.
Further, the decoding circuit is composed of a first control signal A1 generating circuit, a second control signal A2 generating circuit, a NAND gate, a first inverter and a D trigger, wherein the input end of the first control signal A1 generating circuit and the input end of the second control signal A2 generating circuit are connected with a single chip pin Vpulse, the output end of the first control signal A1 generating circuit is connected with the first input end A1 of the NAND gate, the output end of the second control signal A2 generating circuit is respectively connected with the second input end A2 of the NAND gate, the clock control signal input end CLK of the D trigger and the input end of the first inverter, the output end of the NAND gate is connected with the RST end of the D trigger, the D end of the D trigger is connected with a digital power source DVDD, and the output end of the D trigger and the output end of the first inverter are connected with the shift register.
Further, the output signal of the output end of the D flip-flop is used as the level signal DATA of the DATA input end of the shift register, and the output signal of the output end of the first inverter is used as the clock control signal CK of the shift register.
Further, the first control signal A1 generation circuit includes: the input end of the first-stage inverter is connected with a single chip pin Vpulse, the output end of the first-stage inverter is respectively connected with one end of the first load capacitor and the input end of the first delay unit, the other end of the first load capacitor is grounded, and the output end of the first delay unit is connected with the first input end A1 of the NAND gate.
Further, the first stage inverter includes: the output end of the first power supply is connected with the input end of the first adjustable current source, the output end of the first adjustable current source is connected with the source electrode of the first PMOS transistor, the grid electrode of the first PMOS transistor and the grid electrode of the first NMOS transistor are connected with a single chip pin Vpulse, the drain electrode of the first PMOS transistor and the drain electrode of the first NMOS transistor are connected with one end of the first load capacitor and the input end of the first delay unit, and the source electrode of the first NMOS transistor is grounded.
Further, the first delay unit is composed of a second inverter and a third inverter which are connected, the input end of the second inverter is respectively connected with the drain electrode of the first PMOS transistor, the drain electrode of the first NMOS transistor and one end of the first load capacitor, and the output end of the third inverter is connected with the first input end A1 of the NAND gate.
Further, the second control signal A2 generation circuit includes: the output end of the second delay unit is respectively connected with the second input end A2 of the NAND gate, the clock control signal input end CLK of the D trigger and the input end of the first inverter.
Further, the second-stage inverter includes: the output end of the second adjustable current source, the grid electrode of the second PMOS transistor and one end of the second load capacitor are connected, the grid electrodes of the second PMOS transistor and the second NMOS transistor are connected with a single chip pin Vpulse, the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor are respectively connected with the other end of the second load capacitor and the input end of the second delay unit, the source electrode of the second NMOS transistor is connected with the input end of the second adjustable current source, and the output end of the second adjustable current source is grounded.
Further, the second delay unit includes a fourth inverter and a fifth inverter, which are connected, wherein an input end of the fourth inverter is connected with a drain electrode of the second PMOS transistor, a drain electrode of the second NMOS transistor, and another end of the second load capacitor, and an output end of the fifth inverter is connected with a second input end A2 of the nand gate, a clock control signal input end CLK of the D flip-flop, and an input end of the first inverter, respectively.
Further, if the width of the inputted negative pulse width modulation signal is smaller than a specific value, writing a mode control code of 1 into the shift register; otherwise, the mode control code is written to the shift register as 0.
Compared with the prior art, the invention has the following beneficial effects: the single Pin input control code generating circuit for the chip test mode enables a negative pulse width modulation signal to be input by adopting one Pin of a chip through designing the pulse width modulation decoding circuit, generates a data signal and a clock control signal required by a shift register in the test mode control circuit, and can realize the code writing function of two chip Pin ports of a data signal input end and a clock control signal input end required by the original technical scheme under the condition of occupying only one Pin of the chip, thereby saving one chip Pin; meanwhile, a mode control code can be written into the register only by inputting a string of negative pulse width modulation signals through a single chip pin, so that the coding and code sending processes input from the pin are simplified, and the chip testing efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a single Pin input control code generating circuit for chip test mode according to the present invention;
FIG. 2 is a schematic diagram of a decoding circuit according to the present invention;
FIG. 3 is a schematic diagram of a first control signal A1 generating circuit according to the present invention;
FIG. 4 is a schematic diagram of a second control signal A2 generating circuit according to the present invention;
FIG. 5 is a functional timing diagram of a decoding circuit according to the present invention.
Detailed Description
The technical scheme of the invention is further explained below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a single Pin input control code generating circuit for a chip test mode according to the present invention, where the single Pin input control code generating circuit includes a decoding circuit 101 and a shift register 102 connected to each other, and in general, the test mode control circuit needs two pins to input a DATA signal and a clock control signal to control writing codes to the shift register. Specifically, if the width of the inputted negative pwm signal is smaller than a specific value, writing a mode control code of 1 into the shift register 102; otherwise, the mode control code is written into the shift register 102 to be 0, so as to control the test mode control circuit 2 to control the chip to enter different test modes.
As shown in fig. 2, the decoding circuit 101 in the present invention is composed of a first control signal A1 generating circuit 201, a second control signal A2 generating circuit 202, a nand gate 203, a first inverter 204 and a D flip-flop 205, wherein the input end of the first control signal A1 generating circuit 201 and the input end of the second control signal A2 generating circuit 202 are connected to a single chip pin Vpulse, the output end of the first control signal A1 generating circuit 201 is connected to the first input end A1 of the nand gate 203, the output end of the second control signal A2 generating circuit 202 is connected to the second input end A2 of the nand gate 203, the clock control signal input end CLK of the D flip-flop 205 and the input end of the first inverter 204, the output end of the nand gate 203 is connected to the RST end of the D flip-flop 205, the D end of the D flip-flop 205 is connected to the digital power source DVDD, the output end of the D flip-flop 205 and the output end of the first inverter 204 are connected to the shift register 102, the output signal of the output end of the D flip-flop 205 is the signal of the DATA input end of the shift register 102, and the output signal of the first inverter 204 is the clock signal of the clock signal 102.
The input signal Vpulse of the decoding circuit 101 is a negative pulse width modulation signal, the control signals A1 and A2 are generated by the first control signal A1 generating circuit 201 and the second control signal A2 generating circuit 202, the control signals A1 and A2 are used for generating the reset control signal of the D flip-flop 205 through the nand gate 203, meanwhile, the control signal A2 is used as the clock control signal of the D flip-flop 205, and the input end D of the D flip-flop 205 always inputs the high level data '1'. The D flip-flop 205 generates the level signal DATA of the shift register 102 by the reset control signal generated by the control signals A1 and A2 and the clock control signal A2 thereof; the control signal A2 generates the clock control signal CK of the shift register 102 via the first inverter 204; the level signal DATA generated by the decoding circuit 101 is written into the shift register 102 by the clock control signal CK.
As shown in fig. 3, the first control signal A1 generating circuit 201 in the present invention includes: the input end of the first-stage inverter is connected with a single chip pin Vpulse, the output end node N1 of the first-stage inverter is respectively connected with one end of the first load capacitor 304 and the input end of the first delay unit, the other end of the first load capacitor 304 is grounded, and the output end of the first delay unit is connected with the first input end A1 of the NAND gate 203.
The first stage inverter includes: the first power supply comprises a first adjustable current source 301, a first PMOS transistor 302, a first NMOS transistor 303 and a first power supply, wherein the output end of the first power supply is connected with the input end of the first adjustable current source 301, the output end of the first adjustable current source 301 is connected with the source electrode of the first PMOS transistor 302, the grid electrodes of the first PMOS transistor 302 and the grid electrode of the first NMOS transistor 303 are connected with a single chip pin Vpulse, the drain electrode of the first PMOS transistor 302 and the drain electrode of the first NMOS transistor 303 are connected with one end of a first load capacitor 304 and the input end of a first delay unit, and the source electrode of the first NMOS transistor 303 is grounded.
The first delay unit is composed of a second inverter 305 and a third inverter 306 which are connected, wherein the input end of the second inverter 305 is respectively connected with the drain electrode of the first PMOS transistor 302, the drain electrode of the first NMOS transistor 303 and one end of the first load capacitor 304, and the output end of the third inverter 306 is connected with the first input end A1 of the nand gate 203.
When the input signal Vpulse of the decoding circuit 101 changes from low level to high level, the output node N1 of the first-stage inverter and the control signal A1 will be instantaneously inverted; when the input signal Vpulse of the decoding circuit 101 changes from high level to low level, the first NMOS transistor 303 is turned off, the first PMOS transistor 302 is turned on, and the first adjustable current source 301 charges the output node N1 of the first stage inverter through the first PMOS transistor 302 during the period Vpulse is low level. Let the charging current of the first adjustable current source 301 be I1, the capacitance of the first load capacitor 304 be C1, and the charging duration be Deltat 1, the voltage V at the output node N1 of the first stage inverter N1 When the duration of the low level, i.e., the charging duration Δt1, is such that the voltage at the output node N1 of the first-stage inverter reaches the inverted voltage of the second inverter 305, =i1·Δt1/C1, the output control signal A1 of the third inverter 306 is inverted from the high level to the low level; otherwise, the voltage of the output control signal A1 of the third inverter 306 is not inverted, and the high level is maintained unchanged. Here, the first control signal generating circuit 201 is configured to generate the first input signal A1 of the nand gate 203, and generate the RST signal of the D flip-flop 205 together with the second control signal A2, so as to finally generate the DATA output signal of the decoding circuit 101.
As shown in fig. 4, the second control signal A2 generating circuit 202 of the present invention includes: the second stage inverter, the second load capacitor 404 and the second delay unit, the second load capacitor is connected to the second stage inverter, the output node N2 of the second stage inverter is connected to the input end of the second delay unit, and the output end of the second delay unit is connected to the second input end A2 of the nand gate 203, the clock control signal input CLK of the D flip-flop 205 and the input end of the first inverter 204, respectively.
The second-stage inverter includes: the second PMOS transistor 401, the second NMOS transistor 402, and the second adjustable current source 403, the output terminal of the second adjustable current source 403, the gate of the second PMOS transistor 401, and one end of the second load capacitor 404 are connected, the gate of the second PMOS transistor 401 and the gate of the second NMOS transistor 402 are all connected to the single chip pin Vpulse, the drain of the second PMOS transistor 401 and the drain of the second NMOS transistor 402 are respectively connected to the other end of the second load capacitor 404 and the input terminal of the second delay unit, the source of the second NMOS transistor 402 is connected to the input terminal of the second adjustable current source 403, and the output terminal of the second adjustable current source 403 is grounded.
The second delay unit includes a fourth inverter 405 and a fifth inverter 406, where the input end of the fourth inverter 405 is connected to the drain of the second PMOS transistor 401, the drain of the second NMOS transistor 402, and the other end of the second load capacitor 404, and the output end of the fifth inverter 406 is connected to the second input end A2 of the nand gate 203, the clock signal input end CLK of the D flip-flop 205, and the input end of the first inverter 204, respectively.
When the input signal Vpulse of the decoding circuit 101 changes from high level to low level, the output node N2 of the second-stage inverter and the control signal A2 are instantaneously inverted; when the input signal Vpulse of the decoding circuit 101 changes from low level to high level, the second PMOS transistor 401 is turned off, the second NMOS transistor 402 is turned on, and the output node N2 of the output second-stage inverter is gradually discharged to low level by the second adjustable current source 403 through the second NMOS transistor 402, so as to implement delay flip of the output control signal A2 of the fifth inverter 406 from high level to low level. Let the discharge current of the second controllable current source 403 be I2, secondThe load capacitor 404 has a capacitance of C2 and a discharge duration of Deltat 2, and the voltage V at the output node N2 of the second inverter stage N2 The inversion delay period from the high level to the low level of the control signal A2 can be controlled by the current value of the second controllable current source 403 and the capacitance value of the second load capacitor 404 under the positive pulse duration, i.e. the discharge duration Δt2, of the input signal Vpulse sufficient to enable the rising edge of the clock control signal CK generated by the decoding circuit 101 to have a sufficient delay with respect to the input signal Vpulse, so as to avoid the error code caused by the inversion of the DATA signal. Here, the second control signal A2 generating circuit is configured to generate the control clock signal of the clock signal input terminal CLK of the D flip-flop 205, the second control signal A2 of the nand gate 203, and the clock control signal CK required by the shift register in the decoding circuit 101.
The decoding operation time sequence of the decoding circuit 101 in the present invention is shown in FIG. 5, wherein 501 represents a narrow negative pulse in Vpulse, and the charging time Deltat 1 of the output node N1 of the first-stage inverter under the action of the first controllable current source 301 is short enough to make the voltage V of the node N1 N1 Reaching the inversion threshold voltage of the second inverter 305, the control signal A1 does not invert during the negative pulse, and maintains a low level; at this time, the output node N2 of the second inverter is slowly discharged by the second controllable current source 403 under the action of a long enough positive pulse after the negative pulse level, so as to generate a positive pulse control signal A2 slightly wider than the Vpulse negative narrow pulse; during this period, the control signals A1 and A2 go through the reset control signal RST of the D flip-flop 205 generated by the nand gate 203 to be at a high level, and at the same time, the input signal of the D flip-flop 205 is always at a high level '1', and the DATA signal becomes at a high level '1' by the rising edge of the control signal A2; meanwhile, CK is an inverted signal outputted from the inverter 204 after A2 passes through, and its rising edge corresponds to the high level of DATA, and the shift register 102 writes DATA '1' under the effect of the rising edge of CK. 502 represents a wide negative pulse 502 in Vpulse, the charging time Δt1 of the output node N1 of the first stage inverter under the action of the first controllable current source 301 is long enough to enable the voltage V of the N1 node N1 Reaching the inversion threshold voltage of the second inverter 305, the control signal A1 is inverted during the negative pulseTurning to a high level and turning to a low level at the rising edge of the wide negative pulse 502, the first control signal A1 generating circuit 201 generates a narrow positive pulse signal A1 during the Vpulse wide pulse; at this time, the output node N2 of the second inverter is slowly discharged by the second controllable current source 403 under the action of the long enough positive pulse after the negative pulse level, and generates a positive pulse control signal A2 slightly wider than the Vpulse wide negative pulse; during this period, the control signals A1 and A2 generate the reset control signal RST of the D flip-flop 205 through the nand gate 203, and during the period when the RST signal is low, the DATA signal is reset to '0'; meanwhile, CK is an inverted signal outputted from the inverter 204 after A2 passes through, and its rising edge corresponds to the low level '0' of DATA, and the shift register 102 writes the DATA '0' under the effect of the rising edge of CK. Thus, under the effect of the Vphase signal, shift register 102 will correspond to writing data are entered 100..1010..1, for test mode control.
The single Pin input control code generating circuit for the chip test mode only occupies one Pin of the chip, so that one chip Pin is saved; meanwhile, a mode control code can be written into the register only by inputting a string of negative pulse width modulation signals through a single chip pin, so that the coding and code sending processes input from the pin are simplified, and the chip testing efficiency is improved.
The above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, and all technical solutions belonging to the concept of the present invention are within the scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (6)
1. A single Pin input control code generation circuit for a chip test mode is characterized by comprising a decoding circuit (101) and a shift register (102) which are connected, wherein a string of negative pulse width modulation signals is input into the decoding circuit (101) through a single chip Pin Vpulse and converted into a level signal DATA and a clock control signal CK of the shift register (102), and mode control codes CT 1-CTN are written into the shift register (102) and used for controlling a test mode control circuit (2) to control a chip to enter different test modes;
the decoding circuit (101) is composed of a first control signal A1 generating circuit (201), a second control signal A2 generating circuit (202), a NAND gate (203), a first inverter (204) and a D trigger (205), wherein the input end of the first control signal A1 generating circuit (201) and the input end of the second control signal A2 generating circuit (202) are connected with a single chip pin Vpulse, the output end of the first control signal A1 generating circuit (201) is connected with the first input end A1 of the NAND gate (203), the output end of the second control signal A2 generating circuit (202) is respectively connected with the second input end A2 of the NAND gate (203), the clock control signal input end CLK of the D trigger (205) and the input end of the first inverter (204), the output end of the NAND gate (203) is connected with the end of the D trigger (205), the D end of the D trigger (205) is connected with a digital DVDD, and the output end of the D trigger (205) and the output end of the first inverter (204) are connected with the shift register (102);
the first control signal A1 generation circuit (201) includes: the input end of the first-stage inverter is connected with a single chip pin Vpulse, the output end of the first-stage inverter is respectively connected with one end of the first load capacitor (304) and the input end of the first delay unit, the other end of the first load capacitor (304) is grounded, and the output end of the first delay unit is connected with the first input end A1 of the NAND gate (203);
the second control signal A2 generation circuit (202) includes: the second-stage inverter, a second load capacitor (404) and a second delay unit, wherein the second load capacitor is connected into the second-stage inverter, the output end of the second-stage inverter is connected with the input end of the second delay unit, and the output end of the second delay unit is respectively connected with the second input end A2 of the NAND gate (203), the clock control signal input end CLK of the D flip-flop (205) and the input end of the first inverter (204);
the second-stage inverter includes: the second PMOS transistor (401), second NMOS transistor (402) and second adjustable current source (403), the output of second adjustable current source (403), the grid of second PMOS transistor (401), the one end of second load electric capacity (404) are connected, the grid of second PMOS transistor (401), the grid of second NMOS transistor (402) all are connected with single chip pin Vpin ulse, the drain electrode of second PMOS transistor (401), the drain electrode of second NMOS transistor (402) are connected with the other end of second load electric capacity (404), the input of second delay element respectively, the source of second NMOS transistor (402) is connected with the input of second adjustable current source (403), the output ground of second adjustable current source (403).
2. A single Pin input control code generating circuit for a chip test mode according to claim 1, wherein the output signal of the output terminal of the D flip-flop (205) is used as the level signal DATA of the DATA input terminal of the shift register (102), and the output signal of the output terminal of the first inverter (204) is used as the clock control signal CK of the shift register (102).
3. The single Pin input control code generation circuit for chip test mode of claim 1, wherein said first stage inverter comprises: the high-voltage power supply comprises a first adjustable current source (301), a first PMOS transistor (302), a first NMOS transistor (303) and a first power supply, wherein the output end of the first power supply is connected with the input end of the first adjustable current source (301), the output end of the first adjustable current source (301) is connected with the source electrode of the first PMOS transistor (302), the grid electrode of the first PMOS transistor (302) and the grid electrode of the first NMOS transistor (303) are both connected with a single chip pin Vpulse, the drain electrode of the first PMOS transistor (302) and the drain electrode of the first NMOS transistor (303) are both connected with one end of a first load capacitor (304) and the input end of a first delay unit, and the source electrode of the first NMOS transistor (303) is grounded.
4. A single Pin input control code generating circuit for chip test mode according to claim 3, wherein the first delay unit is composed of a second inverter (305) and a third inverter (306) connected, the input terminal of the second inverter (305) is connected with the drain electrode of the first PMOS transistor (302), the drain electrode of the first NMOS transistor (303) and one terminal of the first load capacitor (304), respectively, and the output terminal of the third inverter (306) is connected with the first input terminal A1 of the nand gate (203).
5. The single Pin input control code generation circuit for chip test mode according to claim 4, wherein the second delay unit comprises a fourth inverter (405) and a fifth inverter (406) connected, wherein an input terminal of the fourth inverter (405) is connected to a drain of the second PMOS transistor (401), a drain of the second NMOS transistor (402), and another terminal of the second load capacitor (404), respectively, and an output terminal of the fifth inverter (406) is connected to a second input terminal A2 of the nand gate (203), a clock control signal input terminal CLK of the D flip-flop (205), and an input terminal of the first inverter (204), respectively.
6. The single Pin input control code generation circuit for chip test mode according to claim 1, wherein if the width of the inputted negative pwm signal is smaller than a specific value, the mode control code is written into the shift register (102) as 1; otherwise, the mode control code is written to the shift register (102) as 0.
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| CN111835332A (en) * | 2020-06-08 | 2020-10-27 | 上海美仁半导体有限公司 | Programmable chip, unlocking method and household appliance |
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| DE60021705T2 (en) * | 1999-11-29 | 2006-06-01 | Koninklijke Philips Electronics N.V. | METHOD AND INTEGRATED CIRCUIT DESIGNED TO FEED A TEST PATTERN ON AN INDIVIDUAL COMMON TERMINAL |
| US7315585B2 (en) * | 2004-02-11 | 2008-01-01 | Micrel, Inc. | Clock-less serial data interface using a single pin |
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| CN102664608A (en) * | 2010-12-28 | 2012-09-12 | 博通集成电路（上海）有限公司 | Frequency multiplier and frequency multiplication method |
| CN103066985A (en) * | 2012-12-06 | 2013-04-24 | 无锡中星微电子有限公司 | Chip provided with multiplex pin |
| CN111835332A (en) * | 2020-06-08 | 2020-10-27 | 上海美仁半导体有限公司 | Programmable chip, unlocking method and household appliance |
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