CN218729908U - Power-on and power-off time sequence control circuit - Google Patents
Power-on and power-off time sequence control circuit Download PDFInfo
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- CN218729908U CN218729908U CN202222622862.0U CN202222622862U CN218729908U CN 218729908 U CN218729908 U CN 218729908U CN 202222622862 U CN202222622862 U CN 202222622862U CN 218729908 U CN218729908 U CN 218729908U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/30—Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S20/00—Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
- Y04S20/20—End-user application control systems
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Abstract
The embodiment of the application provides a power-on and power-off time sequence control circuit, and solves the technical problem that the power-on and power-off time sequence cannot be accurately controlled in a system with high requirements on the power-on and power-off time sequence. The circuit comprises: a plurality of power chips; the time sequence control chip is used for controlling the power supply sequence of the plurality of power chips; the standby power supply chip is connected with the plurality of power supply chips through a first capacitor and used for supplying power to the plurality of power supply chips; and one end of the voltage monitoring chip is connected with the standby power supply chip, and the other end of the voltage monitoring chip is connected with the time sequence control chip and used for controlling the time sequence control chip to enter a working state. The voltage division circuit is used for delaying to control the system to be powered off when the voltage is lower than the threshold value, and time is provided for storing key data, so that the subsequent operation can have enough time for storing the data, the reliability of the data is improved, and the reliability of the chip is also improved.
Description
Technical Field
The application relates to the field of power electronics, in particular to a power-on and power-off sequential control circuit.
Background
The circuit system of electronic products has more and more complex structure, usually needs to rely on a plurality of power supplies to supply power, and power management technology for ensuring the reliability of system operation develops therewith. The multi-power supply system has high requirement on the reliability of power supply, wherein the power-on time sequence and power-off time sequence control are very important technologies in the multi-power supply system, and directly influence the reliability of starting and shutting down of electronic products. If the power-on time sequence and the power-off time sequence of the multi-power-supply power supply system are not well controlled, system data loss and even damage to circuit components can be caused, and system faults can be caused.
Most of the Power-on and Power-off in the single board design adopt MOS transistors or Power Good pins for time sequence control, however, in a system with high requirements on the Power-on and Power-off time sequence, such as an SSD Power supply time sequence system, the method may have the technical problem that the Power-on and Power-off time sequence cannot be accurately controlled, so that the system cannot meet the chip requirements.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a power-on and power-off time sequence control circuit, and solves the technical problem that the power-on and power-off time sequence cannot be accurately controlled in a system with high requirements on the power-on and power-off time sequence.
The embodiment of the application provides a power-on and power-off sequential control circuit, the circuit includes: a plurality of power chips;
the time sequence control chip is used for controlling the power supply sequence of the plurality of power chips;
and the standby power supply chip is connected with the plurality of power supply chips through the first capacitor and is used for supplying power to the plurality of power supply chips.
In an implementation manner of the present application, the circuit further includes a voltage monitoring chip, one end of the voltage monitoring chip is connected to the standby power supply chip, and the other end of the voltage monitoring chip is connected to the timing control chip, so as to control the timing control chip to enter a working state.
In an implementation manner of the present application, the standby power supply chip is connected to the SENSE pin of the voltage monitoring chip through a first resistor, a first end of the first resistor is connected to the positive electrode of the first capacitor, a second end of the first resistor is connected to a first end of the second resistor, and a second end of the second resistor is connected to the negative electrode of the first capacitor.
In one implementation manner of the present application, the voltage monitoring chip is connected to the second capacitor through a CT pin.
In an implementation manner of the present application, the delay time of the voltage monitoring chip is 1.25ms to 10s.
In an implementation manner of the present application, the standby power chip is connected to a first end of the third resistor, a second end of the third resistor is connected to an input end of the first power chip, and a second end of the third resistor is connected to the fourth resistor.
In an implementation manner of the present application, the output end of the timing control chip is connected to the second power chip, the third power chip, and the fourth power chip, respectively.
In an implementation of the present application, the model of the standby power chip is SY72001.
In one implementation of the present application, the model of the timing control chip is LM3880MFE-1AE.
In one implementation manner of the present application, the model of the voltage monitoring chip is TPS3808.
The embodiment of the application provides a power-on and power-off time sequence control circuit can carry out accurate control to power-on and power-off time sequences, carry out the mode of supplying power through setting up the electric capacity, carry out down electronic work again after standby capacitor voltage drops to a definite value, use bleeder circuit to carry out delay control and begin to give the system power-off when voltage is less than the threshold value, provide time for key data storage, so that follow-up operation can have sufficient time to carry out data storage, after the completion of storage, carry out power-off according to the order, make the system power-off satisfy the chip manual requirement, the reliability that has improved data has also improved the reliability of chip. The power-off time sequence is accurately controlled through the chip, and the data reliability and the system reliability of the SSD are improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a circuit diagram of a power-on/power-off timing control circuit according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The circuit system of electronic products has more and more complex structure, and usually needs to rely on a plurality of power supplies to supply power, and power management technology is developed to ensure the reliability of system operation. The multi-power supply system has high requirement on the reliability of power supply, wherein the power-on time sequence and power-off time sequence control are very important technologies in the multi-power supply system, and directly influence the reliability of starting and shutting down of electronic products. If the power-on time sequence and the power-off time sequence of the multi-power-supply power supply system are not well controlled, system data loss and even damage to circuit components can be caused, and system faults can be caused.
Most of the Power-on and Power-off circuits in the single board design adopt MOS (metal oxide semiconductor) tubes or Power Good pins for time sequence control, however, in a system with high requirements on the Power-on and Power-off time sequence, such as an SSD (solid state drive) Power supply time sequence system, the method may have the technical problem that the Power-on and Power-off time sequence cannot be accurately controlled, so that the system cannot meet the chip requirements.
In view of the above technical problems, an embodiment of the present application provides a power-on/power-off timing control circuit, which solves the technical problem that a power-on/power-off timing cannot be accurately controlled in a system with a high requirement on the power-on/power-off timing.
The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
The embodiment of the application provides a power-on and power-off sequential control circuit, as shown in fig. 1, the circuit mainly comprises: a plurality of power chips;
the time sequence control chip is used for controlling the power supply sequence of the plurality of power chips;
and the standby power supply chip is connected with the plurality of power supply chips through the first capacitor and is used for supplying power to the plurality of power supply chips.
In this application embodiment, the circuit still includes the voltage monitoring chip, voltage monitoring chip one end with be equipped with the electric power chip and connect, the other end with the sequential control chip is connected, is used for control the sequential control chip gets into operating condition.
In this embodiment of the application, the standby power supply chip is connected to the SENSE pin of the voltage monitoring chip through a first resistor, a first end of the first resistor is connected to the positive electrode of the first capacitor, a second end of the first resistor is connected to a first end of the second resistor, and a second end of the second resistor is connected to the negative electrode of the first capacitor.
In the embodiment of the present application, the voltage monitoring chip is connected to the second capacitor through the CT pin.
In the embodiment of the application, the delay time of the voltage monitoring chip is 1.25 ms-10 s. The delay time is obtained by calculating a second capacitor of the CT pin, and the calculation formula is CT (nF) = [ tD(s) -0.5x10 -3 (s)]×175。
In this embodiment, the standby power supply chip is connected to a first end of a third resistor, a second end of the third resistor is connected to an input end of the first power supply chip, and a second end of the third resistor is connected to a fourth resistor.
In the embodiment of the application, the output end of the timing control chip is respectively connected with the second power supply chip, the third power supply chip and the fourth power supply chip.
In the embodiment of the application, the model of the standby power supply chip is SY72001.
In the embodiment of the application, the model of the timing control chip is LM3880MFE-1AE.
In the embodiment of the application, the model of the voltage monitoring chip is TPS3808.
The embodiment of the application provides a power-on and power-off sequential control circuit, its theory of operation mainly does: the power supply respectively charges a first power supply chip, a second power supply chip, a third power supply chip, a fourth power supply chip and a first capacitor after passing through a standby power supply chip SY72001 with a standby power function, the enabling EN0 of the first power supply chip is directly obtained by dividing the input voltage of the power supply, so that the power supply is firstly powered on, and the power supply is supplied to a voltage monitoring chip TPS3808 with a time delay function and a time sequence control chip LM3880MFE-1AE after the power supply chip is powered on. The voltage monitoring chip monitors that the partial voltage of the first capacitor on the second resistor reaches a threshold value through the SENSE pin and then delays t after the partial voltage reaches the threshold value D And setting the RESET _ L to be high, starting the time sequence control chip to work at the moment, and enabling EN1, EN2 and EN3 respectively in sequence, so that the power-on sequence of the whole system is as follows: input power → first power chip → second power chip → third power chip → fourth power chip.
On the contrary, when the input power supply is disconnected, the first capacitor starts to work, the whole system is powered by the first capacitor, when the voltage of the first capacitor is lower than the SENSE pin threshold value of the voltage monitoring chip TPS3808, RESET _ L is set low at this time, the timing control chip starts to perform power-down operation in sequence, and when the voltage is further reduced, the first power supply chip is powered down last, so that the power-down timing of the whole system is: the fourth power supply chip → the third power supply chip → the second power supply chip → the first power supply chip. In the embodiment of the present application, as shown in fig. 1, the dotted line portion is a path of a power supply direct input mode, and the solid line portion is a path of an enable mode. When the power supply chip is powered on, if the power supply chip wants to output power, the power supply chip can input power supply only by opening the enable, and then the power supply can be output, otherwise, the power supply cannot be output.
The utility model provides a go up electric chronogenesis control circuit can carry out accurate control to going up electric chronogenesis, the mode of supplying power through setting up the electric capacity, carry out electronic work down after reserve electricity electric capacity voltage drops to a definite value again, use bleeder circuit to carry out delay control and begin to give the system power down when voltage is less than the threshold value, provide time for key data preservation, so that follow-up operation can have sufficient time to carry out data preservation, after the preservation is accomplished, carry out power down according to the order, make the system power down satisfy the chip manual requirement, the reliability that has improved data has also improved the reliability of chip. The power-off time sequence is accurately controlled through the chip, and the data reliability and the system reliability of the SSD are improved.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A power-up and power-down timing control circuit, the circuit comprising:
a plurality of power chips;
the time sequence control chip is used for controlling the power supply sequence of the plurality of power chips;
and the standby power supply chip is connected with the plurality of power supply chips through the first capacitor and is used for supplying power to the plurality of power supply chips.
2. The power-on and power-off timing control circuit according to claim 1, further comprising a voltage monitoring chip, wherein one end of the voltage monitoring chip is connected to the standby power supply chip, and the other end of the voltage monitoring chip is connected to the timing control chip, for controlling the timing control chip to enter an operating state.
3. The power-on and power-off timing control circuit according to claim 2, wherein the standby power supply chip is connected to a SENSE pin of the voltage monitoring chip through a first resistor, a first end of the first resistor is connected to an anode of the first capacitor, a second end of the first resistor is connected to a first end of a second resistor, and a second end of the second resistor is connected to a cathode of the first capacitor.
4. The power-on and power-off timing control circuit as claimed in claim 2, wherein the voltage monitoring chip is connected to the second capacitor through a CT pin.
5. The power-on and power-off sequence control circuit as claimed in claim 2, wherein the delay time of the voltage monitoring chip is 1.25 ms-10 s.
6. The power-on and power-off timing control circuit of claim 1, wherein the standby power supply chip is connected to a first end of a third resistor, a second end of the third resistor is connected to the input end of the first power supply chip, and a second end of the third resistor is connected to a fourth resistor.
7. The power-on and power-off timing control circuit of claim 1, wherein the output end of the timing control chip is connected to the second power supply chip, the third power supply chip and the fourth power supply chip respectively.
8. The power-on and power-off sequence control circuit according to claim 1, wherein the model of the standby power supply chip is SY72001.
9. The power-on and power-off timing control circuit as claimed in claim 1, wherein the timing control chip is LM3880MFE-1AE.
10. The power-on and power-off sequential control circuit as claimed in claim 2, wherein the model of the voltage monitoring chip is TPS3808.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222622862.0U CN218729908U (en) | 2022-09-30 | 2022-09-30 | Power-on and power-off time sequence control circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202222622862.0U CN218729908U (en) | 2022-09-30 | 2022-09-30 | Power-on and power-off time sequence control circuit |
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| CN218729908U true CN218729908U (en) | 2023-03-24 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116388559A (en) * | 2023-05-31 | 2023-07-04 | 昆山迈致治具科技有限公司 | Power supply control circuit and FPGA chip |
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- 2022-09-30 CN CN202222622862.0U patent/CN218729908U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116388559A (en) * | 2023-05-31 | 2023-07-04 | 昆山迈致治具科技有限公司 | Power supply control circuit and FPGA chip |
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