CN102346529B - Power supply control circuit - Google Patents
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- CN102346529B CN102346529B CN201010249798.5A CN201010249798A CN102346529B CN 102346529 B CN102346529 B CN 102346529B CN 201010249798 A CN201010249798 A CN 201010249798A CN 102346529 B CN102346529 B CN 102346529B
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Abstract
The invention discloses a power supply control circuit for a mainboard, which comprises a first discharge switch unit, a power supply switch unit and a control unit, wherein the control unit delays the system voltage for generating judgment voltage, the control unit conducts the first discharge switch unit for discharging a first power supply end when the voltage is judged to be lower than the first preset voltage, and the control unit conducts the power supply switch unit for supplying the electricity for the first power supply end when the voltage is judged to be higher than the second preset voltage, wherein the second preset voltage is higher than the first preset voltage.
Description
Technical field
The invention relates to a kind of power control circuit, and particularly relevant for a kind of power control circuit to the electric discharge of mainboard standby voltage end in advance.
Background technology
Advanced technology expansion (Advanced Technology Extended is called for short ATX) mainboard specification is formulated in nineteen ninety-five by Intel company.At present most power supply units is all to use ATX specification, and wherein ATX connector the most often uses two kinds of 20Pin and 24Pin, all comprises the pin of standby voltage (SB5V).Chipset on mainboard, comprise that south bridge is used standby voltage as operating power sometimes, but the discharge time of the standby voltage (SB5V) of exporting because of power supply unit may be different, the standby voltage (SB3V) that therefore causes supplying with south bridge is also different discharge time.
Chip in mainboard (for example South Bridge chip) discharges when incomplete, voltage that power supply unit provides may cause chip to produce abnormal occurrence, not only cannot bring into play thus the function of reinforcement, more can cause the whole system cannot normal operation, even cannot start shooting.In addition,, before system boot completes, standby voltage (SB3V and SB5V) can cause power consumption, produces extra unnecessary power consumption.
Summary of the invention
The invention provides a kind of power control circuit, can to the standby voltage end of mainboard, discharge to prevent the electric discharge of standby voltage end not exclusively to cause mainboard to produce abnormal occurrence in advance.
The present invention proposes a kind of power control circuit, is applicable to a mainboard, and power control circuit comprises the first discharge switching element, power switch unit and control module.Wherein, the first discharge switching element is coupled between the first power end and ground connection.Power switch unit is coupled between system voltage and the first power end.Control module is coupled between the first discharge switching element and power switch unit, and controls the first discharge switching element and power switch unit according to the change in voltage of system voltage.Wherein, control module delay system voltage is to produce a judgement voltage, when judgement voltage is less than first predeterminated voltage, control module conducting the first discharge switching element is to discharge to the first power end, when judgement voltage is greater than the second predeterminated voltage, control module conducting power switch unit is to power to the first power end, and wherein the second predeterminated voltage is greater than the first predeterminated voltage.
In one embodiment of this invention, the first above-mentioned discharge switching element comprises the first fictitious load and a PMOS transistor.The first fictitious load couples the first power end, and the transistorized source terminal of a PMOS and drain electrode end couple respectively the first fictitious load and ground connection, and the transistorized grid of a PMOS is coupled to control module.
In one embodiment of this invention, power control circuit more comprises the second discharge switching element, it is coupled between second source end and ground connection, and be controlled by control module, when judgement voltage is less than the first predeterminated voltage, control module conducting the second discharge switching element is so that second source end is discharged, and when judgement voltage is greater than the first predeterminated voltage, control module is closed the second discharge switching element.
In one embodiment of this invention, above-mentioned second discharge switching element the second fictitious load and the 2nd PMOS transistor.Wherein, the second fictitious load couples second source end, and the transistorized source terminal of the 2nd PMOS and drain electrode end couple respectively the second fictitious load and ground connection, and the transistorized grid of a PMOS is coupled to control module.
In one embodiment of this invention, above-mentioned power switch unit comprises the 3rd PMOS transistor, and its source terminal and drain electrode end be coupling system voltage and the first power end respectively, and the transistorized grid of the 3rd PMOS is coupled in control module.
In one embodiment of this invention, when judgement voltage is greater than the first predeterminated voltage, control module is closed the first discharge switching element.
In one embodiment of this invention, above-mentioned control module comprises the first comparing unit, push-pull circuit, delay cell, the second comparing unit and the 3rd comparing unit.The first comparing unit is in order to comparison system voltage and a reference voltage.Push-pull circuit is coupled to the first comparing unit and system voltage, when system voltage is greater than reference voltage, and push-pull circuit output system voltage.Delay cell is coupled to the output of push-pull circuit, in order to delay system voltage, to produce, judges voltage.The second comparing unit, couples delay cell and the first discharge switching element, according to the comparative result of judgement voltage and the first predeterminated voltage, controls the first discharge switching element.In addition, the 3rd comparing unit is coupled to and connects delay cell and power switch unit, according to the comparative result of judgement voltage and the second predeterminated voltage, controls power switch unit.
In one embodiment of this invention, the first above-mentioned comparing unit comprises the first resistance, the second resistance and the first operational amplifier.The second resistance and the first resistance are serially connected with between cell voltage and ground connection, with dividing potential drop cell voltage, produce reference voltage.The positive input terminal coupling system voltage of the first operational amplifier, its negative input end couples the common joint of the first resistance and the second resistance.
In one embodiment of this invention, above-mentioned push-pull circuit comprises nmos pass transistor and the 4th PMOS transistor.The drain electrode end coupling system voltage of nmos pass transistor wherein, its gate terminal is coupled to the output terminal of the first operational amplifier, and its source terminal is as the output terminal of push-pull circuit and couple resistance.In addition, the transistorized source terminal of the 4th PMOS couples the source terminal of nmos pass transistor, and the transistorized drain electrode end of the 4th PMOS couples ground connection, and the transistorized grid of the 4th PMOS is coupled to the output terminal of the first operational amplifier.
In one embodiment of this invention, above-mentioned delay cell comprises resistance and electric capacity.One end of resistance is coupled to the output of push-pull circuit, and electric capacity is coupled between the other end and ground connection of resistance.
In one embodiment of this invention, above-mentioned delay cell more comprises a diode, and the anode tap of diode couples the common joint of resistance and electric capacity, and the cathode terminal of diode couples the output of push-pull circuit.
In one embodiment of this invention, the second above-mentioned comparing unit comprises the 3rd resistance, the 4th resistance and the second operational amplifier.Wherein the 3rd resistance and the 4th resistance are serially connected with between reference voltage and ground connection, with dividing potential drop reference voltage, produce the first predeterminated voltage.The positive input terminal of the second operational amplifier couples delay cell to receive judgement voltage, the negative input end of the second operational amplifier couples the common joint of the 3rd resistance and the 4th resistance, and the output terminal of the second operational amplifier sees through the 5th resistance and is coupled to the transistorized grid of a PMOS.
In one embodiment of this invention, the 3rd above-mentioned comparing unit comprises the 6th resistance, the 7th resistance and the 3rd operational amplifier.The 6th resistance and the 7th resistance are serially connected with between system voltage and ground connection, with voltage divider system voltage, produce the second predeterminated voltage.The positive input terminal of the 3rd operational amplifier couples the common joint of the 6th resistance and the 7th resistance, and the negative input end of the 3rd operational amplifier couples judgement voltage, and the output terminal of the 3rd operational amplifier sees through the 8th resistance and is coupled to the transistorized grid of the 3rd PMOS.
In one embodiment of this invention, above-mentioned reference voltage equals the first predeterminated voltage.
Based on above-mentioned, the present invention utilizes the comparative result of judgement voltage that control module produces and the first predeterminated voltage, the second predeterminated voltage, come in advance the power end of standby voltage to be discharged, and power end is powered, so that the standby voltage of chip is powered after reaching completely electric discharge again on supply computer motherboard, avoid the remaining voltage of standby voltage to make element relevant to standby voltage in mainboard produce abnormal occurrence.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the power module system figure according to the computing machine of one embodiment of the invention.
Fig. 2 is the calcspar according to the power control circuit of another embodiment of the present invention.
Fig. 3 is the calcspar according to the power control circuit of another embodiment of the present invention.
Fig. 4 is the change in voltage sequential chart according to the power control circuit of Fig. 3 embodiment.
Embodiment
Elaborate below with reference to the accompanying drawings embodiments of the invention, accompanying drawing for example understands example embodiment of the present invention, wherein same the or similar element of same numeral indication.
In notebook, its power module or power supply unit can be converted to various system voltages by AC power or battery supply, such as 3V, 5V, 12V etc., wherein system voltage comprises standby voltage, can be for the circuit on mainboard or South Bridge chip such as SB3V, SB5V etc.If not exclusively can affect the system normal operation of rear end because standby voltage SB3V, SB5V discharge, cause the problems such as South Bridge chip mistake start to produce.Therefore, the power control circuit of the present embodiment may produce the problem proposition settling mode that electric discharge not exclusively affects system normal operation in shutdown afterwards for various system voltages.
Please refer to Fig. 1, Fig. 1 is the power module system figure according to the computing machine of one embodiment of the invention.Power module comprises power supply changeover device (adapter) 108, the first voltage conversion circuit 110, power control circuit 100, second voltage converter 112.Power supply changeover device 108 is used for transmitting voltage source to the first voltage conversion circuit 110, the first voltage conversion circuit 110 can be by power conversion system voltage SB5V-IN, and then required standby voltage SB5V and the SB3V of the system that is converted to, the end points of output standby voltage SB5V is called the first power end OUT1, and output standby voltage SB3V is called second source end OUT2.Wherein, standby voltage SB3V can obtain via 112 pairs of standby voltage SB5V dividing potential drops of second voltage change-over circuit.Power control circuit 100 is integrated in power module system, is used for the first power end OUT1, second source end OUT2 to power and the operation such as electric discharge, to prevent that standby voltage SB3V, SB5V from producing the incomplete problem of discharging after shutdown.
First delay system voltage SB5V-IN is to produce a judgement voltage VE in control module 102 meeting.When judgement voltage VE is less than first predeterminated voltage, control module 102 conducting the first discharge switching elements 104 and the second discharge switching element 116 are to discharge to the first power end OUT1 and second source end OUT2.For example, when judgement voltage VE is greater than the first predeterminated voltage (3V), control module 102 can be closed the first discharge switching element 104 and the second discharge switching element 116.For example, when judgement voltage VE is greater than one second predeterminated voltage (4V), control module meeting conducting power switch unit 106 is to power to the first power end OUT1.Power module produces corresponding voltage according to system voltage SB5V-IN and uses to host computer system.
By above-mentioned discharge flow path, can make standby voltage SB5V or SB3V that the chip (for example south bridge) in host computer system 114 receives reach electric discharge completely, avoid the remaining voltage on standby voltage to make the related elements in host computer system 114 produce abnormal occurrence.For example the CMOS time of host computer system 114 is not expectedly eliminated.Wherein, the second predeterminated voltage is greater than the first predeterminated voltage.That is to say, in the process rising at system voltage SB5V-IN, power control circuit 100 can first discharge by the first discharge switching element 104,116 couples of the first power end OUT1 of the second discharge switching element and second source end OUT2, and when system voltage SB5V-IN reaches the first predeterminated voltage, stops electric discharge; Then when being greater than the second predeterminated voltage, system voltage SB5V-IN just by 106 pairs of power switch unit the first power end OUT1 and second source end OUT2, charges to draw high the magnitude of voltage of standby voltage SB5V or SB3V.
It should be noted that, above-mentioned output terminal of take standby voltage SB5V, SB3V illustrates the technological means of the present embodiment as example, so the present embodiment is not limited to the output terminal of standby voltage SB5V, SB3V, also can use merely at the output terminal of standby voltage SB5V or the output terminal of standby voltage SB3V, as long as select corresponding discharge switching element applicable to the output terminal of a certain group of standby voltage; Can be applied to other power end, and applied output terminal number is also not limited, as long as increase corresponding discharge switching element applicable to the output terminals of many group standby voltages, draws high again its magnitude of voltage after it is discharged completely yet.
Next, further illustrate power control circuit, please refer to Fig. 2, Fig. 2 is the calcspar according to the power control circuit of another embodiment of the present invention.Power control circuit 100 comprises control module 102, the first discharge switch 104, the second discharge switch 116 and power switch unit 106, and wherein control module 102 more comprises one first comparing unit 202, one second comparing unit 204, one the 3rd comparing unit 206, a delay cell 210 and a push-pull circuit 208.The first comparing unit 202 is coupled to push-pull circuit 208, and delay cell 210 is coupled between push-pull circuit 208 and the second comparing unit 204, the 3rd comparing unit 206.
The first comparing unit 202 is coupled between system voltage SB5V-IN and ground connection GND, and according to the variation of system voltage SB5V-IN, controls the output of push-pull circuit 208.When system voltage SB5V-IN is greater than a reference voltage, system voltage SB5V-IN exports the delay cell 210 of rear end to via push-pull circuit 208.Delay cell 210 couples the output terminal of push-pull circuit 208, is used for postponing system voltage SB5V-IN that push-pull circuit 208 exports to produce judgement voltage VE.Can determine the time delay of delay cell 210 according to design requirement, 0.5 tip of a twig for example, and the circuit structure of delay cell 210 is for example RC delay circuit structure.Whether, the 3rd 206 of comparing units judge that conducting that the change in voltage of voltage VE controls power switch 106 whether in the conducting that the second comparing unit 204 can be controlled the first discharge switch 104 and the second discharge switch 116 according to the change in voltage of judgement voltage VE.
When judgement voltage VE is less than the first predeterminated voltage, the second comparing unit 204 meeting conducting the first discharge switching element 104 and the second discharge switching elements 116, to discharge to the first power end OUT1 and second source end OUT2 respectively.When judgement voltage VE is greater than the first predeterminated voltage, the second comparing unit 204 can be closed the first discharge switching element 104 and the second discharge switching element 116.While being greater than the second predeterminated voltage when judgement voltage VE continuation rising, the 3rd comparing unit 206 meeting conducting power switch unit 106, allow system voltage SB5V-IN the first power end SB5V and second source end SB3V be powered to offer the system of rear end, as south bridge is used.Wherein, the second predeterminated voltage is greater than the first predeterminated voltage.That is to say, power control circuit 100 can first discharge to the first power end OUT1 and second source end OUT2, and then draws high its magnitude of voltage.
Next, further illustrate the circuit structure in above-mentioned power control circuit 100, please refer to Fig. 3 is the circuit diagram according to the power control circuit of the present embodiment.Fig. 4 is the change in voltage sequential chart according to the power control circuit of Fig. 3 embodiment.Referring to Fig. 3 and Fig. 4, the first comparing unit 202 comprises resistance R 1, R2 and operational amplifier 302.Wherein resistance R 1, R2 are serially connected with between a cell voltage VBAT and ground connection GND, in order to dividing potential drop cell voltage VBAT to produce above-mentioned reference voltage on the common joint in resistance R 1, R2.Cell voltage VBAT is for example the cell voltage on mainboard, and reference voltage is for example 3V.The positive and negative input end of operational amplifier 302 is coupling system voltage SB5V-IN and reference voltage (3V) respectively, in order to the size of comparison system voltage SB5V-IN and reference voltage.
Push-pull circuit 208 is by NMOS (N channel metal oxide semiconductor transistor, be called for short NMOS) transistor M1 and PMOS (P channel metal oxide semiconductor transistor, abbreviation PMOS) transistor Q1 composes in series, and its grid is all connected in the output of computing comparer 302.Delay cell 210 is comprised of resistance R 9, capacitor C and diode D1, and resistance R 9 and capacitor C coupled in series are between the output and ground connection GND of push-pull circuit 208, and diode D1 is in parallel with resistance R 9.Wherein, resistance R 9 judges voltage VE with the shared contact output of capacitor C.Delay cell 210 is mainly to postpone by RC circuit the system voltage SB5C-IN that push-pull circuit 208 is exported, and allows by this first power end OUT1 of rear end and second source end OUT2 have the longer time to discharge the in the situation that of power connector plug suddenly.
The second comparing unit 204 is comprised of resistance R 3, R4 and operational amplifier 304, and resistance R 3, R4 coupled in series are between cell voltage VBAT and ground connection GND, and its shared contact produces the first predeterminated voltage, and the present embodiment is set as 3V.The positive input terminal of operational amplifier 304 is coupled to judgement voltage VE, and negative input end is coupled to the shared contact of resistance R 3, R4 to receive the first predeterminated voltage.The output of operational amplifier 304 is coupled to the grid of PMOS transistor Q2 and Q3 via resistance R 5.The 3rd comparing unit 206 is comprised of resistance R 6, R7 and operational amplifier 306, and resistance R 6, R7 coupled in series are between cell voltage VBAT and ground connection GND, and its shared contact produces the second predeterminated voltage, and the present embodiment is set as 4V.The negative input end of operational amplifier 306 is coupled to judgement voltage VE, and positive input terminal is coupled to the shared contact of resistance R 6, R7 to receive the second predeterminated voltage.The output of operational amplifier 306 is coupled to the grid of PMOS transistor Q4 via resistance R 8.
The first discharge switching element 104 comprises fictitious load SR1 and PMOS transistor Q2, fictitious load SR1 and PMOS transistor Q2 coupled in series are between the first power end OUT1 and ground connection GND, and the grid of PMOS transistor Q2 sees through the output that resistance R 5 is coupled to operational amplifier 304.The second discharge switching element 116 comprises fictitious load SR2 and PMOS transistor Q3, fictitious load SR2 and PMOS transistor Q3 coupled in series are between second source end OUT2 and ground connection GND, and the grid of PMOS transistor Q3 sees through the output that resistance R 5 is coupled to operational amplifier 304.Power switch unit 106 consists of PMOS transistor Q4, the source electrode of its PMOS transistor Q4 and drain electrode are coupled to system voltage SB5V-IN and the first power end OUT1 (output terminal of standby voltage SB5V), and the grid of PMOS transistor Q4 sees through the output that resistance R 8 is coupled to operational amplifier 306.
Next, the circuit that further illustrates power control circuit 100 is made flowing mode, referring to Fig. 4, when system receives power supply, system voltage SB5V-IN can start to rise, when system voltage SB5V-IN is greater than the reference voltage of 3 volts, and the output meeting conducting nmos pass transistor M1 of operational amplifier 302, allow the output of push-pull circuit 208 rise with system voltage SB5V-IN, can be considered and export system voltage SB5V-IN to delay cell 210.Delay cell 210 meeting delay system voltage SB5V-IN (0.5 second) output judgement voltage VE after about a period of time.Therefore, the voltage upcurve of judgement voltage VE postpones approximately 0.5 second compared with system voltage SB5V-IN, as shown in Figure 4.
The conducting that the second comparing unit 204 decides PMOS transistor Q2, Q3 according to the variation of judgement voltage VE whether, when judgement voltage VE is less than the first predeterminated voltage (the present embodiment is set as 3V), operational amplifier 304 output electronegative potentials are with conducting PMOS transistor Q2, Q3, and now the first power end OUT1 and second source end OUT2 can discharge over the ground.When judgement voltage VE is greater than the first predeterminated voltage (the present embodiment is set as 3V), operational amplifier 304 output noble potentials, to cut out PMOS transistor Q2, Q3, have now completed discharging action.
The conducting that the 3rd comparing unit 204 decides PMOS transistor Q4 according to the variation of judgement voltage VE whether, when judgement voltage VE is greater than the second predeterminated voltage (the present embodiment is set as 4V), operational amplifier 304 output electronegative potentials are with conducting PMOS transistor Q4, and now system voltage SB5V-IN can be switched on to the first power end OUT1 to produce standby voltage SB5V.Because standby voltage SB3V is changed and obtained by standby voltage SB5V, so standby voltage SB3V also can rise to corresponding magnitude of voltage with standby voltage SB5V.
From the above, the second comparing unit 204 can discharge to the first power end OUT1 and second source end OUT2 before system voltage SB5V-IN rises to the first predeterminated voltage, avoids wrong voltage level to cause the System on Chip/SoC mistake start of rear end.At system voltage SB5V-IN, rise to after the second predeterminated voltage, the 3rd comparing unit 204 meeting conducting charging switching elements 106, allow the normal start of power module to produce standby voltage SB5V, SB3V.Via above-mentioned discharge procedures, the electric discharge that the voltage control circuit 100 of the present embodiment can accelerating power source end, avoids wrong voltage level to affect the normal start of System on Chip/SoC.
In addition, before rising to the second predeterminated voltage at judgement voltage VE, PMOS transistor Q4 is in closed condition, and standby voltage SB5V, SB3V can not raise with system voltage SB5V-IN.Therefore can reduce standby voltage SB5V, SB3V load between the system voltage SB5V-IN rising stage in the power consumption that causes.That is to say, can reduce the power consumption causing in start process.
In sum, the present invention utilizes judgement voltage that control module produces and the comparative result of the first predeterminated voltage, come in advance the power end of standby voltage to be discharged, and the comparative result of utilization judgement voltage and the second predeterminated voltage, power end is powered, so that the standby voltage of chip is powered after reaching completely electric discharge again on supply computer motherboard, avoid the remaining voltage of standby voltage to make element relevant to standby voltage in mainboard produce abnormal occurrence.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is worked as with being as the criterion that claim was defined.
Claims (14)
1. a power control circuit, is applicable to a mainboard, and described power control circuit comprises:
One first discharge switching element, is coupled between one first power end and a ground connection;
One power switch unit, is coupled between a system voltage and described the first power end; And
One control module, is coupled between described the first discharge switching element and described power switch unit, and controls described the first discharge switching element and described power switch unit according to the change in voltage of described system voltage;
Wherein, described control module postpones described system voltage to produce a judgement voltage, when described judgement voltage is less than first predeterminated voltage, described in described control module conducting, the first discharge switching element is to discharge to described the first power end, when described judgement voltage is greater than second predeterminated voltage, described in described control module conducting, power switch unit is to power to described the first power end, and wherein said the second predeterminated voltage is greater than described the first predeterminated voltage.
2. power control circuit as claimed in claim 1, is characterized in that, described the first discharge switching element comprises:
One first fictitious load, couples described the first power end; And
One the one PMOS transistor, its source terminal and drain electrode end couple respectively described the first fictitious load and described ground connection, and the transistorized grid of a described PMOS is coupled to described control module.
3. power control circuit as claimed in claim 1, is characterized in that, more comprises:
One second discharge switching element, be coupled between a second source end and described ground connection, and be controlled by described control module, when described judgement voltage is less than described the first predeterminated voltage, described in described control module conducting, the second discharge switching element is to discharge to described second source end, when described judgement voltage is greater than described the first predeterminated voltage, described control module is closed described the second discharge switching element.
4. power control circuit as claimed in claim 3, is characterized in that, described the second discharge switching element comprises:
One second fictitious load, couples described second source end; And
One the 2nd PMOS transistor, its source terminal and drain electrode end couple respectively described the second fictitious load and described ground connection, and the transistorized grid of described the 2nd PMOS is coupled to described control module.
5. power control circuit as claimed in claim 2, is characterized in that, described power switch unit comprises:
One the 3rd PMOS transistor, its source terminal and drain electrode end couple respectively described system voltage and described the first power end, and the transistorized grid of described the 3rd PMOS is coupled to described control module.
6. power control circuit as claimed in claim 1, is characterized in that, when described judgement voltage is greater than described the first predeterminated voltage, described control module is closed described the first discharge switching element.
7. power control circuit as claimed in claim 5, is characterized in that, described control module comprises:
One first comparing unit, in order to more described system voltage and a reference voltage;
One push-pull circuit, is coupled to described the first comparing unit and described system voltage, and when described system voltage is greater than described reference voltage, described push-pull circuit is exported described system voltage;
One delay cell, is coupled to the output of described push-pull circuit, in order to postpone described system voltage to produce described judgement voltage;
One second comparing unit, couples described delay cell and described the first discharge switching element, according to the comparative result of described judgement voltage and described the first predeterminated voltage, controls described the first discharge switching element; And
One the 3rd comparing unit, is coupled to and connects described delay cell and described power switch unit, according to the comparative result of described judgement voltage and described the second predeterminated voltage, controls described power switch unit.
8. power control circuit as claimed in claim 7, is characterized in that, described the first comparing unit comprises:
One first resistance;
One second resistance, and described the first resistance is serially connected with between a cell voltage and described ground connection, with cell voltage described in dividing potential drop, produces described reference voltage; And
One first operational amplifier, its positive input terminal couples described system voltage, and its negative input end couples the common joint of described the first resistance and described the second resistance.
9. power control circuit as claimed in claim 8, is characterized in that, described push-pull circuit comprises:
One nmos pass transistor, its drain electrode end couples described system voltage, and its gate terminal is coupled to the output terminal of described the first operational amplifier, and its source terminal is as the output terminal of described push-pull circuit and couple described delay cell; And
One the 4th PMOS transistor, its source terminal couples the source terminal of described nmos pass transistor, and the transistorized drain electrode end of described the 4th PMOS couples described ground connection, and the transistorized grid of described the 4th PMOS is coupled to the output terminal of described the first operational amplifier.
10. power control circuit as claimed in claim 7, is characterized in that, described delay cell comprises:
One resistance, one end of described resistance is coupled to the output of described push-pull circuit; And
One electric capacity, is coupled between the other end and described ground connection of described resistance.
11. power control circuits as claimed in claim 10, is characterized in that, described delay cell more comprises:
One diode, the anode tap of described diode couples the common joint of described resistance and described electric capacity, and the cathode terminal of described diode couples the output of described push-pull circuit.
12. power control circuits as claimed in claim 8, is characterized in that, described the second comparing unit comprises:
One the 3rd resistance;
One the 4th resistance, and described the 3rd resistance is serially connected with between described cell voltage and described ground connection, with cell voltage described in dividing potential drop, produces described the first predeterminated voltage; And
One second operational amplifier, the positive input terminal of described the second operational amplifier couples described delay cell to receive described judgement voltage, the negative input end of described the second operational amplifier couples the common joint of described the 3rd resistance and described the 4th resistance, and the output terminal of described the second operational amplifier sees through one the 5th resistance and is coupled to the transistorized grid of a described PMOS.
13. power control circuits as claimed in claim 7, is characterized in that, described the 3rd comparing unit comprises:
One the 6th resistance;
One the 7th resistance, and described the 6th resistance is serially connected with between described system voltage and described ground connection, with system voltage described in dividing potential drop, produces described the second predeterminated voltage; And
One the 3rd operational amplifier, the positive input terminal of described the 3rd operational amplifier couples the common joint of described the 6th resistance and described the 7th resistance, the negative input end of described the 3rd operational amplifier couples described judgement voltage, and the output terminal of described the 3rd operational amplifier sees through one the 8th resistance and is coupled to the transistorized grid of described the 3rd PMOS.
14. power control circuits as claimed in claim 7, is characterized in that, described reference voltage equals described the first predeterminated voltage.
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| CN104619103A (en) * | 2013-11-04 | 2015-05-13 | 台达电子工业股份有限公司 | X-ray tube power system and control method thereof |
| CN104578324A (en) * | 2015-02-04 | 2015-04-29 | 环旭电子股份有限公司 | Battery drive device |
| CN106033522B (en) * | 2015-03-20 | 2019-01-25 | 鸿富锦精密工业(武汉)有限公司 | Opening control system |
| CN110874109B (en) * | 2018-08-30 | 2021-11-16 | 环达电脑(上海)有限公司 | Power input control circuit |
| CN110943527B (en) * | 2018-09-25 | 2021-02-26 | 启碁科技股份有限公司 | Power supply device |
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|---|---|---|---|---|
| CN1250172A (en) * | 1998-10-02 | 2000-04-12 | 国际商业机器公司 | Active accelerated discharge of capacity system |
| US7262588B2 (en) * | 2003-11-27 | 2007-08-28 | Ricoh Company, Ltd. | Method and apparatus for power supply controlling capable of effectively controlling switching operations |
| CN101470654A (en) * | 2007-12-28 | 2009-07-01 | 鸿富锦精密工业（深圳）有限公司 | Mainboard test device |
| CN101593963A (en) * | 2008-05-30 | 2009-12-02 | 鸿富锦精密工业（深圳）有限公司 | Overvoltage crowbar |
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| CN102346529A (en) | 2012-02-08 |
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Effective date of registration: 20150916 Address after: 518057 Guangdong province Shenzhen city Nanshan District high tech Park North Park usi Patentee after: USI ELECTRONICS (SHENZHEN) CO., LTD. Address before: No. 1558 Chang Tung Road, Zhangjiang hi tech park, Shanghai Patentee before: Huanxu Electronics Co., Ltd. Patentee before: Universal Global Scientific Industries Co., Ltd. |