CN102346529A - Power supply control circuit - Google Patents
Power supply control circuit Download PDFInfo
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- CN102346529A CN102346529A CN2010102497985A CN201010249798A CN102346529A CN 102346529 A CN102346529 A CN 102346529A CN 2010102497985 A CN2010102497985 A CN 2010102497985A CN 201010249798 A CN201010249798 A CN 201010249798A CN 102346529 A CN102346529 A CN 102346529A
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Abstract
The invention discloses a power supply control circuit for a mainboard, which comprises a first discharge switch unit, a power supply switch unit and a control unit, wherein the control unit delays the system voltage for generating judgment voltage, the control unit conducts the first discharge switch unit for discharging a first power supply end when the voltage is judged to be lower than the first preset voltage, and the control unit conducts the power supply switch unit for supplying the electricity for the first power supply end when the voltage is judged to be higher than the second preset voltage, wherein the second preset voltage is higher than the first preset voltage.
Description
Technical field
The invention relates to a kind of power control circuit, and particularly relevant for a kind of power control circuit that in advance mainboard standby voltage end is discharged.
Background technology
Advanced technology expansion (Advanced Technology Extended is called for short ATX) mainboard specification is formulated in nineteen ninety-five by Intel company.At present most power supply units all are to use the ATX specification, and wherein the ATX connector the most often uses has two kinds of 20Pin and 24Pin, all comprise the pin of standby voltage (SB5V).Chipset on the mainboard comprises that south bridge uses standby voltage as operating power sometimes, but the discharge time of the standby voltage of exporting because of power supply unit (SB5V) maybe be different, and the standby voltage (SB3V) that therefore causes supplying with south bridge is also different discharge time.
When the chip in the mainboard (for example South Bridge chip) discharges when incomplete; Voltage that power supply unit provides possibly cause chip to produce abnormal occurrence; Not only can't bring into play the function of reinforcement thus, more can cause the total system can't normal operation, even can't start shooting.In addition, before system boot was accomplished, standby voltage (SB3V and SB5V) can cause power consumption, produces extra unnecessary power consumption.
Summary of the invention
The present invention provides a kind of power control circuit, can discharge with prevention standby voltage end to the standby voltage end discharge of mainboard in advance and not exclusively cause mainboard to produce abnormal occurrence.
The present invention proposes a kind of power control circuit, is applicable to a mainboard, and power control circuit comprises first discharge switching element, power switch unit and control module.Wherein, first discharge switching element is coupled between first power end and the ground connection.The power switch unit is coupled between the system voltage and first power end.Control module is coupled to first discharge switching element and power switch unit, and controls first discharge switching element and power switch unit according to the change in voltage of system voltage.Wherein, Control module delay system voltage is judged voltage to produce one; When judging voltage less than one first predeterminated voltage, control module conducting first discharge switching element is so that first power end is discharged, when judging voltage greater than second predeterminated voltage; Control module conducting power switch unit is to supply power to first power end, and wherein second predeterminated voltage is greater than first predeterminated voltage.
In one embodiment of this invention, the first above-mentioned discharge switching element comprises first fictitious load and a PMOS transistor.First fictitious load couples first power end, and transistorized source terminal of a PMOS and drain electrode end couple first fictitious load and ground connection respectively, and the transistorized grid of a PMOS is coupled to control module.
In one embodiment of this invention; Power control circuit more comprises second discharge switching element, and it is coupled between second source end and the ground connection, and is controlled by control module; When judging voltage less than first predeterminated voltage; Control module conducting second discharge switching element is to discharge to the second source end, and when judging voltage greater than first predeterminated voltage, control module is closed second discharge switching element.
In one embodiment of this invention, above-mentioned second fictitious load of second discharge switching element and the 2nd PMOS transistor.Wherein, second fictitious load couples the second source end, and transistorized source terminal of the 2nd PMOS and drain electrode end couple second fictitious load and ground connection respectively, and the transistorized grid of a PMOS is coupled to control module.
In one embodiment of this invention, above-mentioned power switch unit comprises the 3rd PMOS transistor, and its source terminal and drain electrode end be the coupling system voltage and first power end respectively, and the transistorized grid of the 3rd PMOS is coupled in control module.
In one embodiment of this invention, when judging voltage greater than first predeterminated voltage, control module is closed first discharge switching element.
In one embodiment of this invention, above-mentioned control module comprises first comparing unit, push-pull circuit, delay cell, second comparing unit and the 3rd comparing unit.First comparing unit is in order to a comparison system voltage and a reference voltage.Push-pull circuit is coupled to first comparing unit and system voltage, when system voltage greater than with reference voltage, push-pull circuit output system voltage.Delay cell is coupled to the output of push-pull circuit, judges voltage in order to delay system voltage to produce.Second comparing unit couples the delay cell and first discharge switching element, controls first discharge switching element according to the comparative result of judging the voltage and first predeterminated voltage.In addition, the 3rd comparing unit then is coupled to and connects delay cell and power switch unit, according to the comparative result control power switch unit of judging the voltage and second predeterminated voltage.
In one embodiment of this invention, the first above-mentioned comparing unit comprises first resistance, second resistance and first operational amplifier.Second resistance and first resistance string are connected between cell voltage and the ground connection, produce reference voltage with the dividing potential drop cell voltage.The positive input terminal coupling system voltage of first operational amplifier, its negative input end couples the common joint of first resistance and second resistance.
In one embodiment of this invention, above-mentioned push-pull circuit comprises nmos pass transistor and the 4th PMOS transistor.The drain electrode end coupling system voltage of nmos pass transistor wherein, its gate terminal is coupled to the output terminal of first operational amplifier, and its source terminal is as the output terminal of push-pull circuit and couple resistance.In addition, the transistorized source terminal of the 4th PMOS couples the source terminal of nmos pass transistor, and the 4th PMOS transistor drain end couples ground connection, and the transistorized grid of the 4th PMOS is coupled to the output terminal of first operational amplifier.
In one embodiment of this invention, above-mentioned delay cell comprises resistance and electric capacity.One end of resistance is coupled to the output of push-pull circuit, and electric capacity is coupled between the other end and ground connection of resistance.
In one embodiment of this invention, above-mentioned delay cell more comprises a diode, and the anode tap of diode couples the common joint of resistance and electric capacity, and the cathode terminal of diode then couples the output of push-pull circuit.
In one embodiment of this invention, the second above-mentioned comparing unit comprises the 3rd resistance, the 4th resistance and second operational amplifier.Wherein the 3rd resistance and the 4th resistance string are connected between reference voltage and the ground connection, produce first predeterminated voltage with the dividing potential drop reference voltage.The positive input terminal of second operational amplifier couples delay cell and judges voltage to receive; The negative input end of second operational amplifier couples the common joint of the 3rd resistance and the 4th resistance, and the output terminal of second operational amplifier sees through the 5th resistance and is coupled to the transistorized grid of a PMOS.
In one embodiment of this invention, the 3rd above-mentioned comparing unit comprises the 6th resistance, the 7th resistance and the 3rd operational amplifier.The 6th resistance and the 7th resistance string are connected between system voltage and the ground connection, produce second predeterminated voltage with voltage divider system voltage.The positive input terminal of the 3rd operational amplifier couples the common joint of the 6th resistance and the 7th resistance, and the negative input end of the 3rd operational amplifier couples judgement voltage, and the output terminal of the 3rd operational amplifier sees through the 8th resistance and is coupled to the transistorized grid of the 3rd PMOS.
In one embodiment of this invention, above-mentioned reference voltage equals first predeterminated voltage.
Based on above-mentioned; The present invention utilizes the comparative result of judgement voltage that control module produces and first predeterminated voltage, second predeterminated voltage; Coming to treat in advance dynamo-electric power end of pressing discharges; And power end supplied power, so that the standby voltage of chip reaches fully and is powered after the discharge again on the supply computer motherboard, avoid the remaining voltage of standby voltage to make element generation abnormal occurrence relevant in the mainboard with standby voltage.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Fig. 1 is the power module system figure according to the computing machine of one embodiment of the invention.
Fig. 2 is the calcspar according to the power control circuit of another embodiment of the present invention.
Fig. 3 is the calcspar according to the power control circuit of another embodiment of the present invention.
Fig. 4 is the change in voltage sequential chart according to the power control circuit of Fig. 3 embodiment.
Embodiment
Set forth embodiments of the invention in detail below with reference to accompanying drawing, the for example clear example embodiment of the present invention of accompanying drawing, the wherein same or similar element of same numeral indication.
In notebook; Its power module or power supply unit can convert AC power or battery supply into various system voltages; For example 3V, 5V, 12V etc., wherein system voltage comprises standby voltage, for example SB3V, SB5V etc. can supply circuit or South Bridge chip on the mainboard to use.Because if standby voltage SB3V, SB5V discharge not exclusively can influence system's normal operation of rear end, cause problem such as South Bridge chip mistake start to produce.Therefore, the power control circuit of present embodiment possibly produce the problem proposition settling mode that discharge not exclusively influences system's normal operation to various system voltages after shutdown.
Please with reference to Fig. 1, Fig. 1 is the power module system figure according to the computing machine of one embodiment of the invention.Power module comprises power-supply adapter (adapter) 108, first voltage conversion circuit 110, power control circuit 100, second electric pressure converter 112.Power-supply adapter 108 is used for transmitting voltage source to the first voltage conversion circuit 110; First voltage conversion circuit 110 can be with power conversion system voltage SB5V-IN; And then required standby voltage SB5V and the SB3V of the system that converts into; The end points of output standby voltage SB5V is called the first power end OUT1, and output standby voltage SB3V is called second source end OUT2.Wherein, standby voltage SB3V can treat via second voltage conversion circuit 112 and dynamo-electric press the SB5V dividing potential drop and get.Power control circuit 100 is integrated in the power module system, is used for the first power end OUT1, second source end OUT2 are supplied power and operation such as discharge, and after shutdown, produces the incomplete problem of discharging to prevent standby voltage SB3V, SB5V.
Through above-mentioned discharge flow path, standby voltage SB5V or SB3V that the chip (for example south bridge) in the host computer system 114 is received reach discharge fully, avoid the remaining voltage on the standby voltage to make the related elements in the host computer system 114 produce abnormal occurrence.For example the CMOS time of host computer system 114 expectedly is not eliminated.Wherein, second predeterminated voltage is greater than first predeterminated voltage.That is to say; In the process that system voltage SB5V-IN rises; Power control circuit 100 can be earlier discharges with second source end OUT2, and when system voltage SB5V-IN reaches first predeterminated voltage, stops to discharge through first discharge switching element 104,116 couples first power end OUT1 of second discharge switching element; Just charge to draw high the magnitude of voltage of standby voltage SB5V or SB3V during at system voltage SB5V-IN then greater than second predeterminated voltage through 106 couples first power end OUT1 in power switch unit and second source end OUT2.
It should be noted that; Above-mentioned output terminal with standby voltage SB5V, SB3V is the technological means that example is explained present embodiment; Right present embodiment is not limited to the output terminal of standby voltage SB5V, SB3V; Also can use merely at the output terminal of standby voltage SB5V or the output terminal of standby voltage SB3V, as long as select for use corresponding discharge switching element promptly applicable to the output terminal of a certain group of standby voltage; Can be applied to other power end, and applied output terminal number is also not limited, as long as draw high its magnitude of voltage again after the discharge switching element that increases correspondence promptly applicable to the output terminals of many group standby voltages, discharges it fully yet.
Next, further specify power control circuit, please with reference to Fig. 2, Fig. 2 is the calcspar according to the power control circuit of another embodiment of the present invention.Power control circuit 100 comprises control module 102, first discharge switch 104, second discharge switch 116 and power switch unit 106, and wherein control module 102 more comprises one first comparing unit 202, one second comparing unit 204, one the 3rd comparing unit 206, a delay cell 210 and a push-pull circuit 208.First comparing unit 202 is coupled to push-pull circuit 208, and delay cell 210 is coupled between push-pull circuit 208 and second comparing unit 204, the 3rd comparing unit 206.
First comparing unit 202 is coupled between system voltage SB5V-IN and the ground connection GND, and controls the output of push-pull circuit 208 according to the variation of system voltage SB5V-IN.As system voltage SB5V-IN during greater than a reference voltage, system voltage SB5V-IN exports the delay cell 210 of rear end to via push-pull circuit 208.Delay cell 210 couples the output terminal of push-pull circuit 208, is used for postponing the system voltage SB5V-IN that push-pull circuit 208 exported and judges voltage VE to produce.The time delay of delay cell 210 can be according to design requirement and deciding, 0.5 tip of a twig for example, and the circuit structure of delay cell 210 then for example is a RC delay circuit structure.The conducting that second comparing unit 204 can be controlled first discharge switch 104 and second discharge switch 116 according to the change in voltage of judging voltage VE whether, the conducting that the change in voltage of 206 judgements of the 3rd comparing unit voltage VE is controlled power switch 106 is whether.
When judging voltage VE less than first predeterminated voltage, second comparing unit, 204 meeting conducting first discharge switching element 104 and second discharge switching elements 116 are to discharge to the first power end OUT1 and second source end OUT2 respectively.When judging voltage VE greater than first predeterminated voltage, second comparing unit 204 can be closed first discharge switching element 104 and second discharge switching element 116.During when judgement voltage VE continuation rising and greater than second predeterminated voltage; The 3rd comparing unit 206 meeting conducting power switch unit 106; Let system voltage SB5V-IN that the first power end SB5V and second source end SB3V are supplied power to offer the system of rear end, use like south bridge.Wherein, second predeterminated voltage is greater than first predeterminated voltage.That is to say that power control circuit 100 can discharge to the first power end OUT1 and second source end OUT2 earlier, and then draws high its magnitude of voltage.
Next, further specifying the circuit structure in the above-mentioned power control circuit 100, is the circuit diagram according to the power control circuit of present embodiment with reference to Fig. 3 please.Fig. 4 is the change in voltage sequential chart according to the power control circuit of Fig. 3 embodiment.Please be simultaneously with reference to Fig. 3 and Fig. 4, first comparing unit 202 comprises resistance R 1, R2 and operational amplifier 302.Wherein resistance R 1, R2 are serially connected with between a cell voltage VBAT and the ground connection GND, in order to dividing potential drop cell voltage VBAT on the common joint of resistance R 1, R2, to produce above-mentioned reference voltage.Cell voltage VBAT for example is the cell voltage on the mainboard, and reference voltage for example is 3V.The positive and negative input end of operational amplifier 302 is coupling system voltage SB5V-IN and reference voltage (3V) respectively, in order to the size of comparison system voltage SB5V-IN and reference voltage.
Push-pull circuit 208 is by NMOS (N channel metal oxide semiconductor transistor; Be called for short NMOS) transistor M1 and PMOS (P channel metal oxide semiconductor transistor; Abbreviation PMOS) transistor Q1 composes in series, and its grid all is connected in the output of computing comparer 302.Delay cell 210 is made up of resistance R 9, capacitor C and diode D1, and resistance R 9 and capacitor C coupled in series are between the output and ground connection GND of push-pull circuit 208, and diode D1 is parallelly connected with resistance R 9.Wherein, resistance R 9 is judged voltage VE with the shared contact output of capacitor C.Delay cell 210 mainly is to postpone the system voltage SB5C-IN that push-pull circuit 208 is exported through the RC circuit, lets first power end OUT1 of rear end and second source end OUT2 under the situation of power connector plug suddenly, have the longer time to discharge by this.
Second comparing unit 204 is made up of resistance R 3, R4 and 304 of operational amplifiers, and resistance R 3, R4 coupled in series are between cell voltage VBAT and ground connection GND, and its shared contact produces first predeterminated voltage, and present embodiment is set at 3V.The positive input terminal of operational amplifier 304 is coupled to judges voltage VE, and negative input end is coupled to the shared contact of resistance R 3, R4 to receive first predeterminated voltage.The output of operational amplifier 304 is coupled to the grid of PMOS transistor Q2 and Q3 via resistance R 5.The 3rd comparing unit 206 is made up of resistance R 6, R7 and 306 of operational amplifiers, and resistance R 6, R7 coupled in series are between cell voltage VBAT and ground connection GND, and its shared contact produces second predeterminated voltage, and present embodiment is set at 4V.The negative input end of operational amplifier 306 is coupled to judges voltage VE, and positive input terminal is coupled to the shared contact of resistance R 6, R7 to receive second predeterminated voltage.The output of operational amplifier 306 is coupled to the grid of PMOS transistor Q4 via resistance R 8.
First discharge switching element 104 comprises fictitious load SR1 and PMOS transistor Q2; Fictitious load SR1 and PMOS transistor Q2 coupled in series are between the first power end OUT1 and ground connection GND, and the grid of PMOS transistor Q2 then sees through the output that resistance R 5 is coupled to operational amplifier 304.Second discharge switching element 116 comprises fictitious load SR2 and PMOS transistor Q3; Fictitious load SR2 and PMOS transistor Q3 coupled in series are between second source end OUT2 and ground connection GND, and the grid of PMOS transistor Q3 then sees through the output that resistance R 5 is coupled to operational amplifier 304.Power switch unit 106 is made up of PMOS transistor Q4; The source electrode of its PMOS transistor Q4 and drain electrode are coupled to system voltage SB5V-IN and the first power end OUT1 (output terminal of standby voltage SB5V), and the grid of PMOS transistor Q4 then sees through the output that resistance R 8 is coupled to operational amplifier 306.
Next, the circuit that further specifies power control circuit 100 is made flowing mode, please be simultaneously with reference to Fig. 4; When system receives power supply; System voltage SB5V-IN can begin to rise, as system voltage SB5V-IN during greater than 3 volts reference voltage, and the output meeting conducting nmos pass transistor M1 of operational amplifier 302; Let the output of push-pull circuit 208 rise, can be considered and export system voltage SB5V-IN to delay cell 210 with system voltage SB5V-IN.Delay cell 210 meeting delay system voltage SB5V-IN (0.5 second) output judgement voltage VE after about a period of time.Therefore, judge that the voltage upcurve of voltage VE postpones about 0.5 second than system voltage SB5V-IN, as shown in Figure 4.
The conducting that second comparing unit 204 decides PMOS transistor Q2, Q3 according to the variation of judging voltage VE whether; When judging voltage VE less than first predeterminated voltage (present embodiment is set at 3V); Operational amplifier 304 output electronegative potentials are with conducting PMOS transistor Q2, Q3, and this moment, the first power end OUT1 and second source end OUT2 can discharge over the ground.When judging voltage VE greater than first predeterminated voltage (present embodiment is set at 3V), operational amplifier 304 output noble potentials have accomplished discharging action this moment to cut out PMOS transistor Q2, Q3.
The conducting that the 3rd comparing unit 204 decides PMOS transistor Q4 according to the variation of judging voltage VE whether; When judging voltage VE greater than second predeterminated voltage (present embodiment is set at 4V); Operational amplifier 304 output electronegative potentials are with conducting PMOS transistor Q4, this moment system voltage SB5V-IN can be switched on to the first power end OUT1 to produce standby voltage SB5V.Owing to standby voltage SB3V is got by standby voltage SB5V conversion, so standby voltage SB3V also can rise to corresponding voltage value with standby voltage SB5V.
From the above, second comparing unit 204 can discharge to the first power end OUT1 and second source end OUT2 before system voltage SB5V-IN rises to first predeterminated voltage, avoids wrong voltage level to cause the System on Chip/SoC mistake start of rear end.After system voltage SB5V-IN rose to second predeterminated voltage, the 3rd comparing unit 204 meeting conducting charging switching elements 106 let the normal start of power module to produce standby voltage SB5V, SB3V.Via above-mentioned discharge procedures, but the discharge of the voltage control circuit 100 accelerating power source ends of present embodiment avoids wrong voltage level to influence the normal start of System on Chip/SoC.
In addition, because before judging that voltage VE rises to second predeterminated voltage, PMOS transistor Q4 is in closed condition, standby voltage SB5V, SB3V can not raise with system voltage SB5V-IN.Therefore can reduce standby voltage SB5V, SB3V load between the system voltage SB5V-IN rising stage in the power consumption that caused.That is to say the power consumption that can reduce in start process to be caused.
In sum; The present invention utilizes the judgement voltage that control module produces and the comparative result of first predeterminated voltage; Come to treat in advance dynamo-electric power end of pressing and discharge, and utilize the comparative result of judging the voltage and second predeterminated voltage, come power end is supplied power; So that the standby voltage of chip is powered after reaching fully discharge again on the supply computer motherboard, avoid the remaining voltage of standby voltage to make element generation abnormal occurrence relevant in the mainboard with standby voltage.
Though the present invention discloses as above with embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when doing a little change and retouching, so protection scope of the present invention is when being as the criterion with what claim defined.
Claims (14)
1. a power control circuit is applicable to a mainboard, and said power control circuit comprises:
One first discharge switching element is coupled between one first power end and the ground connection;
One power switch unit is coupled between a system voltage and said first power end; And
One control module is coupled to said first discharge switching element and said power switch unit, and controls said first discharge switching element and said power switch unit according to the change in voltage of said system voltage;
Wherein, Said control module postpones said system voltage and judges voltage to produce one; When said judgement voltage during less than one first predeterminated voltage, said first discharge switching element of said control module conducting to be discharging to said first power end, when said judgement voltage during greater than one second predeterminated voltage; The said power switch of said control module conducting unit is to supply power to said first power end, and wherein said second predeterminated voltage is greater than said first predeterminated voltage.
2. power control circuit as claimed in claim 1 is characterized in that, said first discharge switching element comprises:
One first fictitious load couples said first power end; And
One the one PMOS transistor, its source terminal and drain electrode end couple said first fictitious load and said ground connection respectively, and the transistorized grid of a said PMOS is coupled to said control module.
3. power control circuit as claimed in claim 1 is characterized in that, more comprises:
One second discharge switching element; Be coupled between said second source end and the said ground connection; And be controlled by said control module, when said judgement voltage during less than said first predeterminated voltage, said second discharge switching element of said control module conducting is to discharge to said second source end; When said judgement voltage during greater than said first predeterminated voltage, said control module is closed said second discharge switching element.
4. power control circuit as claimed in claim 3 is characterized in that, said second discharge switching element comprises:
One second fictitious load couples said second source end; And
One the 2nd PMOS transistor, its source terminal and drain electrode end couple said second fictitious load and said ground connection respectively, and the transistorized grid of said the 2nd PMOS is coupled to said control module.
5. power control circuit as claimed in claim 1 is characterized in that, said power switch unit comprises:
One the 3rd PMOS transistor, its source terminal and drain electrode end couple said system voltage and said first power end respectively, and the transistorized grid of said the 3rd PMOS is coupled to said control module.
6. power control circuit as claimed in claim 1 is characterized in that, when said judgement voltage during greater than said first predeterminated voltage, said control module is closed said first discharge switching element.
7. power control circuit as claimed in claim 1 is characterized in that, said control module comprises:
One first comparing unit is in order to a more said system voltage and a reference voltage;
One push-pull circuit is coupled to said first comparing unit and said system voltage, when said system voltage greater than with said reference voltage, said push-pull circuit is exported said system voltage;
One delay cell is coupled to the output of said push-pull circuit, in order to postpone said system voltage to produce said judgement voltage;
One second comparing unit couples said delay cell and said first discharge switching element, controls said first discharge switching element according to the comparative result of said judgement voltage and said first predeterminated voltage; And
One the 3rd comparing unit is coupled to and connects said delay cell and said power switch unit, controls said power switch unit according to the comparative result of said judgement voltage and said second predeterminated voltage.
8. power control circuit as claimed in claim 7 is characterized in that, said first comparing unit comprises:
One first resistance;
One second resistance, and said first resistance string is connected between a cell voltage and the said ground connection, produces said reference voltage with the said cell voltage of dividing potential drop; And
One first operational amplifier, its positive input terminal couples said system voltage, and its negative input end couples the common joint of said first resistance and said second resistance.
9. power control circuit as claimed in claim 8 is characterized in that, said push-pull circuit comprises:
One nmos pass transistor, its drain electrode end couples said system voltage, and its gate terminal is coupled to the output terminal of said first operational amplifier, and its source terminal is as the output terminal of said push-pull circuit and couple said delay cell; And
One the 4th PMOS transistor, its source terminal couples the source terminal of said nmos pass transistor, and said the 4th PMOS transistor drain end couples said ground connection, and the transistorized grid of said the 4th PMOS is coupled to the output terminal of said first operational amplifier.
10. power control circuit as claimed in claim 7 is characterized in that, said delay cell comprises:
One resistance, an end of said resistance is coupled to the output of said push-pull circuit; And
One electric capacity is coupled between the other end and said ground connection of said resistance.
11. power control circuit as claimed in claim 10 is characterized in that, said delay cell more comprises:
One diode, the anode tap of said diode couples the common joint of said resistance and said electric capacity, and the cathode terminal of said diode couples the output of said push-pull circuit.
12. power control circuit as claimed in claim 7 is characterized in that, said second comparing unit comprises:
One the 3rd resistance;
One the 4th resistance, and said the 3rd resistance string is connected between said cell voltage and the said ground connection, produces said first predeterminated voltage with the said cell voltage of dividing potential drop; And
One second operational amplifier; The positive input terminal of said second operational amplifier couples said delay cell to receive said judgement voltage; The negative input end of said second operational amplifier couples the common joint of said the 3rd resistance and said the 4th resistance, and the output terminal of said second operational amplifier sees through one the 5th resistance and is coupled to the transistorized grid of a said PMOS.
13. power control circuit as claimed in claim 7 is characterized in that, said the 3rd comparing unit comprises:
One the 6th resistance;
One the 7th resistance, and said the 6th resistance string is connected between said system voltage and the said ground connection, produces said second predeterminated voltage with the said system voltage of dividing potential drop; And
One the 3rd operational amplifier; The positive input terminal of said the 3rd operational amplifier couples the common joint of said the 6th resistance and said the 7th resistance; The negative input end of said the 3rd operational amplifier couples said judgement voltage, and the output terminal of said the 3rd operational amplifier sees through one the 8th resistance and is coupled to the transistorized grid of said the 3rd PMOS.
14. power control circuit as claimed in claim 7 is characterized in that, said reference voltage equals said first predeterminated voltage.
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| CN104578324A (en) * | 2015-02-04 | 2015-04-29 | 环旭电子股份有限公司 | Battery drive device |
| CN104619103A (en) * | 2013-11-04 | 2015-05-13 | 台达电子工业股份有限公司 | X-ray tube power system and control method thereof |
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| CN110874109A (en) * | 2018-08-30 | 2020-03-10 | 环达电脑(上海)有限公司 | Power input control circuit |
| CN110943527A (en) * | 2018-09-25 | 2020-03-31 | 启碁科技股份有限公司 | Power supply device |
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| CN104619103A (en) * | 2013-11-04 | 2015-05-13 | 台达电子工业股份有限公司 | X-ray tube power system and control method thereof |
| CN104578324A (en) * | 2015-02-04 | 2015-04-29 | 环旭电子股份有限公司 | Battery drive device |
| CN106033522A (en) * | 2015-03-20 | 2016-10-19 | 鸿富锦精密工业(武汉)有限公司 | Start-up control system |
| CN106033522B (en) * | 2015-03-20 | 2019-01-25 | 鸿富锦精密工业(武汉)有限公司 | Opening control system |
| CN110874109A (en) * | 2018-08-30 | 2020-03-10 | 环达电脑(上海)有限公司 | Power input control circuit |
| CN110874109B (en) * | 2018-08-30 | 2021-11-16 | 环达电脑(上海)有限公司 | Power input control circuit |
| CN110943527A (en) * | 2018-09-25 | 2020-03-31 | 启碁科技股份有限公司 | Power supply device |
| CN110943527B (en) * | 2018-09-25 | 2021-02-26 | 启碁科技股份有限公司 | Power supply device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102346529B (en) | 2014-04-16 |
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Effective date of registration: 20150916 Address after: 518057 Guangdong province Shenzhen city Nanshan District high tech Park North Park usi Patentee after: USI ELECTRONICS (SHENZHEN) CO., LTD. Address before: No. 1558 Chang Tung Road, Zhangjiang hi tech park, Shanghai Patentee before: Huanxu Electronics Co., Ltd. Patentee before: Universal Global Scientific Industries Co., Ltd. |