CN115543907A - Control method and device based on PCIe chip in storage device - Google Patents

Control method and device based on PCIe chip in storage device Download PDF

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Publication number
CN115543907A
CN115543907A CN202211483060.4A CN202211483060A CN115543907A CN 115543907 A CN115543907 A CN 115543907A CN 202211483060 A CN202211483060 A CN 202211483060A CN 115543907 A CN115543907 A CN 115543907A
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interface card
pcie
signal
circuit
mainboard
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CN115543907B (en
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江博
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The embodiment of the application provides a control method and a control device based on a PCIe chip in a storage device, wherein the method comprises the following steps: when any PCIe interface is inserted into the mainboard, an enabling signal is sent to the interface card through the mainboard to control a power supply of the mainboard to be communicated with the interface card through the first power supply circuit and communicated with the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on; when the power-off demand of the interface card is detected, a closing signal is sent to the interface card through any one mainboard, so that a second power circuit between the control interface card and the PCIe chip is disconnected, the PCIe chip is powered off independently under the condition that the interface card is powered on, the independent power-off repair of the PCIe chip is realized, the normal operation of other services is ensured, the operation cost is reduced, the quality reinforcement is carried out on a service path, and the reliability and the self-healing capacity of a product are improved.

Description

Control method and device based on PCIe chip in storage device
Technical Field
The present application relates to the field of storage devices, and in particular, to a control method and apparatus based on a PCIe chip in a storage device.
Background
The one-frame four-control (Quad Hosts and Single cards) of the current storage control frame is gradually becoming a trend of high-end storage due to the strong reliability of the four bad frames. Four controllers (i.e. main boards) are arranged in one frame of four controllers, i.e. one case, and after four controllers fail and three controllers fail, the remaining controller can still provide normal service for customers.
When at least one motherboard is present in a subrack, the interface cards need to be powered up to provide the traffic data flow path. When the interface card fails to be upgraded or needs to be repaired, the chip of the interface card needs to be powered off and controlled. At this time, only all the motherboards can be controlled to perform power down operation on the interface cards, and the power down operation on the entire interface cards can affect other services, which is also high in operation cost.
Disclosure of Invention
In view of the foregoing problems, embodiments of the present application are provided to provide a control method and apparatus based on a PCIe chip in a storage device, which overcome or at least partially solve the foregoing problems.
In order to solve the above problem, an embodiment of the present application discloses a control method based on a PCIe chip in a storage device, where the storage device is provided with an interface card, the interface card is provided with the PCIe chip and multiple PCIe interfaces connected to the PCIe chip, and when any one PCIe interface is inserted into a motherboard, a power supply of the motherboard is connected to an interface card through a first power circuit, and the interface card is connected to the PCIe chip through a second power circuit, and the method includes:
when any PCIe interface is inserted into the mainboard, an enabling signal is sent to the interface card through the mainboard to control a power supply of the mainboard to be communicated with the interface card through the first power supply circuit and communicated with the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on;
when the power-off requirement of the interface card is detected, a shutdown signal is sent to the interface card through any one mainboard to control the disconnection of a second power circuit between the interface card and the PCIe chip, so that the PCIe chip is powered off independently under the condition that the interface card is powered on.
Optionally, the mainboard is provided with first signal circuit, sends the enable signal to the interface card through the mainboard to the power supply who controls the mainboard includes through first power supply circuit and interface card intercommunication:
calling a first signal circuit through the mainboard to send an enabling signal to the interface card so as to control a power supply of the mainboard to be communicated with the interface card through the first power circuit; the first signal circuit is used for controlling connection or disconnection of the first power supply circuit.
Optionally, a first switch is disposed on the first power circuit, the first signal circuit is connected to the first switch to control the first switch to be turned on or turned off, and the invoking of the first signal circuit by the motherboard to send the enable signal to the interface card includes:
the first signal circuit is called through the mainboard to send an enabling signal to the first switch, so that the first switch is turned on.
Optionally, a first control element is further disposed between the first signal circuit and the first switch, and the first signal circuit controls the first switch to be turned on or turned off through the first control element.
Optionally, the first control element comprises or gate logic.
Optionally, the mainboard is provided with second signal circuit, sends the shutdown signal to the interface card through arbitrary one mainboard to the disconnection of the second power supply circuit between control interface card and the PCIe chip includes:
calling a second signal circuit through any one mainboard to send a closing signal to the interface card so as to control the disconnection of a second power circuit between the interface card and the PCIe chip; the second signal circuit is used for controlling connection or disconnection of the second power supply circuit.
Optionally, a second switch is disposed on the second power supply circuit, the second signal circuit is connected to the second switch to control the second switch to be turned on or turned off, and the step of calling the second signal circuit through any one of the motherboards to send the turn-off signal to the interface card includes:
and calling a second signal circuit through any one mainboard to send a closing signal to the second switch so as to close the second switch.
Optionally, a second control element is further disposed between the second signal circuit and the second switch, and the second signal circuit controls the second switch to be turned on or turned off through the second control element.
Optionally, the second control element comprises and logic circuitry.
Optionally, the motherboard is provided with a programmable logic device.
Optionally, sending the enable signal to the interface card through the motherboard includes:
and sending a first control signal to the programmable logic device to enable the programmable logic device to send an enabling signal to the interface card.
Optionally, sending the shutdown signal to the interface card through any one motherboard includes:
and sending a second control signal to any one programmable logic unit to enable any one programmable logic unit to send a closing signal to the interface card.
Optionally, the power-off requirement includes an upgrade failure and/or a service requirement.
Optionally, after powering down the PCIe chip alone while the interface card remains powered up, the method further includes:
and performing repair operation on the PCIe chip.
Optionally, four main boards are provided.
Optionally, the interface card further includes a data distribution algorithm module and/or an EBOF module.
Optionally, an overload fuse is disposed between the power supply of the main board and the first switch.
The embodiment of the application also discloses a controlling means based on PCIe chip in storage device, storage device is provided with the interface card, and the interface card is provided with the PCIe chip and a plurality of PCIe interfaces of being connected with the PCIe chip, inserts under the condition of arbitrary one PCIe interface at the mainboard, and the power supply of mainboard links to each other with the first power supply circuit of interface card, and the interface card passes through the second power supply circuit with the PCIe chip and links to each other, and the device includes:
the power-on module is used for sending an enabling signal to the interface card through the mainboard when any PCIe interface is inserted into the mainboard so as to control a power supply of the mainboard to be communicated with the interface card through the first power supply circuit and communicated with the PCIe chip through the second power supply circuit, and the interface card and the PCIe chip are powered on;
and the independent power-off module is used for sending a shutdown signal to the interface card through any one mainboard when the power-off requirement of the interface card is detected so as to control the disconnection of a second power circuit between the interface card and the PCIe chip and enable the PCIe chip to be powered off independently under the condition that the interface card is kept powered on.
The embodiment of the application also discloses an electronic device, which comprises a processor, a memory and a computer program stored on the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the control method based on the PCIe chip in the storage device are implemented.
The embodiment of the application also discloses a computer nonvolatile readable storage medium, on which a computer program is stored, and when being executed by a processor, the computer program realizes the steps of the control method based on the PCIe chip in the storage device.
The embodiment of the application has the following advantages:
in the embodiment of the application, the storage device is provided with an interface card, the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected with the PCIe chip, under the condition that any one PCIe interface is inserted into the mainboard, a power supply of the mainboard is connected with the interface card through a first power circuit, the interface card is connected with the PCIe chip through a second power circuit, and when any one PCIe interface is inserted into the mainboard, an enabling signal is sent to the interface card through the mainboard so as to control the power supply of the mainboard to be communicated with the interface card through the first power circuit and be communicated with the PCIe chip through the second power circuit, so that the interface card and the PCIe chip are powered on; when the power-off demand of the interface card is detected, a shutdown signal is sent to the interface card through any mainboard, so that a second power circuit between the control interface card and the PCIe chip is disconnected, the PCIe chip is powered off independently under the condition that the interface card is powered on, the independent power-off repair of the PCIe chip is realized, the normal operation of other services is ensured, the operation cost is reduced, the quality reinforcement is carried out on a service path, and the reliability and the self-healing capacity of a product are improved.
Drawings
FIG. 1 is a block diagram of a one-frame four-control storage device;
FIG. 2 is a schematic diagram of an embodiment of a control method based on a PCIe chip in a storage device according to the present application;
FIG. 3 is a schematic diagram of an embodiment of a control method based on a PCIe chip in a storage device according to the present application;
FIG. 4 is a flowchart illustrating steps of an embodiment of a control method based on a PCIe chip in a storage device according to the present application;
FIG. 5 is a flowchart illustrating steps of another embodiment of a method for controlling a storage device based on a PCIe chip according to the present application;
FIG. 6 is a flowchart illustrating steps of another embodiment of a method for controlling a storage device based on a PCIe chip according to the present application;
FIG. 7 is a flowchart illustrating steps of another embodiment of a method for controlling a storage device based on a PCIe chip of the present application;
fig. 8 is a block diagram of an embodiment of a control apparatus based on a PCIe chip in a storage device according to the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
As shown in fig. 1, a one-frame four-control storage device includes four motherboards, a client server is interconnected with multiple hosts through a 400G network, an EBOF (a network card type) network disk cabinet is interconnected with an EBOF interface card through the 400G network, and a data distribution algorithm interface card and the EBOF interface card of the multiple hosts are respectively interconnected with the four motherboards in a frame through PCIe (peripheral component interconnect express) chips. The data distribution algorithm interface card receives the service data of the front-end server, the EBOF interface card forwards the service data to the EBOF network disk cabinet, and the data distribution algorithm interface card and the EBOF interface card are physical links used by service data flow.
When the upgrade of the data distribution algorithm interface card and the EBOF interface card fails or due to service requirements, the PCIe chip needs to be controlled electrically to carry out repair operation. At this time, the four mainboards have and logic for controlling the power-off of the PCIe chip, and the four mainboards are required to simultaneously send a shutdown signal to control the power-off of the PCIe chip, and the data distribution algorithm interface card and the EBOF interface card are also powered off, so that other services are affected.
However, in the standard protocol of OCP (Open computing project) NIC (network interface controller) 3.0, which can be referred to at present, PCIe Bifurcation is defined as follows:
single Host (1 x 16) and 1x16 OCP NIC 3.0 Card (Single Controller) (Single motherboard, single Host and Single PCIe port);
single Host (2 x 8) and 2x8 OCP NIC 3.0 cards (Dual Controllers) (Single board Single Host and Single board Dual PCIe port);
quad Hosts (4 x 4) and 4x4 OCP NIC 3.0 Card (Single Controller) (Single motherboard with four Hosts and Single PCIe port);
quad Hosts (4 x 4) and 4x4 OCP NIC 3.0 Cards (Quad Controllers) (single motherboard with four Hosts and single board with four PCIe ports).
As can be seen, the above protocol does not define an interconnection topology scenario of four motherboards and four hosts with a single board and a single PCIe end.
Based on this, the present application provides an embodiment of a control method based on a PCIe chip in a storage Device, as shown in fig. 2 and fig. 3, after host x86 loads a bios (basic input output System) for operation, host x86 may directly access a CPLD (Complex Programmable Logic Device) of a motherboard through a smbus (System Management Bus), where the CPLD provides an enable command interface and a close command interface.
Each mainboard provides MAIN-PWR-EN (MAIN power supply signal circuit), the MAIN-PWR-EN of four mainboards are combined together by utilizing an OR gate logic circuit, and finally the switch A from P12V-edge to P12V on the multi-homing interface card is controlled, when at least one mainboard is inserted into the machine frame, host x86 controls the CPLD of the mainboard to send an enabling signal through the MAIN-PWR-EN, and the multi-homing interface card can be powered on.
Each mainboard provides a PWR-EN (independent power signal circuit), the PWR-EN of the four mainboards are combined together by using an AND logic circuit, and finally the DCDC switches from P12V to P3V3_ PCIE on the multi-homing interface card are controlled (the P3V3_ PCIE is a working power supply used by a PCIe end chip, and the DCDC is a device for converting a direct current power supply of a certain voltage level into a direct current power supply of other voltage levels and is equivalent to one switch). When the multi-homing interface card fails to upgrade or needs of services, the host x86 controls the CPLD of any one mainboard to send a closing signal through the PWR-EN, the P12V and the P3V3_ PCIE are disconnected, and the P12V-edge are still communicated, so that the demand of independent power-off of a PCIe end chip is realized, normal operation of other services is ensured, the operation cost is reduced, quality reinforcement is performed on a service path, and the reliability and the self-healing capability of a product are improved.
The examples of the present application are further illustrated below:
referring to fig. 4, a flowchart illustrating steps of an embodiment of a control method based on a PCIe chip in a storage device according to the present application is shown, where the storage device is provided with an interface card, the interface card is provided with the PCIe chip and multiple PCIe interfaces connected to the PCIe chip, and when any one PCIe interface is inserted into a motherboard, a power supply of the motherboard is connected to the interface card through a first power circuit, and the interface card is connected to the PCIe chip through a second power circuit, and the method may include the following steps:
step 401, when any PCIe interface is inserted into the motherboard, sending an enable signal to the interface card through the motherboard to control the power supply of the motherboard to communicate with the interface card through the first power circuit, and communicate with the PCIe chip through the second power circuit, so that the interface card and the PCIe chip are powered on.
When any one PCIe interface is inserted into the mainboard, the interface card needs to be powered on, so that a service data flow path is provided for the mainboard, an enabling signal is sent to the interface card through the mainboard, the power supply of the mainboard is controlled to be communicated with the interface card through the first power supply circuit, and the interface card and the PCIe chip are powered on through the second power supply circuit and the PCIe chip.
In a specific implementation, four motherboards may be provided.
By arranging the four mainboards, the storage control frame with one frame and four controls is formed, so that the reliability of the storage device is improved, and even if three of the four mainboards fail, the normal service of a client can be provided by using the remaining one mainboard.
In practical applications, the interface card may further include a data distribution algorithm module and/or an EBOF module.
By arranging the algorithm module and/or the EBOF module, the interface card can bear the service data of the front-end server and forward the service data to the EBOF network disk cabinet, thereby providing a service data flow path.
Step 402, when the power-off requirement of the interface card is detected, a shutdown signal is sent to the interface card through any one mainboard to control the disconnection of a second power circuit between the interface card and the PCIe chip, so that the PCIe chip is powered off independently under the condition that the interface card remains powered on.
When the power-off requirement of the interface card is detected, in order to avoid the influence of other services, a shutdown signal is sent to the interface card through any mainboard, so that the disconnection of a second power circuit between the interface card and the PCIe chip is controlled, and the PCIe chip is powered off independently under the condition that the interface card is kept powered on.
In one embodiment of the present application, the power down requirement includes an upgrade failure and/or a business requirement.
When the interface card fails to be upgraded or needs to be subjected to business, the PCIe chip needs to be powered off, so that faults are eliminated, and business requirements are met.
In an embodiment of the present application, after powering down the PCIe chip alone while the interface card remains powered up in step 402, the method may further include the steps of:
and performing repair operation on the PCIe chip.
After the repair operation for the PCIe chip is completed, the motherboard that sends the shutdown signal to the interface card in step 402 may send an enable signal to the interface card to control the second power circuit between the interface card and the PCIe chip to be reconnected, so that the PCIe chip is powered on again.
In the embodiment of the application, the storage device is provided with an interface card, the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected with the PCIe chip, under the condition that any one PCIe interface is inserted into the mainboard, a power supply of the mainboard is connected with the interface card through a first power circuit, the interface card is connected with the PCIe chip through a second power circuit, and when any one PCIe interface is inserted into the mainboard, an enabling signal is sent to the interface card through the mainboard so as to control the power supply of the mainboard to be communicated with the interface card through the first power circuit and be communicated with the PCIe chip through the second power circuit, so that the interface card and the PCIe chip are powered on; when the power-off demand of the interface card is detected, a closing signal is sent to the interface card through any one mainboard, so that a second power circuit between the control interface card and the PCIe chip is disconnected, the PCIe chip is powered off independently under the condition that the interface card is powered on, the independent power-off repair of the PCIe chip is realized, the normal operation of other services is ensured, the operation cost is reduced, the quality reinforcement is carried out on a service path, and the reliability and the self-healing capacity of a product are improved.
Referring to fig. 5, a flowchart illustrating steps of another embodiment of a control method based on a PCIe chip in a storage device according to the present application is shown, where the storage device is provided with an interface card, the interface card is provided with the PCIe chip and multiple PCIe interfaces connected to the PCIe chip, and when any one PCIe interface is inserted into a motherboard, a power supply of the motherboard is connected to an interface card through a first power circuit, the interface card is connected to the PCIe chip through a second power circuit, and the motherboard is provided with a first signal circuit, and the method may include the following steps:
step 501, when any PCIe interface is inserted into the mainboard, the mainboard calls the first signal circuit to send an enable signal to the interface card so as to control the power supply of the mainboard to be communicated with the interface card through the first power circuit and be communicated with the PCIe chip through the second power circuit, and the interface card and the PCIe chip are powered on.
The first signal circuit is used for controlling connection or disconnection of the first power supply circuit, so that control over the first power supply circuit can be completed through the first signal circuit, and influence on control over the second power supply circuit is avoided.
When any one PCIe interface is inserted into the mainboard, the interface card needs to be powered on, so that a service data flow path is provided for the mainboard, the mainboard calls the first signal circuit to send an enabling signal to the interface card, the power supply of the mainboard is controlled to be communicated with the interface card through the first power circuit, the power supply of the mainboard is controlled to be communicated with the PCIe chip through the second power circuit, and the interface card and the PCIe chip are powered on.
In an embodiment of the present application, a first switch is disposed on the first power circuit, the first signal circuit is connected to the first switch to control the first switch to be turned on or turned off, and the step 601 of sending the enable signal to the interface card by calling the first signal circuit through the motherboard may include the following sub-steps:
and a substep 11 of calling the first signal circuit through the main board to send an enable signal to the first switch to turn on the first switch.
Through setting up first switch, be convenient for control first power supply circuit's intercommunication or disconnection more, the accurate control of electrifying to interface card and PCIe chip that realizes.
In another embodiment of the present application, an overload fuse may be disposed between the power supply of the main board and the first switch.
When the current in the first power supply circuit is overlarge, the overload fuse can disconnect the power supply from the first switch, so that the interface card and the PCIe chip are prevented from being damaged due to overload, and the safe operation of the circuit is ensured.
In a particular application, the overload fuse may be configured as an efause switch.
In a specific implementation, a first control part is further arranged between the first signal circuit and the first switch, and the first signal circuit controls the first switch to be turned on or turned off through the first control part.
The first control part is internally provided with control logic, and the first signal circuit can be controlled by the control logic of the first control part, so that the first switch is turned on or off according to the control logic of the first control part.
In practical applications, the first control element may comprise an or gate logic circuit, the control logic of which is as follows:
as long as one of the input signals is at a high level (logic '1', i.e. enable signal), the output signal is at a high level, and the first switch can be opened; the first switch is turned off only when all the input signals are low (logic "0", i.e., off signal) and the output signal is low.
In a specific implementation, four motherboards may be provided.
Through setting up four mainboards, form the storage control frame of a frame four accuse to promote storage device's reliability, even after three of them trouble of four mainboards, utilize remaining mainboard still can provide customer's normal service.
In practical applications, the interface card may further include a data distribution algorithm module and/or an EBOF module.
By arranging the algorithm module and/or the EBOF module, the interface card can receive the service data of the front-end server and forward the service data to the EBOF network disk cabinet, thereby providing a service data flow path.
Step 502, when the power-off requirement of the interface card is detected, a shutdown signal is sent to the interface card through any one mainboard to control the disconnection of a second power circuit between the interface card and the PCIe chip, so that the PCIe chip is powered off independently under the condition that the interface card remains powered on.
When the power-off requirement of the interface card is detected, in order to avoid the influence of other services, a shutdown signal is sent to the interface card through any mainboard, so that the disconnection of a second power circuit between the interface card and the PCIe chip is controlled, and the PCIe chip is powered off independently under the condition that the interface card is kept powered on.
In one embodiment of the present application, the power down requirement includes an upgrade failure and/or a business requirement.
When the interface card fails to be upgraded or needs to be subjected to business, the PCIe chip needs to be powered off, so that faults are eliminated, and business requirements are met.
In an embodiment of the present application, after powering down the PCIe chip alone while the interface card remains powered up in step 502, the method may further include the steps of:
and performing repair operation on the PCIe chip.
After the repair operation for the PCIe chip is completed, the motherboard that sends the shutdown signal to the interface card in step 502 may send an enable signal to the interface card to control the second power circuit between the interface card and the PCIe chip to be reconnected, so that the PCIe chip is powered on again.
In the embodiment of the application, the storage device is provided with an interface card, the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected with the PCIe chip, under the condition that any one PCIe interface is inserted into the mainboard, a power supply of the mainboard is connected with the interface card through a first power circuit, the interface card is connected with the PCIe chip through a second power circuit, the mainboard is provided with a first signal circuit, when any one PCIe interface is inserted into the mainboard, the first signal circuit is called by the mainboard to send an enabling signal to the interface card so as to control the power supply of the mainboard to be communicated with the interface card through the first power circuit and communicated with the PCIe chip through the second power circuit, and the interface card and the PCIe chip are powered on; when the power-off demand of the interface card is detected, a closing signal is sent to the interface card through any one mainboard, so that a second power circuit between the control interface card and the PCIe chip is disconnected, the PCIe chip is powered off independently under the condition that the interface card is powered on, the independent power-off repair of the PCIe chip is realized, the normal operation of other services is ensured, the operation cost is reduced, the quality reinforcement is carried out on a service path, and the reliability and the self-healing capacity of a product are improved.
Referring to fig. 6, a flowchart illustrating steps of another embodiment of a control method based on a PCIe chip in a storage device according to the present application is shown, where the storage device is provided with an interface card, the interface card is provided with the PCIe chip and multiple PCIe interfaces connected to the PCIe chip, and when any one PCIe interface is inserted into a motherboard, a power supply of the motherboard is connected to an interface card through a first power circuit, the interface card is connected to the PCIe chip through a second power circuit, and the motherboard is provided with a second signal circuit, where the method may include the following steps:
step 601, when any PCIe interface is inserted into the mainboard, an enable signal is sent to the interface card through the mainboard, so that a power supply of the mainboard is controlled to be communicated with the interface card through the first power circuit and communicated with the PCIe chip through the second power circuit, and the interface card and the PCIe chip are powered on.
When any one PCIe interface is inserted into the mainboard, the interface card needs to be powered on, so that a service data flow path is provided for the mainboard, an enable signal is sent to the interface card through the mainboard, the power supply of the mainboard is controlled to be communicated with the interface card through the first power circuit, and the interface card and the PCIe chip are powered on through the second power circuit and the PCIe chip.
In a specific implementation, the number of the main boards may be four.
By arranging the four mainboards, the storage control frame with one frame and four controls is formed, so that the reliability of the storage device is improved, and even if three of the four mainboards fail, the normal service of a client can be provided by using the remaining one mainboard.
In practical applications, the interface card may further include a data distribution algorithm module and/or an EBOF module.
By arranging the algorithm module and/or the EBOF module, the interface card can bear the service data of the front-end server and forward the service data to the EBOF network disk cabinet, thereby providing a service data flow path.
Step 602, when a power-off requirement of the interface card is detected, calling a second signal circuit through any one motherboard to send a shutdown signal to the interface card so as to control a second power circuit between the interface card and the PCIe chip to be disconnected, so that the PCIe chip is powered off independently when the interface card is powered on.
The second signal circuit is used for controlling the connection or disconnection of the second power supply circuit, so that the control of the second power supply circuit can be completed through the second signal circuit, and the influence on the control of the first power supply circuit is avoided.
When the power-off requirement of the interface card is detected, in order to avoid influence of other services, the second signal circuit is called by any mainboard to send a closing signal to the interface card so as to control the disconnection of the second power circuit between the interface card and the PCIe chip, and the PCIe chip is powered off independently under the condition that the interface card is kept powered on.
In an embodiment of the present application, a second switch is disposed on the second power circuit, and the second signal circuit is connected to the second switch to control the second switch to be turned on or off, and the step 602 of calling the second signal circuit through any one motherboard to send the off signal to the interface card may include the following sub-steps:
and a substep 21 of calling a second signal circuit through any one of the mainboards to send a closing signal to the second switch to close the second switch.
Through setting up the second switch, be more convenient for control second power supply circuit's switching on or disconnection, accurately realize the control of independently going down under the circumstances that keeps the power on to the PCIe chip to the interface card.
In a specific implementation, a second control piece is further arranged between the second signal circuit and the second switch, and the second signal circuit controls the second switch to be turned on or turned off through the second control piece.
The second control part is internally provided with control logic, and the second signal circuit can be controlled by the control logic of the second control part, so that the second switch is turned on or off according to the control logic of the second control part.
In practical applications, the second control element may comprise an and gate logic circuit, the control logic of which is as follows:
when all the input signals are at high level (logic '1', namely enable signals) at the same time, the output signals are at high level, and the second switch can be opened; as long as one of the input signals is low (logic "0", i.e. close signal), the output signal is low, which closes the second switch.
In an embodiment of the present application, the power-off requirement includes upgrade failure and/or business requirement.
When the interface card fails to be upgraded or needs to be subjected to business, the PCIe chip needs to be powered off, so that faults are eliminated, and business requirements are met.
In an embodiment of the present application, after powering down the PCIe chip alone while the interface card remains powered up in step 602, the method may further include the steps of:
and performing repair operation on the PCIe chip.
After the repair operation for the PCIe chip is completed, the motherboard that sends the shutdown signal to the interface card in step 602 may send an enable signal to the interface card to control the second power circuit between the interface card and the PCIe chip to be reconnected, so that the PCIe chip is powered on again.
In the embodiment of the application, the storage device is provided with an interface card, the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected with the PCIe chip, under the condition that any one PCIe interface is inserted into the mainboard, a power supply of the mainboard is connected with the interface card through a first power circuit, the interface card is connected with the PCIe chip through a second power circuit, the mainboard is provided with a second signal circuit, when any one PCIe interface is inserted into the mainboard, an enabling signal is sent to the interface card through the mainboard, so that the power supply of the mainboard is controlled to be communicated with the interface card through the first power circuit and communicated with the PCIe chip through the second power circuit, and the interface card and the PCIe chip are powered on; when the power-off demand of the interface card is detected, the second signal circuit is called through any one mainboard to send a closing signal to the interface card, so that the second power circuit between the control interface card and the PCIe chip is disconnected, the PCIe chip is powered off independently under the condition that the interface card is powered on, the independent power-off repair of the PCIe chip is realized, the normal operation of other services is ensured, the operation cost is reduced, the quality reinforcement is carried out on a service path, and the reliability and the self-healing capacity of a product are improved.
Referring to fig. 7, a flowchart illustrating steps of another embodiment of a control method based on a PCIe chip in a storage device according to the present application is shown, where the storage device is provided with an interface card, the interface card is provided with the PCIe chip and multiple PCIe interfaces connected to the PCIe chip, and when any one PCIe interface is inserted into a motherboard, a power supply of the motherboard is connected to an interface card through a first power circuit, the interface card is connected to the PCIe chip through a second power circuit, and the motherboard is provided with a programmable logic device, where the method may include the following steps:
step 701, when any PCIe interface is inserted into the motherboard, sending a first control signal to the programmable logic device, so that the programmable logic device sends an enable signal to the interface card, so as to control the power supply of the motherboard to be communicated with the interface card through the first power circuit, and to be communicated with the PCIe chip through the second power circuit, so that the interface card and the PCIe chip are powered on.
When any PCIe interface is inserted into the mainboard, the interface card needs to be powered on, so that a service data flow path is provided for the mainboard, a first control signal is sent to the programmable logic unit, the programmable logic unit sends an enabling signal to the interface card, a power supply source of the mainboard is controlled to be communicated with the interface card through the first power circuit, and is communicated with the PCIe chip through the second power circuit, and the interface card and the PCIe chip are powered on.
In a specific implementation, four motherboards may be provided.
Through setting up four mainboards, form the storage control frame of a frame four accuse to promote storage device's reliability, even after three of them trouble of four mainboards, utilize remaining mainboard still can provide customer's normal service.
In practical applications, the interface card may further include a data distribution algorithm module and/or an EBOF module.
By arranging the algorithm module and/or the EBOF module, the interface card can receive the service data of the front-end server and forward the service data to the EBOF network disk cabinet, thereby providing a service data flow path.
Step 702, when the power-off requirement of the interface card is detected, sending a second control signal to any one of the programmable logic units, so that any one of the programmable logic units sends a shutdown signal to the interface card to control a second power circuit between the interface card and the PCIe chip to be disconnected, so that the PCIe chip is powered off independently under the condition that the interface card is powered on.
When the power-off requirement of the interface card is detected, in order to avoid the influence of other services, a second control signal is sent to any one programmable logic unit, and any one programmable logic unit sends a closing signal to the interface card so as to control a second power circuit between the interface card and the PCIe chip to be disconnected, and therefore the PCIe chip is powered off independently under the condition that the interface card is kept powered on.
In one embodiment of the present application, the power down requirement includes an upgrade failure and/or a business requirement.
When the interface card fails to be upgraded or needs to be subjected to business, the PCIe chip needs to be powered off, so that faults are eliminated, and business requirements are met.
In an embodiment of the present application, after powering down the PCIe chip alone while the interface card remains powered up in step 702, the method may further include the steps of:
and performing repair operation on the PCIe chip.
After the repair operation for the PCIe chip is completed, the motherboard that sends the shutdown signal to the interface card in step 702 may send an enable signal to the interface card to control the second power circuit between the interface card and the PCIe chip to be reconnected, so that the PCIe chip is powered on again.
By setting the programmable logic device, different signal paths can be selected according to different control signals, corresponding control is accurately completed, and the influence of error control on the normal operation of the service is avoided.
In a specific implementation, the programmable logic device can be set as a CPLD, so as to deal with various control logics to meet various control requirements.
In the embodiment of the application, the storage device is provided with an interface card, the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected with the PCIe chip, under the condition that any one PCIe interface is inserted into a mainboard, a power supply of the mainboard is connected with the interface card through a first power circuit, the interface card is connected with the PCIe chip through a second power circuit, and the mainboard is provided with a programmable logic unit; when the power-off requirement of the interface card is detected, a second control signal is sent to any one programmable logic device, the programmable logic device sends a closing signal to the interface card, the second power circuit between the interface card and the PCIe chip is controlled to be disconnected, the PCIe chip is powered off independently under the condition that the interface card is powered on, independent power-off repair of the PCIe chip is achieved, normal operation of other services is guaranteed, operation cost is reduced, quality reinforcement is conducted on a service path, and reliability and self-healing capacity of a product are improved.
It should be noted that for simplicity of description, the method embodiments are described as a series of acts, but those skilled in the art should understand that the embodiments are not limited by the described order of acts, as some steps can be performed in other orders or simultaneously according to the embodiments. Further, those skilled in the art will also appreciate that the embodiments described in the specification are presently preferred and that no particular act is required of the embodiments of the application.
Referring to fig. 8, it shows that the embodiment of the present application also discloses a structural block diagram of an embodiment of a control apparatus based on a PCIe chip in a storage device, where the storage device is provided with an interface card, the interface card is provided with the PCIe chip and a plurality of PCIe interfaces connected to the PCIe chip, and when any one PCIe interface is inserted into the motherboard, a power supply of the motherboard is connected to the interface card through a first power circuit, and the interface card is connected to the PCIe chip through a second power circuit, and the apparatus may include the following modules:
the power-on module 801 is used for sending an enable signal to the interface card through the mainboard when any one PCIe interface is inserted into the mainboard, so as to control the power supply of the mainboard to be communicated with the interface card through the first power circuit and be communicated with the PCIe chip through the second power circuit, and power on the interface card and the PCIe chip is enabled.
In an embodiment of the present application, the motherboard may be provided with a first signal circuit, and the power-on module 801 may include the following sub-modules:
the first signal circuit submodule is used for calling the first signal circuit through the mainboard to send an enabling signal to the interface card so as to control the power supply of the mainboard to be communicated with the interface card through the first power circuit; the first signal circuit is used for controlling connection or disconnection of the first power supply circuit.
In an embodiment of the present application, a first switch may be disposed on the first power circuit, and the first signal circuit is connected to the first switch to control the first switch to be turned on or off, and the first signal circuit sub-module may include the following sub-units:
and the first switch subunit is used for calling the first signal circuit through the mainboard to send an enabling signal to the first switch so as to open the first switch.
In an embodiment of the present application, a programmable logic device may be disposed on a motherboard, and the power-on module 801 may further include the following sub-modules:
and the first control logic submodule is used for sending a first control signal to the programmable logic device so that the programmable logic device sends an enabling signal to the interface card.
The independent power-off module 802 is configured to send a shutdown signal to the interface card through any one motherboard when a power-off requirement of the interface card is detected, so as to control a second power circuit between the interface card and the PCIe chip to be disconnected, so that the PCIe chip is powered off independently when the interface card remains powered on.
In an embodiment of the present application, the motherboard is provided with a second signal circuit, and the single power-down module 802 may include the following sub-modules:
the second signal circuit submodule is used for calling a second signal circuit through any mainboard to send a closing signal to the interface card so as to control the disconnection of a second power supply circuit between the interface card and the PCIe chip; the second signal circuit is used for controlling connection or disconnection of the second power supply circuit.
In an embodiment of the present application, a second switch is disposed on the second power circuit, the second signal circuit is connected to the second switch to control the second switch to be turned on or off, and the second signal circuit sub-module may include the following sub-units:
and the second switch subunit is used for calling the second signal circuit through any one mainboard to send a closing signal to the second switch so as to close the second switch.
In an embodiment of the present application, a programmable logic device may be disposed on the motherboard, and the separate power down module 802 may further include the following sub-modules:
and the second control logic submodule is used for sending a second control signal to any one programmable logic unit so that any one programmable logic unit sends a closing signal to the interface card.
In another embodiment of the present application, the apparatus may further include the following modules:
and the chip repair module is used for repairing the PCIe chip.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The embodiment of the present application also provides an electronic device, which may include a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and when the computer program is executed by the processor, the steps of the control method based on the PCIe chip in the storage device as described above are implemented.
The embodiment of the present application further provides a computer non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the control method based on the PCIe chip in the storage device are implemented.
The embodiments in the present specification are all described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same and similar between the embodiments may be referred to each other.
As will be appreciated by one of skill in the art, embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage devices, CD-ROMs, optical storage devices, etc.) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory device that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory device produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the true scope of the embodiments of the application.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrases "comprising one of \ 8230; \8230;" does not exclude the presence of additional like elements in a process, method, article, or terminal device that comprises the element.
The foregoing describes in detail a control method and apparatus based on a PCIe chip in a storage device, where a specific example is applied to illustrate principles and embodiments of the present application, and the description of the foregoing embodiment is only used to help understand the method and core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (20)

1. A control method based on PCIe chips in storage equipment is characterized in that the storage equipment is provided with an interface card, the interface card is provided with the PCIe chips and a plurality of PCIe interfaces connected with the PCIe chips, under the condition that any one PCIe interface is inserted into a mainboard, a power supply of the mainboard is connected with a first power circuit of the interface card, the interface card is connected with the PCIe chips through a second power circuit, and the method comprises the following steps:
when any PCIe interface is inserted into the mainboard, an enabling signal is sent to the interface card through the mainboard so as to control a power supply of the mainboard to be communicated with the interface card through the first power circuit and communicated with the PCIe chip through the second power circuit, and the interface card and the PCIe chip are powered on;
when the power-off requirement of the interface card is detected, a shutdown signal is sent to the interface card through any one mainboard to control the disconnection of the second power circuit between the interface card and the PCIe chip, so that the PCIe chip is powered off independently under the condition that the interface card is kept powered on.
2. The method of claim 1, wherein a motherboard is provided with a first signal circuit, and the sending an enable signal to the interface card via the motherboard to control power of the motherboard to communicate with the interface card via the first power circuit comprises:
calling the first signal circuit through the mainboard to send an enabling signal to the interface card so as to control a power supply of the mainboard to be communicated with the interface card through the first power circuit; the first signal circuit is used for controlling connection or disconnection of the first power supply circuit.
3. The method of claim 2, wherein a first switch is disposed on the first power circuit, the first signal circuit is connected to the first switch to control the first switch to be turned on or off, and the invoking of the first signal circuit by the motherboard to send the enable signal to the interface card comprises:
and calling the first signal circuit through a mainboard to send an enabling signal to the first switch so as to open the first switch.
4. The method of claim 3, wherein a first control element is further disposed between the first signal circuit and the first switch, and the first signal circuit controls the first switch to be turned on or off through the first control element.
5. The method of claim 4, wherein the first control comprises OR gate logic.
6. The method of claim 1, wherein a second signal circuit is provided on a motherboard, and wherein sending a shutdown signal to the interface card via any of the motherboards to control disconnection of the second power circuit between the interface card and the PCIe chip comprises:
calling the second signal circuit through any one mainboard to send a shutdown signal to the interface card so as to control the disconnection of the second power supply circuit between the interface card and the PCIe chip; the second signal circuit is used for controlling connection or disconnection of the second power supply circuit.
7. The method according to claim 6, wherein a second switch is disposed on the second power circuit, the second signal circuit is connected to the second switch to control the second switch to be turned on or off, and the invoking of the second signal circuit by any one of the motherboards to send the off signal to the interface card comprises:
and calling the second signal circuit through any one mainboard to send a closing signal to the second switch so as to close the second switch.
8. The method of claim 7, wherein a second control element is further disposed between the second signal circuit and the second switch, and the second signal circuit controls the second switch to be turned on or off through the second control element.
9. The method of claim 8, wherein the second control comprises and gate logic.
10. The method of claim 1, wherein the motherboard has programmable logic disposed thereon.
11. The method of claim 10, wherein sending an enable signal to the interface card via the motherboard comprises:
and sending a first control signal to the programmable logic device to enable the programmable logic device to send an enabling signal to the interface card.
12. The method of claim 10, wherein said sending a shutdown signal to said interface card via any of the motherboards comprises:
and sending a second control signal to any one of the programmable logic devices to enable any one of the programmable logic devices to send a closing signal to the interface card.
13. The method of any one of claims 1 to 12, wherein the power down requirements include upgrade failures and/or business requirements.
14. The method of any of claims 1-12, wherein after said powering down the PCIe chip alone with the interface card remaining powered up, the method further comprises:
and repairing the PCIe chip.
15. Method according to any of claims 1 to 12, characterized in that four main boards are provided.
16. The method of any of claims 1 to 12, wherein the interface card further comprises a data distribution algorithm module and/or an EBOF module.
17. The method according to any one of claims 3 to 5, wherein an overload fuse is provided between a power supply of the main board and the first switch.
18. The utility model provides a controlling means based on PCIe chip in storage device, its characterized in that, storage device is provided with the interface card, the interface card be provided with the PCIe chip and with a plurality of PCIe interfaces that the PCIe chip is connected, under the condition that the mainboard inserts arbitrary one PCIe interface, the power supply of mainboard with the first power supply circuit of interface card links to each other, the interface card with the PCIe chip passes through the second power supply circuit and links to each other, the device includes:
the power-on module is used for sending an enabling signal to the interface card through the mainboard when any PCIe interface is inserted into the mainboard, so as to control a power supply of the mainboard to be communicated with the interface card through the first power supply circuit and communicated with the PCIe chip through the second power supply circuit, and power-on of the interface card and the PCIe chip is realized;
and the independent power-off module is used for sending a closing signal to the interface card through any mainboard when the power-off requirement of the interface card is detected so as to control the disconnection of the second power circuit between the interface card and the PCIe chip and enable the PCIe chip to be powered off independently under the condition that the interface card is kept powered on.
19. An electronic device, comprising a processor, a storage device, and a computer program stored on the storage device and capable of running on the processor, the computer program, when executed by the processor, implementing the steps of the method according to any one of claims 1 to 17.
20. A computer non-transitory readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 17.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116880658A (en) * 2023-07-25 2023-10-13 成都电科星拓科技有限公司 Low-power consumption PCIe (peripheral component interconnect express) repeater chip and design method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113419618A (en) * 2021-06-18 2021-09-21 苏州浪潮智能科技有限公司 Server decoding card power-off control method, system, terminal and storage medium
CN113645049A (en) * 2021-07-30 2021-11-12 苏州浪潮智能科技有限公司 Network card electrifying method, system, storage medium and equipment
CN115017079A (en) * 2022-05-31 2022-09-06 深圳市商汤科技有限公司 Power-off method of management equipment, chip, PCIe card and business processing equipment
CN115269474A (en) * 2021-04-29 2022-11-01 济南宇视智能科技有限公司 Server and PCIe hot plug control method, device and medium thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115269474A (en) * 2021-04-29 2022-11-01 济南宇视智能科技有限公司 Server and PCIe hot plug control method, device and medium thereof
CN113419618A (en) * 2021-06-18 2021-09-21 苏州浪潮智能科技有限公司 Server decoding card power-off control method, system, terminal and storage medium
CN113645049A (en) * 2021-07-30 2021-11-12 苏州浪潮智能科技有限公司 Network card electrifying method, system, storage medium and equipment
CN115017079A (en) * 2022-05-31 2022-09-06 深圳市商汤科技有限公司 Power-off method of management equipment, chip, PCIe card and business processing equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116880658A (en) * 2023-07-25 2023-10-13 成都电科星拓科技有限公司 Low-power consumption PCIe (peripheral component interconnect express) repeater chip and design method thereof
CN116880658B (en) * 2023-07-25 2024-03-29 成都电科星拓科技有限公司 Low-power consumption PCIe (peripheral component interconnect express) repeater chip and design method thereof

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