CN110109715A - A kind of system and method for server security starting - Google Patents
A kind of system and method for server security starting Download PDFInfo
- Publication number
- CN110109715A CN110109715A CN201910382054.1A CN201910382054A CN110109715A CN 110109715 A CN110109715 A CN 110109715A CN 201910382054 A CN201910382054 A CN 201910382054A CN 110109715 A CN110109715 A CN 110109715A
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- Prior art keywords
- spi
- fpga
- chip
- cpld
- bmc
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Storage Device Security (AREA)
- Stored Programmes (AREA)
Abstract
The invention proposes a kind of systems of server security starting, which includes FPGA, CPLD and SPI Switch.FPGA save Standard firmware file, and with do and switch with BMC spi bus and PCH spi bus respectively, before booting detect ROM file in FPGA the key and image file of burning it is whether identical；CPLD chip controls whether to be switched on by SPI Switch according to FPGA testing result；Based on system proposed by the present invention, it is also proposed that the method for clean boot verifies successfully when the inspection signal that CPLD receives FPGA is high, the control bus of ROM is switched to BMC and PCH.When the FPGA that CPLD is received checks that signal is low, verification failure does not allow to be switched on.The chip that the present invention uses can self-programming, and cost is relatively low, software and hardware combining, enables server independently controllable clean boot.
Description
Technical field
The invention belongs to the technical field of server starting, in particular to the system of a kind of server security starting and side
Method.
Background technique
With the continuous development of computer technology with progress, server is widely used in each as high-performance computer
Field, for providing quick, accurate, safe calculating and storage service, due to server be generally used for operation key business and
Significant data is stored, so the safety of server is particularly important.
For the credible starting of server, TPM TPCM module is mainly used in the industry at present.Module manufacturers only have Infineon
It is expensive Deng a small number of manufacturers, and technology is closed, the research and development participation of manufacturer server is lower, and independence is poor.Existing scheme master
If server master board reserves TPM/TPCM card interface, purchase TPM/TPCM card is used to support credible starting.TPM/TPCM card by
Specialized vendor's design, software and hardware all compare closing, can not accomplish autonomous controllable and expensive.
Summary of the invention
The invention proposes a kind of system and method for server security starting can make to service using software and hardware combining
Device starting is safely controllable, and cost reduces.
To achieve the goals above, the system of a kind of server security starting proposed by the present invention: including fpga chip,
CPLD chip and SPI Switch chip；
The fpga chip for saving BMC Standard firmware file and BIOS Standard firmware file, and with respectively with BMC
Spi bus and the spi bus of PCH do and switch, while detect before booting BMC ROM file and BIOS ROM file with
Whether the key and image file of burning are identical in fpga chip；The CPLD chip is used for the result detected according to fpga chip
It controls whether to be switched on by SPI Switch chip；
The fpga chip is connected by spi bus with SPI Switch chip；The CPLD chip is switched by SPI to be believed
Number with SPI Switch chip communication.
Further, the system also includes physics jump caps；
The physics jump cap is used to be arranged the write-protect pin of FPGA.
Further, the SPI Switch chip includes the first SPI Switch chip and the 2nd SPI Switch core
Piece；
The fpga chip is connected by the first spi bus with the input terminal of the first SPI Switch chip；The FPGA
Chip also passes through the second spi bus and is connected with the 2nd SPI Switch chip input terminal；The CPLD chip is cut by the first SPI
Change signal and the first SPI Switch chip communication；The CPLD chip also passes through the 2nd SPI switching signal and the 2nd SPI
Switch chip communication.
Further, the output end of the first SPI Switch chip passes through third spi bus and BMC and BMC respectively
ROM is connected；The output end of the 2nd SPI Switch chip passes through the 4th spi bus respectively and is connected with PCH and PCH ROM.
Further, the first SPI Switch chip is used to switch the first spi bus of FPGA and the third of BMC
Spi bus；
The 2nd SPI Switch chip is used to switch the second spi bus of FPGA and the 4th spi bus of PCH.
A kind of method of server security starting is that the system based on a kind of starting of server security is realized, the method
The following steps are included:
FPGA saves BMC Standard firmware file and BIOS Standard firmware file；
Use the write-protect pin of physics jump cap setting FPGA；
Fpga chip constructs SPI controller and provides 2 spi bus interfaces, the switching of the first SPI Switch chip
The first spi bus of FPGA and the third spi bus of BMC；2nd SPI Switch chip switch FPGA the second spi bus and
The 4th spi bus of PCH；
CPLD chip controls whether to be switched on by the first SPI Switch chip of control and the 2nd SPI Switch chip.
Further, the method for the write-protect pin using physics jump cap setting FPGA includes:
When physics jump cap is connected to 2 and 3 pin, FPGA is in write-protect state；
When physics jump cap is connected to 1 and 2 pin, FPGA write-protect is inactive.
Further, the CPLD chip by control the first SPI Switch chip and the 2nd SPI Switch chip come
The method for controlling whether booting includes, when the inspection OK signal that CPLD receives FPGA is high, BMC ROM file and BIOS
ROM file verifies successfully, and CPLD exports the first SPI switching signal and the 2nd SPI switching signal, and the control bus of ROM is switched
To BMC and PCH.When the FPGA that CPLD is received checks that OK signal is low, authentication check is unsuccessful, when CPLD control powers on
Sequence does not allow to be switched on.
The effect provided in summary of the invention is only the effect of embodiment, rather than invents all whole effects, above-mentioned
A technical solution in technical solution have the following advantages that or the utility model has the advantages that
The embodiment of the present invention proposes a kind of system and method for server security starting, which includes fpga chip,
CPLD chip and SPI Switch chip.Fpga chip is used to save BMC Standard firmware file and BIOS Standard firmware file, with
And switch with being done respectively with the spi bus of the spi bus of BMC and PCH, while BMC ROM file and BIOS are detected before booting
ROM file in fpga chip the key and image file of burning it is whether identical；CPLD chip according to fpga chip for examining
The result of survey controls whether to be switched on by SPI Switch chip；Fpga chip passes through spi bus and SPI Switch chip
It is connected；CPLD chip uses the write-protect of physics jump cap setting FPGA by SPI switching signal and SPI Switch chip communication
Pin.When the inspection OK signal that CPLD receives FPGA is high, BMC ROM file and BIOS ROM file are verified successfully,
CPLD exports the first SPI switching signal and the 2nd SPI switching signal, and the control bus of ROM is switched to BMC and PCH.Work as CPLD
When the FPGA received checks that OK signal is low, authentication check is unsuccessful, and CPLD controls electrifying timing sequence, does not allow to be switched on.This hair
The bright fpga chip used can self-programming, and cost is relatively low, software and hardware combining, and enabling server, independently controllable safety opens
It is dynamic, promote product competitiveness and corporate image.
Detailed description of the invention
Attached drawing 1 is a kind of system connection figure for server security starting that the embodiment of the present invention 1 proposes；
Attached drawing 2 is a kind of method flow diagram of server security starting proposed based on the embodiment of the present invention 1.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that, term " longitudinal direction ", " transverse direction ", "upper", "lower", "front", "rear",
The orientation or positional relationship of the instructions such as "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" is based on attached drawing institute
The orientation or positional relationship shown is merely for convenience of the description present invention, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
Embodiment 1
The embodiment of the present invention 1 proposes a kind of system of server security starting, including fpga chip, CPLD chip and
SPI Switch chip.
Wherein, fpga chip is for saving BMC Standard firmware file and BIOS Standard firmware file, and with respectively with
The spi bus of BMC and the spi bus of PCH do and switch, at the same detect before booting BMC ROM file and BIOS ROM file with
Whether the key and image file of burning are identical in fpga chip；
The result that CPLD chip is used to be detected according to fpga chip controls whether to be switched on by SPI Switch chip；
Fpga chip is connected by spi bus with SPI Switch chip；CPLD chip passes through SPI switching signal and SPI
Switch chip communication.
The system of server security starting further includes physics jump cap, and the write-protect using physics jump cap setting FPGA is drawn
Foot.
SPI Switch chip includes the first SPI Switch chip and the 2nd SPI Switch chip；
Fpga chip is connected by the first spi bus with the input terminal of the first SPI Switch chip；Fpga chip is also logical
The second spi bus is crossed to be connected with the 2nd SPI Switch chip input terminal；CPLD chip passes through the first SPI switching signal and first
SPI Switch chip communication；CPLD chip also passes through the 2nd SPI switching signal and the 2nd SPI Switch chip communication.
The output end of first SPI Switch chip passes through third spi bus respectively and is connected with BMC and BMC ROM；Second
The output end of SPI Switch chip passes through the 4th spi bus respectively and is connected with PCH and PCH ROM.
First SPI Switch chip is used to switch the first spi bus of FPGA and the third spi bus of BMC；
2nd SPI Switch chip is used to switch the second spi bus of FPGA and the 4th spi bus of PCH.
The system connection figure started such as a kind of Fig. 1 server security for giving the proposition of the embodiment of the present invention 1.
The Standard firmware file of BMC and BIOS is saved using fpga chip.
The write-protect pin default physics jump cap that FPGA is arranged using a physics jump cap is connected to 2-3 pin, at this time
FPGA is in write-protect state, does not allow to change the programming file of FPGA；When needs more new key and image file are, by physics
Jump cap is connected to 1-2 pin, and FPGA write-protect at this time is inactive, can be with normal refresh FPGA file.
1 pin of physics jump cap is connected with Vcc, and 2 pins of physics jump cap are grounded by resistance R2 all the way, and in addition one
Road is connected with fpga chip.
2 SPI controllers are constructed using fpga chip, the first spi bus interface and the second spi bus interface are provided.
Fpga chip is connected by the first spi bus with the first SPI Switch chip input terminal, and fpga chip passes through the
Two spi bus are connected with the 2nd SPI Switch chip input terminal.The output end of first SPI Switch chip passes through respectively
Three spi bus are connected with BMC and BMC ROM；The output end of 2nd SPI Switch chip pass through respectively the 4th spi bus with
PCH with PCH ROM is connected.First SPI Switch chip be used for switch FPGA the first spi bus and BMC the 3rd SPI it is total
Line；2nd SPI Switch chip is used to switch the second spi bus of FPGA and the 4th spi bus of PCH.
The first SPI Switch chip and the 2nd SPI Switch chip are controlled using CPLD.
A kind of system based on a kind of server security starting that the embodiment of the present invention 1 proposes, it is also proposed that server peace
The method started entirely.
Fpga chip saves BMC Standard firmware file and BIOS Standard firmware file；
Use the write-protect pin of physics jump cap setting FPGA；
Fpga chip constructs SPI controller and provides 2 spi bus interfaces, the switching of the first SPI Switch chip
The first spi bus of FPGA and the third spi bus of BMC；2nd SPI Switch chip switch FPGA the second spi bus and
The 4th spi bus of PCH；
CPLD chip controls whether to be switched on by the first SPI Switch chip of control and the 2nd SPI Switch chip.
When the inspection OK signal that CPLD receives FPGA is high, BMC ROM file and BIOS ROM file are verified successfully, CPLD output
The control bus of ROM is switched to BMC and PCH by the first SPI switching signal and the 2nd SPI switching signal.It is received as CPLD
When FPGA checks that OK signal is low, authentication check is unsuccessful, and CPLD controls electrifying timing sequence, does not allow to be switched on.
As Fig. 2 gives the method flow diagram that a kind of server security proposed based on the embodiment of the present invention 1 is started.
In step s 201, the process is started to process；
In step S202, BMC Standard firmware file and BIOS Standard firmware file are saved using FPGA；
In step S203, using the write-protect pin of physics jump cap setting FPGA, draw when physics jump cap is connected to 2 and 3
When foot, FPGA is in write-protect state；When physics jump cap is connected to 1 and 2 pin, FPGA write-protect is inactive.
In step S204, SPI controller is constructed using fpga chip and 2 spi bus interfaces, the first SPI are provided
Switch chip switches the first spi bus of FPGA and the third spi bus of BMC；2nd SPI Switch chip switches FPGA
The second spi bus and PCH the 4th spi bus；
In step S205, judge that CPLD receives the inspection OK signal of FPGA as high level or low level；Work as CPLD
When the inspection OK signal for receiving FPGA is high level, step S206 is executed；When the inspection OK signal that CPLD receives FPGA is
When low level, step S207 is executed.
In step S206, BMC ROM file and BIOS ROM file are verified successfully, and CPLD exports the first SPI switching letter
Number and the 2nd SPI switching signal, the control bus of ROM is switched to BMC and PCH.
In step S207, authentication check is unsuccessful, and CPLD controls electrifying timing sequence, does not allow to be switched on.
In step S208, whole flow process terminates.
Above content is only to structure example of the invention and explanation, affiliated those skilled in the art
It makes various modifications or additions to the described embodiments or is substituted in a similar manner, without departing from invention
Structure or beyond the scope defined by this claim, be within the scope of protection of the invention.
Claims (8)
1. a kind of system of server security starting, which is characterized in that including fpga chip, CPLD chip and SPI Switch core
Piece；
The fpga chip for saving BMC Standard firmware file and BIOS Standard firmware file, and with respectively with BMC's
The spi bus of spi bus and PCH, which are done, to be switched, at the same detect before booting BMC ROM file and BIOS ROM file in FPGA
Whether the key and image file of burning are identical in chip；The CPLD chip according to the result that fpga chip detects for passing through
SPI Switch chip controls whether to be switched on；
The fpga chip is connected by spi bus with SPI Switch chip；The CPLD chip by SPI switching signal with
SPI Switch chip communication.
2. a kind of system of server security starting according to claim 1, which is characterized in that the system also includes objects
Manage jump cap；
The physics jump cap is used to be arranged the write-protect pin of FPGA.
3. a kind of system of server security starting according to claim 1, which is characterized in that the SPI Switch core
Piece includes the first SPI Switch chip and the 2nd SPI Switch chip；
The fpga chip is connected by the first spi bus with the input terminal of the first SPI Switch chip；The fpga chip
Also it is connected by the second spi bus with the 2nd SPI Switch chip input terminal；The CPLD chip passes through the first SPI switching letter
Number with the first SPI Switch chip communication；The CPLD chip also passes through the 2nd SPI switching signal and the 2nd SPI Switch
Chip communication.
4. a kind of system of server security starting according to claim 3, which is characterized in that the first SPI
The output end of Switch chip passes through third spi bus respectively and is connected with BMC and BMC ROM；The 2nd SPI Switch core
The output end of piece passes through the 4th spi bus respectively and is connected with PCH and PCH ROM.
5. according to a kind of system of server security starting of claim 3 or 4, which is characterized in that the first SPI
Switch chip is used to switch the first spi bus of FPGA and the third spi bus of BMC；
The 2nd SPI Switch chip is used to switch the second spi bus of FPGA and the 4th spi bus of PCH.
6. a kind of method of server security starting, is opened based on a kind of server security described in claim 1 to 5 any one
What dynamic system was realized, which is characterized in that the described method comprises the following steps:
FPGA saves BMC Standard firmware file and BIOS Standard firmware file；
Use the write-protect pin of physics jump cap setting FPGA；
Fpga chip constructs SPI controller and provides 2 spi bus interfaces, and the first SPI Switch chip switches FPGA's
The third spi bus of first spi bus and BMC；2nd SPI Switch chip switches the second spi bus and PCH of FPGA
4th spi bus；
CPLD chip controls whether to be switched on by the first SPI Switch chip of control and the 2nd SPI Switch chip.
7. a kind of method of server security starting according to claim 6, which is characterized in that described to use physics jump cap
The method that the write-protect pin of FPGA is arranged includes:
When physics jump cap is connected to 2 and 3 pin, FPGA is in write-protect state；
When physics jump cap is connected to 1 and 2 pin, FPGA write-protect is inactive.
8. a kind of method of server security starting according to claim 6, which is characterized in that the CPLD chip passes through
The method that the first SPI Switch chip and the 2nd SPI Switch chip are controlled to control whether booting includes, when CPLD is received
When inspection OK signal to FPGA is high, BMC ROM file and BIOS ROM file are verified successfully, and CPLD exports the first SPI and cuts
Signal and the 2nd SPI switching signal are changed, the control bus of ROM is switched to BMC and PCH.When the FPGA that CPLD is received is checked
When OK signal is low, authentication check is unsuccessful, and CPLD controls electrifying timing sequence, does not allow to be switched on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910382054.1A CN110109715A (en) | 2019-05-08 | 2019-05-08 | A kind of system and method for server security starting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910382054.1A CN110109715A (en) | 2019-05-08 | 2019-05-08 | A kind of system and method for server security starting |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110109715A true CN110109715A (en) | 2019-08-09 |
Family
ID=67488994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910382054.1A Withdrawn CN110109715A (en) | 2019-05-08 | 2019-05-08 | A kind of system and method for server security starting |
Country Status (1)
| Country | Link |
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| CN (1) | CN110109715A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110647429A (en) * | 2019-09-30 | 2020-01-03 | 联想(北京)有限公司 | Electronic equipment, processing system and processing method |
| CN110781501A (en) * | 2019-10-10 | 2020-02-11 | 苏州浪潮智能科技有限公司 | Control circuit and server |
| CN111399880A (en) * | 2020-03-13 | 2020-07-10 | 浪潮商用机器有限公司 | PCIe Switch configuration system, method, device and medium |
| CN111399919A (en) * | 2020-03-06 | 2020-07-10 | 苏州浪潮智能科技有限公司 | Starting method and system of server, electronic equipment and storage medium |
| CN111666236A (en) * | 2020-06-13 | 2020-09-15 | 曙光信息产业(北京)有限公司 | Server and communication method |
| CN111859471A (en) * | 2020-06-12 | 2020-10-30 | 苏州浪潮智能科技有限公司 | System and method for realizing server system protection based on programmable device |
| CN112231145A (en) * | 2020-10-10 | 2021-01-15 | 苏州浪潮智能科技有限公司 | CPLD (Complex programmable logic device) -based switching structure and method for controlling BMC (baseboard management controller) restart |
| CN112817645A (en) * | 2021-01-26 | 2021-05-18 | 浪潮电子信息产业股份有限公司 | BIOS starting method, device, equipment and readable storage medium |
| CN113157304A (en) * | 2021-03-12 | 2021-07-23 | 山东英信计算机技术有限公司 | Server firmware updating device and method based on USB storage equipment |
| CN113392052A (en) * | 2021-06-11 | 2021-09-14 | 深圳市同泰怡信息技术有限公司 | BIOS system, method and computer readable storage medium based on four-way server |
| CN113448401A (en) * | 2021-05-28 | 2021-09-28 | 山东英信计算机技术有限公司 | Mainboard and server |
| CN114139168A (en) * | 2022-01-29 | 2022-03-04 | 苏州浪潮智能科技有限公司 | TPCM measuring method, device and medium |
| CN114416432A (en) * | 2022-03-29 | 2022-04-29 | 山东云海国创云计算装备产业创新中心有限公司 | Chip safe start detection method, device, equipment and medium |
-
2019
- 2019-05-08 CN CN201910382054.1A patent/CN110109715A/en not_active Withdrawn
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110647429A (en) * | 2019-09-30 | 2020-01-03 | 联想(北京)有限公司 | Electronic equipment, processing system and processing method |
| CN110781501A (en) * | 2019-10-10 | 2020-02-11 | 苏州浪潮智能科技有限公司 | Control circuit and server |
| CN111399919A (en) * | 2020-03-06 | 2020-07-10 | 苏州浪潮智能科技有限公司 | Starting method and system of server, electronic equipment and storage medium |
| CN111399880A (en) * | 2020-03-13 | 2020-07-10 | 浪潮商用机器有限公司 | PCIe Switch configuration system, method, device and medium |
| CN111859471A (en) * | 2020-06-12 | 2020-10-30 | 苏州浪潮智能科技有限公司 | System and method for realizing server system protection based on programmable device |
| CN111666236A (en) * | 2020-06-13 | 2020-09-15 | 曙光信息产业(北京)有限公司 | Server and communication method |
| CN112231145B (en) * | 2020-10-10 | 2022-05-31 | 苏州浪潮智能科技有限公司 | CPLD (Complex programmable logic device) -based switching structure and method for controlling BMC (baseboard management controller) restart |
| CN112231145A (en) * | 2020-10-10 | 2021-01-15 | 苏州浪潮智能科技有限公司 | CPLD (Complex programmable logic device) -based switching structure and method for controlling BMC (baseboard management controller) restart |
| CN112817645A (en) * | 2021-01-26 | 2021-05-18 | 浪潮电子信息产业股份有限公司 | BIOS starting method, device, equipment and readable storage medium |
| CN113157304A (en) * | 2021-03-12 | 2021-07-23 | 山东英信计算机技术有限公司 | Server firmware updating device and method based on USB storage equipment |
| CN113157304B (en) * | 2021-03-12 | 2024-02-06 | 山东英信计算机技术有限公司 | Device and method for updating server firmware based on USB storage device |
| CN113448401A (en) * | 2021-05-28 | 2021-09-28 | 山东英信计算机技术有限公司 | Mainboard and server |
| CN113392052A (en) * | 2021-06-11 | 2021-09-14 | 深圳市同泰怡信息技术有限公司 | BIOS system, method and computer readable storage medium based on four-way server |
| CN113392052B (en) * | 2021-06-11 | 2023-07-18 | 深圳市同泰怡信息技术有限公司 | BIOS system and method based on four-way server and computer readable storage medium |
| CN114139168A (en) * | 2022-01-29 | 2022-03-04 | 苏州浪潮智能科技有限公司 | TPCM measuring method, device and medium |
| CN114416432A (en) * | 2022-03-29 | 2022-04-29 | 山东云海国创云计算装备产业创新中心有限公司 | Chip safe start detection method, device, equipment and medium |
| CN114416432B (en) * | 2022-03-29 | 2022-07-08 | 山东云海国创云计算装备产业创新中心有限公司 | Chip safe start detection method, device, equipment and medium |
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Application publication date: 20190809 |